Rohm LAPIS SEMICONDUCTOR ML620Q503 User Manual

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Dear customer

LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1

day of October,

2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which

LAPIS established a new company, LAPIS Technology Co., Ltd. ("LAPIS

Technology") and LAPIS Technology succeeded LAPIS Semiconductor's LSI business.

Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"

and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."

Furthermore, there are no changes to the documents relating to our products other than

the company name, the company trademark, logo, etc.

Thank you for your understanding.

LAPIS Technology Co., Ltd.

October 1, 2020

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Page 1 Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1 day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"...
Page 2 FEUL620Q504-01 ML620Q503/Q504 User’s Manual Issue Date: Apr.16, 2015...
Page 3 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
Page 4 ML620Q503/Q504 User’s Manual Preface This manual describes the operation of the hardware of the 16-bit microcontroller ML620Q503/Q504. The following manuals are also available. Read them as necessary.  nX-U16/100 Core Instruction Manual Description on the basic architecture and the each instruction of the nX-U16/100 Core ...
Page 5 ML620Q503/Q504 User’s Manual Notation Classification Notation Description ♦ Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F Indicates a binary number; “b” may be omitted. x: A value 0 or 1 ♦...
Page 6: Table Of Contents
ML620Q503/Q504 User’s Manual Contents Table of Contents Chapter 1 1. Overview ............................1-1 1.1 Features ............................1-1 1.2 Configuration of Functional Blocks .................... 1-5 1.2.1 Block Diagram of ML620Q503/504 ................1-5 1.3 Pins ............................1.3.1 Pin Layout ........................1-6 1.3.1.1 Pin Layout of ML620Q503/Q504 TQFP Package ..........
Page 7 ML620Q503/Q504 User’s Manual Contents Chapter 4 4. Power Management.......................... 4-1 4.1 General Description ........................4.1.1 Features ........................4-1 4.1.2 Configuration ....................... 4-1 4.2 Description of Registers ........................ 4-2 4.2.1 Register Configuration List ..................4-2 4.2.2 Stop Code Acceptor (STPACP) .................. 4-3 4.2.3 Standby Control Register (SBYCON) .................
Page 8 ML620Q503/Q504 User’s Manual Contents Description of Operation ......................5-51 5.3.1 Interrupt Source ......................5-51 5.3.2 Maskable Interrupt Processing ................. 5-53 5.3.3 Non-Maskable Interrupt Processing ................. 5-53 5.3.4 Software Interrupt Processing .................. 5-53 5.3.5 Notes on Interrupt Routine..................5-54 5.3.6 Interrupt Processing When Interrupt Level Control Enabled ........5-58 5.3.7 Flow Chart (When Interrupt Level Control Enabled) ..........
Page 9 ML620Q503/Q504 User’s Manual Contents Chapter 8 8. Timers ............................... 8-1 Overview ............................8-1 8.1.1 Features ........................8-1 8.1.2 Configuration ....................... 8-1 Description of Registers ......................8-3 8.2.1 List of Registers ......................8-3 8.2.2 Timer n Data Register (TMnmD : {n,m}={0,1}, {2,3}, {4,5}, {6,7}) ......8-4 8.2.3 Timer n Counter Register (TMnmC : {n,m}={0,1}, {2,3}, {4,5}, {6,7}) ......
Page 10 ML620Q503/Q504 User’s Manual Contents 9.3.7 Event/Emergency Stop Trigger Control ..............9-42 9.3.7.1 Trigger Signal ..................... 9-42 9.3.7.2 Start/Stop Operations by EventTrigger ............9-43 9.3.7.3 Emergency StopOperation ................9-43 9.3.8 Output at Counter Stop ..................... 9-45 9.3.9 Changing Period, Event A/B, and Dead Time during Operation ......9-46 9.3.10 Interrupt Source ......................
Page 11 ML620Q503/Q504 User’s Manual Contents 12.3 Description of Operation ....................... 12.3.1 Master Mode and Slave Mode ................12-19 12.3.2 Control of Polarity and Phase of Serial Clock ............12-19 12.3.3 Data Transfer Timing When SF0CPHA Is "0" ............12-19 12.3.4 Data Transfer Timing When SF0CPHA Is "1" ............12-20 12.3.5 Serial Clock Baud Rate ..................
Page 12 ML620Q503/Q504 User’s Manual Contents Chapter 14 14. UART with FIFO (UARTF) ......................14-1 14.1 General Description ........................ 14.1.1 Features ........................14-1 14.1.2 Configuration ......................14-2 14.1.3 List of Pins ......................14-3 14.2 Description of Registers ......................14.2.1 List of Registers ...................... 14-3 14.2.2 UARTF0 Transmit/Receive Buffer (UAF0BUF) ............
Page 13 ML620Q503/Q504 User’s Manual Contents Chapter 16 16. Port XT ............................16-1 16.1 General Description ........................ 16.1.1 Features ........................16-1 16.1.2 Configuration ......................16-1 16.1.3 List of Pins ......................16-1 16.2 Description of Registers ......................16.2.1 List of Registers ...................... 16-2 16.2.2 Port XT Data Register (PXTD) ................
Page 14 ML620Q503/Q504 User’s Manual Contents 19.2.1 List of Registers ...................... 19-3 19.2.2 Port 2 Data Register (P2D) ..................19-4 19.2.3 Port 2 Direction Register (P2DIR) ................19-5 19.2.4 Port 2 Control Registers (P2CON) ................. 19-6 19.2.5 Port 2 Mode Registers (P2MOD) ................19-8 19.3 Description of Operation .......................
Page 15 ML620Q503/Q504 User’s Manual Contents 22.2.4 Port 5 Control Register (P5CON) ................22-9 22.2.5 Port 5 Mode Register (P5MOD) ................22-12 22.3 Description of Operation ....................... 22.3.1 Input/Output Port Functions .................. 22-15 22.3.2 Primary Function Other Than Input/Output Port........... 22-15 22.3.3 Secondary to Quartic Functions ................22-15 Chapter 23 23.
Page 16 ML620Q503/Q504 User’s Manual Contents 25.2.2 SA-ADC Result Register n (SADRn) n=0 to 9, A, B ..........25-4 25.2.3 SA-ADC Control Register 0(SADCON0) ..............25-5 25.2.4 SA-ADC Control Register1 (SADCON1) ..............25-7 25.2.5 SA-ADC Enable Register (SADEN)................ 25-8 25.2.6 SA-ADC Touch Sensor Register (SADTCH) ............25-9 25.2.7 SA-ADC Trigger Register (SADTRG) ..............
Page 17 ML620Q503/Q504 User’s Manual Contents Chapter 28 28. Voltage Level Supervisor ......................28-1 28.1 General Description ........................28.1.1 Features ........................28-1 28.1.2 Configuration ......................28-1 28.2 Description of Registers ......................28.2.1 List of Registers ...................... 28-2 28.2.2 Voltage level supervisor control register (VLSCON) ..........28-3 28.2.3 Voltage level supervisor mode register (VLSMOD) ..........
Page 18: Overview
Chapter 1 Overview...
Page 19: Features
ML620Q503/Q504 User’s Manual Chapter 1 Overview Overview Features This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I C bus interface (master), supply voltage level detect circuit, RC oscillation type A/D converter, and successive approximation type A/D converter are incorporated around 16-bit CPU nX-U16/100.
Page 20 ML620Q503/Q504 User’s Manual Chapter 1 Overview • Timers (TMR) − 8 bits × 8 channels (Timer0-7: 16-bit × 4 configuration available by using Timer0-1 or Timer2-3, Timer4-5, Timer6-7) − Selection of one shot timer mode is possible − External clock can be selected as timer clock. •...
Page 21 ML620Q503/Q504 User’s Manual Chapter 1 Overview • Successive approximation type A/D converter (SA-ADC) − Input × 12 channels − 12-bit A/D converter − Starting by trigger of Timer/FTM function. − Capacitive touch sense function • Analog Comparator (CMP) − Input × 2 ch −...
Page 22 ML620Q503/Q504 User’s Manual Chapter 1 Overview • Shipment − Die *Please contact our responsible sales person for the pad layout information. − 48-pin plastic TQFP Tray ML620Q503-xxxTBZWAAL ML620Q504-xxxTBZWAAL Tape and Reel ML620Q503-xxxTBZWABL ML620Q504-xxxTBZWABL • Guaranteed operating range − Operating temperature (ambient) : −40°C to +85°C −...
Page 23: Configuration Of Functional Blocks
ML620Q503/Q504 User’s Manual Chapter 1 Overview Configuration of Functional Blocks 1.2.1 Block Diagram of ML620Q503/Q504 CPU (nX-U16/100) co-processor EPSW1~3 ELR1~3 ECSR1~3 GREG (muldiv) 0~15 DSR/CSR Timing Controller Program Memory Instruction Instruction Controller (Flash) On-Chip Decoder Register 32K/64Kbyte Data-bus Power SCK0 SIN0 SSIO x 1 SOUT0...
Page 24: Pins
ML620Q503/Q504 User’s Manual Chapter 1 Overview Pins 1.3.1 Pin Layout 1.3.1.1 Pin Layout of ML620Q503/Q504 TQFP Package P05 | RCM *4 | P54 P04 | RT0 *5 | P55 P03 | AIN11 | RS0 | *3$ *6 | P56 P02 | AIN10 | RCT0 | *2$ *7 | P57 P01 | AIN9 | CS0 | *1$ TEST0...
Page 25: List Of Pins
ML620Q503/Q504 User’s Manual Chapter 1 Overview 1.3.2 List of Pins 1.3.2.1 List of Pins of ML620Q503/Q504 TQFP Package 1st Function 2nd/3rd/4th Function Reset functio Function function pin name function pin name name State name － – Negative power supply pin –...
Page 26 ML620Q503/Q504 User’s Manual Chapter 1 Overview 1st Function 2nd/3rd/4th Function Reset functio Function function pin name function pin name name State name P31/ Input-Output port/ UART EXI31/ Hi-Z C clock SSIO data External interrupt/ SCL0 SIN0 TXD0 data CMP0 output output input Comparator minus input...
Page 27 ML620Q503/Q504 User’s Manual Chapter 1 Overview 1st Function 2nd/3rd/4th Function Reset functio Function function pin name function pin name name State name P57/ Input-Output port/ SSIOF EXI57/ Hi-Z OUTC High-speed External interrupt/ SSF0 select TMOUTF TMCKI output clock output output Timer clock input input/output FEUL620Q504...
Page 28: Description Of Pins
ML620Q503/Q504 User’s Manual Chapter 1 Overview 1.3.3 Description of Pins In the table below indicates the functional pin description. The pin name represents the function pin name of the primary function of each terminal, The pin mode represents the set of mode register of Port Control.
Page 29 ML620Q503/Q504 User’s Manual Chapter 1 Overview Pin name Description LSI pin name Logic mode UART UART0 data output pin. P01,P31,P41,P51 TXD0 – UART0 data input pin. P00,P30,P40,P50 RXD0 – UART with FIFO data output pin. P21,P35,P45,P55 TXDF0 – UART with FIFO data input pin. P20,P34,P44,P54 RXDF0 –...
Page 30 ML620Q503/Q504 User’s Manual Chapter 1 Overview Pin name Description LSI pin name Logic mode Successive approximation type A/D converter Reference power supply pin for successive – – approximation type A/D converter. Analog input for successive approximation type A/D (AIN0-3) P34-37, –...
Page 31: Termination Of Unused Pins
ML620Q503/Q504 User’s Manual Chapter 1 Overview 1.3.4 Termination of Unused Pins Table 1-1 shows methods of terminating the unused pins. Table 1-1 Termination of Unused Pins Recommended pin termination RESET_N open TEST0 open TEST1_N open Connect to V P00 to P05 open PXT0 to PXT1 open...
Page 32: Cpu And Memory Space
Chapter 2 CPU and Memory Space...
Page 33: General Description
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2. CPU and Memory Space 2.1 General Description The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipeline architecture parallel processing. It can also perform multiplication/division and multiply-accumulate operation by a coprocessor.
Page 34: Program Memory Space
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2.2 Program Memory Space The program memory space stores program codes or vector tables. The program codes have a length of 16 bits and are specified by a 16-bit program counter (PC). The program memory space is configured by 32K words (64Kbytes) as one segment (code segment).
Page 35: Data Memory Space
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2.3 Data Memory Space The data memory space consists of the segment 0 for the ROM window area, RAM area, and SFR area, the segments 7 and F for the flash data area, and the segments 1, 8, and 9 for the ROM reference area. The data memory space is configured by 32K words (64Kbytes) as one segment (data segment).
Page 36 ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space DSR:DADR Data segment 0 Data segment 7 0:0000H 7:0000H Data flash area 7:07FFH ROM Window area 7:0800H 0:D7FFH 0:D800H RAM area Unused area 0:EFFFH 0:F000H SFR area 0:FFFFH 7:FFFFH 8bit 8bit DSR:DADR Data segment 8 Data segment F...
Page 37: Instruction Length
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2.4 Instruction Length The length of an instruction is 16 bits. 2.5 Data Type Data type of byte (8 bits) and word (16 bits) are supported. 2.6 Description of Registers 2.6.1 List of Registers Address Symbol Symbol...
Page 38: Multiplication/Division Coprocessor
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2.7 Multiplication/Division Coprocessor 2.7.1 General Description This LSI has the built-in multiplication/division function as a coprocessor of the CPU nX-U16/100. For the coprocessor instructions, see "nX-U16/100 Core Instruction Manual". For the multiplication/division library including the routines that carry out operations using this function, see "MULDIVU8LIB User's Manual".
Page 39: Registers A, B, C, And D (Cr0 To Cr7)
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2.7.2.1 Registers A, B, C, and D (CR0 to CR7) Access: R/W Access size: 8/16 bit Initial value: 0000H AREG7 AREG6 AREG5 AREG4 AREG3 AREG2 AREG1 AREG0 Initial value AREG15 AREG14 AREG13 AREG12 AREG11...
Page 40: Operation Mode Register (Cr8)
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2.7.2.2 Operation Mode Register (CR8) Access: R/W Access size: 8 bits Initial value: 00H CLEN – – SIGN – CLMOD2 CLMOD1 CLMOD0 Initial value The operation mode register sets the operation mode. The bit symbol cannot be used in the program.
Page 41: Operation Status Register (Cr9)
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2.7.2.3 Operation Status Register (CR9) Access: R/W Access size: 8 bits Initial value: 00H – – Initial value The operation status register stores the state of an operation execution result. The bit symbol cannot be used in the program. •...
Page 42: Coprocessor Id Register (Cr15)
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space The flags changes during each operation as follows: Operation mode SIGN Multiplication Division Multiply-accumulate (non-saturating) Multiply-accumulate (saturating) *: Changes according to the result. -: No change. 2.7.2.4 Coprocessor ID Register (CR15) Access: R Access size: 8 bits Initial value: 81H...
Page 43: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 2 CPU and Memory Space 2.7.3 Description of Operation When using the multiplication/division function, see "MULDIVU8LIB User's Manual" for the available multiplication/division library. The following example shows a program for multiplication without using the library. ; 0x1234H × 0x0AA55H multiplication example ,#55H ;...
Page 44: Reset Function
Chapter 3 Reset Function...
Page 45: Overview
ML620Q503/Q504 User’s Manual Chapter 3 Reset Function 3 Reset Function 3.1 Overview This LSI has the six reset functions shown below. If any of the six reset conditions is satisfied, this LSI enters system reset mode. • Reset by the RESET_N pin •...
Page 46: Description Of Registers
ML620Q503/Q504 User’s Manual Chapter 3 Reset Function 3.2 Description of Registers 3.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F00C Reset status register RSTAT – – FEUL620Q504 3–2...
Page 47: Reset Status Register (Rstat)
ML620Q503/Q504 User’s Manual Chapter 3 Reset Function 3.2.2 Reset Status Register (RSTAT) Address: 0F00CH Access: R/W Access size: 8 bits Initial value: Undefined RSTAT – – – LLDR VLSR WDTR – Initial value *)The initial value depends on the reset factor RSTAT is a special function register (SFR) that indicates the causes set to the system reset mode.
Page 48: Description Of Operation
ML620Q503/Q504 User’s Manual Chapter 3 Reset Function 3.3 Description of Operation 3.3.1 Cause of Reset This LSI can be reset by hard reset from LSI pin, Software reset by BRK instruction, and LSI internal status. • Reset by the RESET_N pin System Reset occur when “0”...
Page 49 ML620Q503/Q504 User’s Manual Chapter 3 Reset Function [Note] In system reset mode, the contents of data memory and those of any SFR whose initial value is undefined are not initialized and are undefined. Initialize them by software. In system reset mode by the BRK instruction, no special function register (SFR) that has a fixed initial value is initialized either.
Page 50: Power Management
Chapter 4 Power Management...
Page 51: General Description
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4 Power Management 4.1 General Description The LSI has four power management modes listed below to save the Power consumption. It also has a block control function, which power downs the circuits of unused peripherals (reset registers and stop clock supplies) to make even more reducing the current consumption.
Page 52: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.2 Description of Registers 4.2.1 Register Configuration List Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F008 Stop code acceptor STPACP – – 0F009 Standby control register SBYCON – 0F068 BLKCON0 8/16 Block control register 01 BLKCON01 0F069...
Page 53: Stop Code Acceptor (Stpacp)
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.2.2 Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value: -(Undefined) STPACP – – – – – – – – Initial value STPACP is a write-only special function register (SFR) that is used for setting a STOP mode. When STPACP is read, “00H”...
Page 54: Standby Control Register (Sbycon)
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H SBYCON – – – – HLTH DHLT Initial value SBYCON is a special function register (SFR) to control the operation mode of MCU. Description of Bits •...
Page 55: Block Control Register 01 (Blkcon01)
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.2.4 Block Control Register 01 (BLKCON01) Address: 0F068H Access: R/W Access size: 8/16 bit Initial value: 0000H BLKCON0 DTM7 DTM6 DTM5 DTM4 DTM3 DTM2 DTM1 DTM0 Initial value BLKCON1 – – – – DFTM3 DFTM2 DFTM1...
Page 56 ML620Q503/Q504 User's Manual Chapter 4 Power Management DTM6 Description Enable operating the timer 6 (initial value) Disable operating the timer 6 DTM7 Description Enable operating the timer 7 (initial value) Disable operating the timer 7 • DFTM3-0 (bits 11 to 8) The DFTM3-0 bits are used to control the operation of multi-function timer(FTM).
Page 57: Block Control Register 23 (Blkcon23)
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.2.5 Block Control Register 23 (BLKCON23) Address: 0F06AH Access: R/W Access size: 8/16 bit Initial value: 0000H BLKCON2 DI2C1 DI2C0 – DUAF0 DUA1 DUA0 DSIOF0 DSIO0 Initial value BLKCON3 DCMP1 DCMP0 – – –...
Page 58 ML620Q503/Q504 User's Manual Chapter 4 Power Management • DI2C1-0 (bits 7 to 6) The DI2C1-0 bits are used to control the I C bus interface operation. DI2C1 Description Enable operating the I C bus interface 1 (initial value) Disable operating the I C bus interface 1 DI2C0 Description...
Page 59: Block Control Register 45 (Blkcon45)
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.2.6 Block Control Register 45 (BLKCON45) Address: 0F06CH Access: R/W Access size: 8/16 bit Initial value: 0400H BLKCON4 – – – – – – DRAD DSAD Initial value BLKCON5 – – – – –...
Page 60 ML620Q503/Q504 User's Manual Chapter 4 Power Management [Note] •When any flag is set to “1” (disable operation), the function of the applicable block is reset (all registers are initialized) and the clock supply to that block stops. While the flag is set to “1”, the writing to the registers of the block becomes invalid.
Page 61: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.3 Description of Operation 4.3.1 HALT Mode 4.3.1.1 HALT Mode During the HALT mode, the CPU interrupts execution of instructions and only the peripheral circuits are running. When the HLT bit of the standby control register (SBYCON) is set to “1”, the mode changes to the HALT mode. When a WDT interrupt request, or an interrupt request enabled by an interrupt enable register (IE1 to IE7) is issued, the HLT bit is set to “0”...
Page 62: Deep-Halt Mode
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.3.1.2 DEEP-HALT Mode During the DEEP-HALT mode, the CPU interrupts execution of instructions, and the entire circuit stops operating except for some peripheral blocks such as watchdog timer and LTBC. When the DHLT bit of the standby control register (SBYCON) is set to “1”, the mode changes to the DEEP-HALT mode.
Page 63 ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.3.1.3 HALT-H Mode During the HALT-H mode, the CPU interrupts execution of instructions, the high-speed clock is stopped, and only the peripheral circuits operate that can operate with the low-speed clock. When the HLTH bit of the standby control register (SBYCON) is set to “1”, the mode changes to the HALT-H mode.
Page 64: Stop Mode
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.3.2 STOP Mode During the STOP mode, the low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by successively writing “5nH” and “0AnH” (where n is 0 to 0FH) to the stop code acceptor (STPACP) and the STP bit of the standby control register (SBYCON) is set to “1”, the STOP mode is entered.
Page 65: Oscillation Stop And Restart Timing Of High-Speed Clock
ML620Q503/Q504 User's Manual Chapter 4 Power Management Oscillation Low-speed RC waveform oscillation 29 counts Oscillation Low-speed waveform crystal oscillation 8192 counts LSCLK SYSCLK crystal oscillation RC oscillation High-speed RC Oscillation waveform oscillation 512 counts High-speed Oscillation waveform crystal oscillation 4096 counts OSCLK crystal crystal...
Page 66 ML620Q503/Q504 User's Manual Chapter 4 Power Management Oscillation Low-speed RC waveform oscillation Oscillation 29 counts Low-speed waveform crystal oscillation 8192 counts LSCLK RC oscillation crystal oscillation High-speed RC Oscillation waveform oscillation 512 counts High-speed Oscillation waveform crystal oscillation 4096 counts OSCLK crystal crystal...
Page 67: Note On Return Operation From Stop/Halt/Deep-Halt/Halt-H Mode
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.3.2.3 Note on Return Operation from STOP/HALT/DEEP-HALT/HALT-H Mode The operation of returning from the STOP, HALT, DEEP-HALT, or HALT-H mode varies according to the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.
Page 68: Operation Of Functions In Stop/Halt/Deep-Halt/Halt-H Mode
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.3.3 Operation of Functions in STOP/HALT/DEEP-HALT/HALT-H Mode Table 4-3 shows the states of the functions in each of the STOP, HALT, DEEP-HALT, and HALT-H modes. Table 4-3 State of Functions in STOP/HALT/DEEP-HALT/HALT-H Mode Function HALT HALT-H...
Page 69: Block Control Function
ML620Q503/Q504 User's Manual Chapter 4 Power Management 4.3.4 Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing power consumption. For each block control register without DLLD flag, the initial value of each flag is “0”, meaning the operation of each block is enabled.
Page 70: Interrupts
Chapter 5 Interrupts...
Page 71: General Description
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5 Interrupts 5.1 General Description This LSI has 38 interrupt sources (External interrupts: 8 sources, Internal interrupts: 30 sources) and a software interrupt (SWI). For details of each interrupt, see the following chapters: "Chapter 6 Clock Generation Circuit" "Chapter 7 Time Base Counter "...
Page 72: Configuration
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.1.2 Configuration Figure 5-1 shows the circuit of the interrupt controller. EXInTGO (to FTM) Non-Maskable int Interrupt source from each Int arbiter peripheral int (to CPU) (level Maskable int control) IRQ* PXT0 PXT1 Int Edge Noise Sampling Selector...
Page 73: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2 Description of Registers 5.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F010 8/16 Interrupt enable register 01 IE01 0F011 0F012 8/16 Interrupt enable register 23 IE23 0F013 0F014 8/16 Interrupt enable register 45 IE45...
Page 74 ML620Q503/Q504 User's Manual Chapter 5 Interrupts Address Initial value Name Symbol (Byte) Symbol (Word) Size 0F04A External interrupt 23 selection EXI2SEL 8/16 EXI23SEL register 0F04B EXI3SEL 0F04C External interrupt 45 selection EXI4SEL 8/16 EXI45SEL register 0F04D EXI5SEL 0F04E External interrupt 67 selection EXI6SEL 8/16 EXI67SEL...
Page 75: Interrupt Enable Register 01 (Ie01)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.2 Interrupt Enable Register 01 (IE01) Address: 0F010H Access: R/W Access size: 8/16 bits Initial value: 0000H – – – – – – – – Initial value EEXI7 EEXI6 EEXI5 EEXI4 EEXI3 EEXI2 EEXI1 EEXI0 Initial value IE01 is a special function register (SFR) used to control enable/disable for each interrupt request.
Page 76 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • EEXI4 (bit 12) EEXI4 is the enable flag for the external interrupt 4 (EXI4INT). EEXI4 Description Disabled (initial value) Enabled • EEXI5 (bit 13) EEXI5 is the enable flag for the external interrupt 5 (EXI5INT). EEXI5 Description Disabled (initial value)
Page 77: Interrupt Enable Register 23 (Ie23)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.3 Interrupt Enable Register 23 (IE23) Address: 0F012H Access: R/W Access size: 8/16 bits Initial value: 0000H – EUAF0 EUA1 EUA0 EI2C1 EI2C0 ESIOF0 ESIO0 Initial value EMD0 EVLS ELOSC – – – – –...
Page 78 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • EUA0 (bit 4) EUA0 is the enable flag for the UART0 reception interrupt (UA0INT). EUA0 Description Disabled (initial value) Enabled • EUA1 (bit 5) EUA1 is the enable flag for the UART0 transmission interrupt (UA1INT). EUA1 Description Disabled (initial value)
Page 79: Interrupt Enable Register 45 (Ie45)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.4 Interrupt Enable Register 45 (IE45) Address: 0F014H Access: R/W Access size: 8/16 bits Initial value: 0000H – – ECMP1 ECMP0 – – ERAD ESAD Initial value ETM7 ETM6 ETM5 ETM4 ETM3 ETM2 ETM1 ETM0 Initial value IE45 is a special function register (SFR) used to control enable/disable for each interrupt request.
Page 80 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • ETM0 (bit 8) ETM0 is the enable flag for the 8-bit timer 0 interrupt (TM0INT). ETM0 Description Disabled (initial value) Enabled • ETM1 (bit 9) ETM1 is the enable flag for the 8-bit timer 1 interrupt (TM1INT). ETM1 Description Disabled (initial value)
Page 81: Interrupt Enable Register 67 (Ie67)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.5 Interrupt Enable Register 67 (IE67) Address: 0F016H Access: R/W Access size: 8/16 bit Initial value: 0000H – – – – EFTM3 EFTM2 EFTM1 EFTM0 Initial value – – – – – ELTBC2 ELTBC1 ELTBC0 Initial value IE67 is a special function register (SFR) used to control enable/disable for each interrupt request.
Page 82 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • ELTBC0 (bit 8) ELTBC0 is the enable flag for the time base counter 0 interrupt (LTB0INT). ELTBC0 Description Disabled (initial value) Enabled • ELTBC1 (bit 9) ELTBC1 is the enable flag for the time base counter 1 interrupt (LTB1INT). ELTBC1 Description Disabled (initial value)
Page 83: Interrupt Request Register 01 (Irq01)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.6 Interrupt Request Register 01 (IRQ01) Address: 0F018H Access: R/W Access size: 8/16 bit Initial value: 0000H IRQ0 – – – – – – – QWDT Initial value IRQ1 QEXI7 QEXI6 QEXI5 QEXI4 QEXI3 QEXI2 QEXI1 QEXI0...
Page 84 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • QEXI1 (bit 9) QEXI1 is the request flag for the external interrupt 1 (EXI1INT). QEXI1 Description No request (initial value) Request • QEXI2 (bit 10) QEXI2 is the request flag for the external pin interrupt 2 (EXI2INT). QEXI2 Description No request (initial value)
Page 85 ML620Q503/Q504 User's Manual Chapter 5 Interrupts [Note] When an interrupt is generated by the write instruction to the interrupt request register (IRQ1) or to the interrupt enable register (IE1), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL620Q504 5–15...
Page 86: Interrupt Request Register 23 (Irq23)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.7 Interrupt Request Register 23 (IRQ23) Address: 0F01AH Access: R/W Access size: 8/16 bit Initial value: 0000H IRQ2 – QUAF0 QUA1 QUA0 QI2C1 QI2C0 QSIOF0 QSIO0 Initial value IRQ3 QMD0 QVLS QLOSC – – –...
Page 87 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • QI2C1 (bit 3) QI2C1 is the request flag for the I2C bus 1 interrupt (I2C1INT). QI2C1 Description No request (initial value) Request • QUA0 (bit 4) QUA0 is the request flag for the UART0 reception interrupt (UA0INT). QUA0 Description No request (initial value)
Page 88 ML620Q503/Q504 User's Manual Chapter 5 Interrupts [Note] When an interrupt is generated by the write instruction to the interrupt request register (IRQ23) or to the interrupt enable register (IE23), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL620Q504 5–18...
Page 89: Interrupt Request Register 45 (Irq45)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.8 Interrupt Request Register 45 (IRQ45) Address: 0F01CH Access: R/W Access size: 8/16 bit Initial value: 0000H – – IRQ4 QCMP1 QCMP0 – – QRAD QSAD Initial value IRQ5 QTM7 QTM6 QTM5 QTM4 QTM3 QTM2 QTM1 QTM0...
Page 90 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • QCMP1 (bit 5) QCMP1 is the request flag for the comparator 1 interrupt (CMP1INT). QCMP1 Description No request (initial value) Request • QTM0 (bit 8) QTM0 is the request flag for the 8-bit timer 0 interrupt (TM0INT). QTM0 Description No request (initial value)
Page 91 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • QTM6 (bit 14) QTM6 is the request flag for the 8-bit timer 6 interrupt (TM6INT). QTM6 Description No request (initial value) Request • QTM7 (bit 15) QTM7 is the request flag for the 8-bit timer 5 interrupt (TM7INT). QTM7 Description No request (initial value)
Page 92: Interrupt Request Register 67 (Irq67)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.9 Interrupt Request Register 67 (IRQ67) Address: 0F01EH Access: R/W Access size: 8/16 bits Initial value: 0000H IRQ6 – – – – QFTM3 QFTM2 QFTM1 QFTM0 Initial value IRQ7 – – – – – QLTBC2 QLTBC1 QLTBC0...
Page 93 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • QFTM3 (bit 3) QFTM3 is the request flag for the 16-bit timer 3 interrupt (FTM3INT). QFTM3 Description No request (initial value) Request • QLTBC0 (bit 8) QLTBC0 is the request flag for the time base counter 0 interrupt (LTB0INT). QLTBC0 Description No request (initial value)
Page 94: Interrupt Level Control Enable Register (Ilen)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.10 Interrupt Level Control Enable Register (ILEN) Address: 0F020H Access: R/W Access size: 8/16 bits Initial value: 0000H ILENL – – – – – – – Initial value ILENH – – – – – –...
Page 95: Current Interrupt Request Level Register (Cil)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.11 Current Interrupt Request Level Register (CIL) Address: 0F022H Access: R/W Access size: 8/16 bits Initial value: 0000H CILL CILN – – – CILM3 CILM2 CILM1 CILM0 Initial value CILH – – – – –...
Page 96 ML620Q503/Q504 User's Manual Chapter 5 Interrupts CILM2 Description Interrupt level 3 is not in processing (initial value) Interrupt level 3 is in processing CILM3 Description Interrupt level 4 is not in processing (initial value) Interrupt level 4 is in processing •...
Page 97: Interrupt Level Control Register 1 (Ilc1)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.12 Interrupt Level Control Register 1 (ILC1) Address: 0F024H Access: R/W Access size: 8/16 bits Initial value: 0000H ILC1L L1EXI3 L0EXI3 L1EXI2 L0EXI2 L1EXI1 L0EXI1 L1EXI0 L0EXI0 Initial value ILC1H L1EXI7 L0EXI7 L1EXI6 L0EXI6 L1EXI5 L0EXI5 L1EXI4...
Page 98 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • L1-0EXI3 (bits 7 to 6) L1-0EXI3 set the level of the external interrupt 3 (EXI3INT). L1EXI3 L0EXI3 Description Level 1 (initial value) Level 2 Level 3 Level 4 • L1-0EXI4 (bits 9 to 8) L1-0EXI4 set the level of the external interrupt 4 (EXI4INT).
Page 99: Interrupt Level Control Register 2 (Ilc2)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.13 Interrupt Level Control Register 2 (ILC2) Address: 0F026H Access: R/W Access size: 8/16 bits Initial value: 0000H ILC2L L1I2C1 L0I2C1 L1I2C0 L0I2C0 L1SIOF0 L0SIOF0 L1SIO0 L0SIO0 Initial value ILC2H – – L1UAF0 L0UAF0 L1UA1 L0UA1 L1UA0...
Page 100 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • L1-0I2C1 (bits 7 to 6) L1-0I2C1 set the level of the I2C bus 1 interrupt (I2C1INT). L1I2C1 L0I2C1 Description Level 1 (initial value) Level 2 Level 3 Level 4 • L1-0UA0 (bits 9 to 8) L1-0UA0 set the level of the UART0 reception interrupt (UA0INT).
Page 101: Interrupt Level Control Register 3 (Ilc3)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.14 Interrupt Level Control Register 3 (ILC3) Address: 0F028H Access: R/W Access size: 8/16 bits Initial value: 0000H ILC3L – – – – – – – – Initial value ILC3H L1MD0 L0MD0 L1VLS L0VLS L1LOSC L0LOSC –...
Page 102 ML620Q503/Q504 User's Manual Chapter 5 Interrupts [Note] A write instruction to the interrupt level control register 3 (ILC3) should be executed after disabling the interrupt. Except this way, the write instruction to the interrupt level control register 3(ILC3) is not guaranteed.. FEUL620Q504 5–32...
Page 103: Interrupt Level Control Register 4 (Ilc4)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.15 Interrupt Level Control Register 4 (ILC4) Address: 0F02AH Access: R/W Access size: 8/16 bits Initial value: 0000H ILC4L – – – – L1RAD L0RAD L1SAD L0SAD Initial value ILC4H – – – – L1CMP1 L0CMP1 L1CMP0...
Page 104 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • L1-0CMP1 (bits 11 to 10) L1-0CMP1 set the level of the comparator 1 interrupt (CMP1INT). L1CMP1 L0CMP1 Description Level 1 (initial value) Level 2 Level 3 Level 4 [Note] A write instruction to the interrupt level control register 4 (ILC4) should be executed after disabling the interrupt.
Page 105: Interrupt Level Control Register 5 (Ilc5)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.16 Interrupt Level Control Register 5 (ILC5) Address: 0F02CH Access: R/W Access size: 8/16 bits Initial value: 0000H ILC5L L1TM3 L0TM3 L1TM2 L0TM2 L1TM1 L0TM1 L1TM0 L0TM0 Initial value ILC5H L1TM7 L0TM7 L1TM6 L0TM6 L1TM5 L0TM5 L1TM4...
Page 106 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • L1-0TM3 (bits 7 to 6) L1-0TM3 set the level of the 8-bit timer 3 interrupt (TM3INT). L1TM3 L0TM3 Description Level 1 (initial value) Level 2 Level 3 Level 4 • L1-0TM4 (bits 9 to 8) L1-0TM4 set the level of the 8-bit timer 4 interrupt (TM4INT).
Page 107: Interrupt Level Control Register 6 (Ilc6)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.17 Interrupt Level Control Register 6 (ILC6) Address: 0F02EH Access: R/W Access size: 8/16 bits Initial value: 0000H ILC6L L1FTM3 L0FTM3 L1FTM2 L0FTM2 L1FTM1 L0FTM1 L1FTM0 L0FTM0 Initial value ILC6H – – – – –...
Page 108 ML620Q503/Q504 User's Manual Chapter 5 Interrupts • L1-0FTM3 (bits 7 to 6) L1-0FTM3 set the level of the 16-bit timer 3 interrupt (FTM3INT). L1FTM3 L0FTM3 Description Level 1 (initial value) Level 2 Level 3 Level 4 [Note] A write instruction to the interrupt level control register 6 (ILC6) should be executed after disabling the interrupt.
Page 109: Interrupt Level Control Register 7 (Ilc7)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.18 Interrupt Level Control Register 7 (ILC7) Address: 0F030H Access: R/W Access size: 8/16 bits Initial value: 0000H ILC7L – – L1LTBC2 L0LTBC2 L1LTBC1 L0LTBC1 L1LTBC0 L0LTBC0 Initial value ILC7H – – – – –...
Page 110 ML620Q503/Q504 User's Manual Chapter 5 Interrupts [Note] A write instruction to the interrupt level control register 7 (ILC7) should be executed after disabling the interrupt. Except this way, the write instruction to the interrupt level control register 7(ILC7) is not guaranteed. FEUL620Q504 5–40...
Page 111: External Interrupt Control Registers 01 (Exicon01)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.19 External Interrupt Control Registers 01 (EXICON01) Address: 0F040H Access: R/W Access size: 8/16 bit Initial value: 0000H EXICON0 EXI7E0 EXI6E0 EXI5E0 EXI4E0 EXI3E0 EXI2E0 EXI1E0 EXI0E0 Initial value EXICON1 EXI7E1 EXI6E1 EXI5E1 EXI4E1 EXI3E1 EXI2E1 EXI1E1...
Page 112: External Interrupt Control Registers 23 (Exicon23)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.20 External Interrupt Control Registers 23 (EXICON23) Address: 0F042H Access: R/W Access size: 8/16 bit Initial value: 0000H EXICON2 EXI7SM EXI6SM EXI5SM EXI4SM EXI3SM EXI2SM EXI1SM EXI0SM Initial value EXICON3 EXI7FL EXI6FL EXI5FL EXI4FL EXI3FL EXI2FL EXI1FL...
Page 113: External Interrupt 01 Selection Register (Exi01Sel)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.21 External Interrupt 01 Selection Register (EXI01SEL) Address: 0F048H Access: R/W Access size: 8/16 bit Initial value: 0000H EXI0SEL EXI0S7 EXI0S6 EXI0S5 EXI0S4 EXI0S3 EXI0S2 EXI0S1 EXI0S0 Initial value EXI1SEL EXI1S7 EXI1S6 EXI1S5 EXI1S4 EXI1S3 EXI1S2 EXI1S1...
Page 114 ML620Q503/Q504 User's Manual Chapter 5 Interrupts [Note] A write instruction to the External Interrupt Selection Register(EXI01SEL) should be executed after disabling the interrupt to be changed. And the request bit which correspond to the request register need to be cleared after the change.
Page 115: External Interrupt 23 Selection Register (Exi23Sel)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.22 External Interrupt 23 Selection Register (EXI23SEL) Address: 0F04AH Access: R/W Access size: 8/16 bit Initial value: 0000H EXI2SEL EXI2S7 EXI2S6 EXI2S5 EXI2S4 EXI2S3 EXI2S2 EXI2S1 EXI2S0 Initial value EXI3SEL EXI3S7 EXI3S6 EXI3S5 EXI3S4 EXI3S3 EXI3S2 EXI3S1...
Page 116 ML620Q503/Q504 User's Manual Chapter 5 Interrupts [Note] A write instruction to the External Interrupt Selection Register(EXI23SEL) should be executed after disabling the interrupt to be changed. And the request bit which correspond to the request register need to be cleared after the change.
Page 117: External Interrupt 45 Selection Register (Exi45Sel)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.23 External Interrupt 45 Selection Register (EXI45SEL) Address: 0F04CH Access: R/W Access size: 8/16 bit Initial value: 0000H EXI4SEL EXI4S7 EXI4S6 EXI4S5 EXI4S4 EXI4S3 EXI4S2 EXI4S1 EXI4S0 Initial value EXI5SEL EXI5S7 EXI5S6 EXI5S5 EXI5S4 EXI5S3 EXI5S2 EXI5S1...
Page 118 ML620Q503/Q504 User's Manual Chapter 5 Interrupts [Note] A write instruction to the External Interrupt Selection Register(EXI45SEL) should be executed after disabling the interrupt to be changed. And the request bit which correspond to the request register need to be cleared after the change.
Page 119: External Interrupt 67 Selection Register (Exi67Sel)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.2.24 External Interrupt 67 Selection Register (EXI67SEL) Address: 0F04EH Access: R/W Access size: 8/16 bit Initial value: 0000H EXI6SEL EXI6S7 EXI6S6 EXI6S5 EXI6S4 EXI6S3 EXI6S2 EXI6S1 EXI6S0 Initial value EXI7SEL EXI7S7 EXI7S6 EXI7S5 EXI7S4 EXI7S3 EXI7S2 EXI7S1...
Page 120 ML620Q503/Q504 User's Manual Chapter 5 Interrupts [Note] A write instruction to the External Interrupt Selection Register(EXI67SEL) should be executed after disabling the interrupt to be changed. And the request bit which correspond to the request register need to be cleared after the change.
Page 121: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.3 Description of Operation 5.3.1 Interrupt Source With the exception of the watchdog timer interrupt (WDTINT), interrupt enable/disable for 37 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE0 to 7). WDTINT is a non-maskable interrupt.
Page 122 ML620Q503/Q504 User's Manual Chapter 5 Interrupts Timer 7 interrupt TM7INT 005EH Function timer 0 interrupt FTM0INT 0060H Function timer 1 interrupt FTM1INT 0062H Function timer 2 interrupt FTM2INT 0064H Function timer 3 interrupt FTM3INT 0066H Time base counter 0 interrupt LTB0INT 0070H Time base counter 1 interrupt...
Page 123: Maskable Interrupt Processing
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.3.2 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to "1", the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) Transfer the program counter (PC) to ELR1 (2) Transfer CSR to ECSR1 (3) Transfer PSW to EPSW1 (4) Set the MIE flag to "0"...
Page 124: Notes On Interrupt Routine
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.3.5 Notes on Interrupt Routine Notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable.
Page 125 ML620Q503/Q504 User's Manual Chapter 5 Interrupts A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled •Processing immediately after the start of interrupt routine execution Specify the "PUSH LR" instruction to save the subroutine return address in the stack. •Processing at the end of interrupt routine execution Specify "POP LR"...
Page 126 ML620Q503/Q504 User's Manual Chapter 5 Interrupts Status B: Non-maskable interrupt is being processed B-1: When no instruction is executed in an interrupt routine •Processing immediately after the start of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW.
Page 127 ML620Q503/Q504 User's Manual Chapter 5 Interrupts Example of description: B-2-2 Intrpt_B-2-2: ; Start ; Save ELR, EPSW, LR PUSH ELR,EPSW,LR at the beginning Sub_1: BL Sub_1 ; Call subroutine Sub_1 ; Return PC from LR POP PC, PSW, LR ; Return PC from the stack ;...
Page 128: Interrupt Processing When Interrupt Level Control Enabled
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.3.6 Interrupt Processing When Interrupt Level Control Enabled (1) Interrupt processing The interrupt handler carries out the following processing. i. The following processing is made when multiple interrupts are enabled. When a higher level interrupt request occurs, that request should be processed with priority. For this reason, the general-purpose registers are saved to memory and the EPW and EPSW registers are pushed in order to retain the processor state at return.
Page 129: Flow Chart (When Interrupt Level Control Enabled)
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.3.7 Flow Chart (When Interrupt Level Control Enabled) The figure below shows the flow chart of the software processing of a maskable interrupt when the interrupt level control is enabled. The EI and DI instructions allow the execution of multiple interrupts by a higher-level maskable interrupt request during the "execution of the desired processing".
Page 130 ML620Q503/Q504 User's Manual Chapter 5 Interrupts Non-maskable interrupt request Save general-purpose registers to memory Execute desired processing Write access to current interrupt level register (CIL) Restore general-purpose registers from memory RTI instruction Interrupt processing end FEUL620Q504 5–60...
Page 131: Interrupt Disable State
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.3.8 Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state.
Page 132: External Interrupt
ML620Q503/Q504 User's Manual Chapter 5 Interrupts 5.3.9 External Interrupt When an interrupt edge selected with the external interrupt control register 0/1 (EXICON01) occurs at one of external interrupts EXI0 to 7, any of the maskable EXI0 to EXI7 interrupts (EXI0INT to EXI7INT) occurs. It is possible to set the external interrupt control register 2/3 (EXICON23) to perform the filtering with noise filtering and/or sampling (2φ...
Page 133 ML620Q503/Q504 User's Manual Chapter 5 Interrupts T16KHZ SYSCLK EXIn EXInINT Interrupt request n = 0 to 7 QEXIn (d) When Rising-Edge Interrupt Mode with Sampling is Selected Figure 5-2 External Interrupt Generation Timing FEUL620Q504 5–63...
Page 134: Clock Generation Circuit
Chapter 6 Clock Generation Circuit...
Page 135: General Description
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6 Clock Generation Circuit 6.1 General Description The clock generation circuit generates and provides the low-speed clock (LSCLK), the high-speed clock (HSCLK), the system clock (SYSCLK), and the high-speed output clock (OUTCLK). LSCLK and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU, and OUTCLK is a clock that is output from a port.
Page 136 ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit [Note] After power-on or system reset, the operation starts by the clock supplied from the built-in high-speed clock generation circuit. At initialization by software, set the FCON0, FCON1 and FCON2 register to switch to the required clock.
Page 137: List Of Pins
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Pin Name Function Pin for connecting a crystal for low-speed clock. XT1/ Pin for connecting a crystal for low-speed clock. LSCLKI Used for low-speed external clock input OSC0 Pin for connecting a crystal/ceramic oscillator for high-speed clock.
Page 138: Clock Configuration Diagram
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.1.4 Clock Configuration Diagram Figure 6-2 shows the clock system diagram. System clock (SYSCLK) Interrupt Register access T16KHZ Controller Register access LSCLK Low-speed clock (LSCLK) LTBC T256HZ High-speed clock (HSCLK) Register access Timer High-speed source oscillation clock (OSCLK)
Page 139: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.2 Description of Registers 6.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F002 FCON0 8/16 Frequency control register 01 FCON01 0F003 FCON1 0F004 FCON2 8/16 Frequency control register 23 FCON23 0F005 FCON3...
Page 140: Frequency Control Register 01 (Fcon01)
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.2.2 Frequency Control Register 01 (FCON01) Address: 0F002H Access: R/W Access size: 8/16 bit Initial value: 0373H FCON0 OUTC2 OUTC1 OUTC0 OSCM1 OSCM0 SYSC2 SYSC1 SYSC0 Initial value FCON1 HOSST LOSST – –...
Page 141 ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit • OSCM1-0 (bits 4 to 3) The OSCM1-0 bits are used to select the high-speed clock mode. Crystal/ceramic oscillation mode, built-in RC oscillation mode, or external clock input mode can be selected. OSCM1 and OSCM0 can be rewritten only when high-speed oscillation is being stopped (ENOSC bit of FCON1 is "0").
Page 142 ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit • LOSCON (bit 11) The LOSCON bit also permits the low-speed crystal oscillator circuit to oscillate when the low-speed built-in RC oscillation mode is selected. When LOSCON is turned to "1", the low-speed crystal oscillator circuit is enabled to oscillate at the same time even though the built-in RC oscillation mode is selected by the XTM1 or XTM0 bit.
Page 143: Frequency Control Register 23(Fcon23)
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 23(FCON23) Address: 0F004H Access: R/W Access size: 8/16 bits Initial Value: 0002H FCON2 HFLTSEL HFLTSEL – LFLTSEL – – XTM1 XTM0 Initial value FCON3 – – – – –...
Page 144 ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit • HFLTSEL1-0 （bit 7 to 6） HFLTSEL1-0 bits are used to select noise filter on/off at high-speed crystal/ceramic oscillation or external high-speed clock input mode. Two different eliminaton width are selectable. When noise filter is on at 16MHz high speed clock operation, select “High-speed clock noise filter1”.
Page 145: Frequency Status Register (Fstat)
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.2.4 Frequency Status Register (FSTAT) Address: 0F00AH Access: R Access size: 8 bits Initial value: 06H FSTAT – – – – – LOSCS HOSCS – Initial value FSTAT is a special function register (SFR) used to show the clock generation circuit state. Description of Bits •...
Page 146: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3 Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Built-In RC Oscillation Mode Figure 6-3 shows the low-speed clock generation circuit configuration in the built-in RC oscillation mode. When the RC oscillation clock is counted to 128, the low-speed oscillation clock (LSCLK) starts to be supplied. STOP mode RC oscillator circuits...
Page 147: Low-Speed External Clock Input Mode
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.1.3 Low-Speed External Clock Input Mode In external low-speed clock input mode, external clock is input from the PXT1 pin. Figure 6-5 shows the circuit configuration in the external low-speed clock input mode. STOP mode Low-speed oscillation 16 counts...
Page 148: Low-Speed Built-In Rc Oscillation Mode Operation
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.1.4 Low-Speed Built-In RC Oscillation Mode Operation The low-speed built-in RC oscillation mode starts by the occurrence of power ON reset. After power-on, the built-in RC oscillation clock is counted to 128 as the low-speed clock, then the built-in RC oscillation clock (LSCLK) is supplied to the peripheral circuits.
Page 149: Low-Speed Crystal Oscillation Mode Operation
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.1.5 Low-Speed Crystal Oscillation Mode Operation For the low-speed crystal oscillation, the oscillation start/stop can be controlled by the frequency control register 1 (FCON1) or 2 (FCON2). If it sets the XTM1 and XTM0 bits of FCON2 to "01" or the LOSCON bit of FCON1 to "1", Crystal oscillator circuit starts oscillation.
Page 150: Low-Speed External Clock Mode Operation
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.1.6 Low-Speed External Clock Input Mode Operation For the low-speed external clock, the oscillation start/stop can be controlled by the frequency control register 2 (FCON2). If it sets the XTM0 and XTM1 bits of FCON2 to "11", external clock input becomes accepted and then the external clock input is counted to 16, then the low-speed clock (LSCLK) switches to the external clock.
Page 151: High-Speed Clock
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.2 High-Speed Clock For the high-speed clock generation circuit, the built-in RC oscillation mode, the crystal/ceramic oscillation mode, or the external clock input mode can be selected. 6.3.2.1 High-Speed Built-in RC Oscillation Mode Figure 6-9 shows the high-speed clock generation circuit configuration in the built-in RC oscillation mode.
Page 152: High-Speed External Clock Input Mode
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.2.3 High-Speed External Clock Input Mode In external high-speed clock input mode, external clock is input from the P11/OSC1 pin. Figure 6-11 shows the circuit configuration in the external clock input mode. STOP mode ENOSC (Enable oscillation) High-speed oscillation clock...
Page 153: High-Speed Built-In Rc Oscillation Mode Operation
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.2.4 High-Speed Built-In RC Oscillation Mode Operation For the high-speed built-in RC oscillation, the oscillation start/stop can be controlled by the frequency control register 1 (FCON1). Oscillation can be started by setting the ENOSC bit of FCON1 to "1". OSCLK starts to be supplied after the built-in RC oscillation clock is counted to 512 after the oscillation starts.
Page 154 ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit ENOSC bit Low-speed Built-in RC oscillation Built-in RC oscillation built-in oscillation Low-speed RC oscillation 29 counts High-speed Built-in RC oscillation Built-in RC oscillation built-in oscillation High-speed RC oscillation 512 counts High-speed RC oscillation 512 counts Built-in RC oscillation Built-in RC oscillation OSCLK...
Page 155: High-Speed Crystal/Ceramic Oscillation Mode Operation
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.2.5 High-Speed Crystal/Ceramic Oscillation Mode Operation High speed clock is switch to crystal/ceramic oscillation mode by setting FCON0 bit of OSCM1,0 to “01”. If the ENOSC bit of FCON1 is set to "1", the built-in RC oscillation clock is counted to 512 as the high-speed clock, then the built-in RC oscillation clock is supplied as OSCLK.
Page 156 ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit ENOSC bit Low-speed clock built-in RC oscillation built-in RC oscillation Low-speed RC oscillation 29 counts ：oscillation start time ：oscillation start time High-speed crystal/ceramic oscillation crystal/ceramic oscillation crystal/ceramic oscillation High-speed oscillation 4096 counts High-speed oscillation 4096 counts HOSCS bit High-speed...
Page 157: High-Speed External Clock Mode Operation
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.2.6 High-Speed External Clock Mode Operation For the high-speed external clock, the oscillation start/stop can be controlled by the frequency control register1 (FCON1). Oscillation can be started by setting the ENOSC bit of FCON1 to "1". The external clock starts to be supplied as OSCLK after the built-in RC oscillation clock is counted to 512 after the oscillation starts and then the external clock is counted to 128.
Page 158 ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit ENOSC bit Low-speed oscillation Low-speed oscillation Low-speed oscillation Low-speed RC oscillation 26 counts Low-speed RC oscillation 29 counts High-speed External clock External clock External clock High-speed oscillation High-speed oscillation 128 counts 128 counts HOSCS bit High-speed built-in RC oscillation...
Page 159: Switching Of System Clock
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.3 Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-15 shows the flow chart of the system clock switching processing (HSCLK→LSCLK), and Figure 6-16 shows the flow chart of the system clock switching processing (LSCLK→HSCLK).
Page 160: Low-Speed Oscillation Clock Switch Interrupt
ML620Q503/Q504 User's Manual Chapter 6 Clock Generation Circuit 6.3.4 Low-speed oscillation clock switch interrupt The low-speed oscillation clock change interrupt occurs only when switching the mode from low-speed built-in RC oscillation mode to low-speed crystal oscillation mode or external low-speed clock input mode. The interrupt does not occurs when switching the mode from low-speed crystal oscillation mode or external low-speed clock input mode to low-speed build-in RC oscillation mode.
Page 161: Time Base Counter
Chapter 7 Time Base Counter...
Page 162: Overview
ML620Q503/Q504 User’s Manual Chapter 7 Time Base Counter 7. Time Base Counter 7.1 Overview The time base counter generates base clocks for peripheral circuits, and generates interrupt periodically. 7.1.1 Features • LTBC generates T32KHZ to T1HZ signals by dividing the low-speed clock (LSCLK). •...
Page 163: Description Of Registers
ML620Q503/Q504 User’s Manual Chapter 7 Time Base Counter 7.2 Description of Registers 7.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) Low-speed time base counter 0F060 LTBR – register 0F062 LTBADJL 8/16 Low-speed time base counter LTBADJ frequency adjustment register 0F063...
Page 164: Low-Speed Time Base Counter (Ltbr)
ML620Q503/Q504 User’s Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter (LTBR) Address: 0F060H Access: R/W Access size: 8 bits Initial value: 00H LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ Initial value LTBR is a special function register (SFR) to read the T128HZ-T1HZ outputs of the low-speed time base counter. When write to LTBR, the content of LTBR becomes “0”...
Page 165: Low-Speed Time Base Counter Frequency Adjustment Registers (Ltbadj)
ML620Q503/Q504 User’s Manual Chapter 7 Time Base Counter 7.2.3 Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJ) Address: 0F062H Access: R/W Access size: 8/16 bits Initial value: 0000H LTBADJL LADJ7 LADJ6 LADJ5 LADJ4 LADJ3 LADJ2 LADJ1 LADJ0 Initial value LTBADJH –...
Page 166 ML620Q503/Q504 User’s Manual Chapter 7 Time Base Counter The adjustment values (LADJ10-0) to be set in LTBADJH and LTBADJL can be obtained by using the following equations: Adjustment value = Frequency adjustment ratio × 2097152 (decimal) = Frequency adjustment ratio × 200000h (hexadecimal) Example 1: When adjusting +15.0ppm (gaining time) Adjustment value = +15.0ppm ×...
Page 167: Low-Speed Time Base Counter Interrupt Select Registers (Ltbint)
ML620Q503/Q504 User’s Manual Chapter 7 Time Base Counter 7.2.4 Low-Speed Time Base Counter Interrupt select Registers (LTBINT) Address: 0F064H Access: R/W Access size: 8/16 bits Initial value: 0630H LTBINTL – LTI1S2 LTI1S1 LTI1S0 – LTI0S2 LTI0S1 LTI0S0 Initial value LTBINTH –...
Page 168: Description Of Operation
ML620Q503/Q504 User’s Manual Chapter 7 Time Base Counter 7.3 Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. Three of LBC interrupt request interrupt by falling edge of clock output which was assigned by the low-speed time base counter interrupt select register.
Page 169 ML620Q503/Q504 User’s Manual Chapter 7 Time Base Counter Figure 7-4 shows interrupt generation timing of the time base counter output by writing to LTBR. LTBR Write T256HZ T128HZ T64HZ T32HZ T16HZ T16HZ T8HZ T4HZ T2HZ T1HZ Indicates interrupt timing Figure 7-4 Interrupt Timing by Writing to LTBR FEUL620Q504 7–8...
Page 170: Timers
Chapter 8 Timers...
Page 171: Overview
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8. Timers 8.1 Overview This LSI includes 8 channels of 8-bit timers. A pair of 2 timers functions as 16-bit timer. 8.1.1 Features • The timer interrupt (TMnINT, n=0 to 7) is generated when the values of timer counter register (TMnC, n=0 to7) and timer data register (TMnD, n=0 to 7) coincide.
Page 172 ML620Q503/Q504 User’s Manual Chapter 8 Timers Alternative counter clock of each channels are as below 8bit mode case channel Selectable clock LSCLK/OSCLK LSCLK/OSCLK/external pin(P42) LSCLK/OSCLK/external pin(P43) LSCLK/OSCLK/external pin(P52) LSCLK/OSCLK/external pin(P53) LSCLK/OSCLK/low-speed crystal oscillation(*1) 16 bit mode case channel Selectable clock LSCLK/OSCLK LSCLK/OSCLK/external pin(P42) LSCLK/OSCLK/external pin(P52)
Page 173: Description Of Registers
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.2 Description of Registers 8.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F300 TM0D 8/16 Timer 01 data register TM01D 0F301 TM1D 0F302 TM2D 8/16 Timer 23 data register TM23D 0F303 TM3D...
Page 174: Timer N Data Register (Tmnmd : {N,M}={0,1}, {2,3}, {4,5}, {6,7})
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.2.2 Timer n Data Register (TMnmD : {n,m}={0,1} , {2,3} , {4,5} , {6,7}) Address: 0F300H(TM0D/TM01D), 0F301H(TM1D), 0F302H(TM2D/TM23D), 0F303H(TM3D), 0F304H(TM4D/TM45D), 0F305H(TM5D), 0F306H(TM6D/TM67D), 0F307H(TM7D) Access: R/W Access size: 8/16 bits Initial value: FFFFH TMnD TnD7 TnD6 TnD5 TnD4...
Page 175: Timer N Counter Register (Tmnmc : {N,M}={0,1}, {2,3}, {4,5}, {6,7})
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.2.3 Timer n Counter Register (TMnmC : {n,m}={0,1} , {2,3} , {4,5} , {6,7}) Address: 0F310H(TM0C/TM01C), 0F311H(TM1C), 0F312H(TM2C/TM23C), 0F313H(TM3C), 0F314H(TM4C/TM45C), 0F315H(TM5C), 0F316H(TM6C/TM67C), 0F317H(TM7C) Access: R/W Access size: 8/16 bits Initial value: 0000H TMnC TnC7 TnC6 TnC5 TnC4...
Page 176: Timer N Control Register (Tmnmcon : {N,M}={0,1}, {2,3}, {4,5}, {6,7})
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.2.4 Timer nm Control Register (TMnmCON : {n,m}={0,1}, {2,3}, {4,5}, {6,7}) Address: 0F320H(TM0CON/TM01CON), 0F321H(TM1CON), 0F322H(TM2CON/TM23CON), 0F323H(TM3CON), 0F324H(TM4CON/TM45CON), 0F325H(TM5CON), 0F326H(TM6CON/TM67CON), 0F327H(TM7CON) Access: R/W Access size: 8/16 bits Initial value: 0000H TMnCON TnOST TmM16 TnDIV2 TnDIV1 TnDIV0 –...
Page 177 ML620Q503/Q504 User’s Manual Chapter 8 Timers • TnDIV2-0 (bit 5 to 3), TmDIV2-0 (bit 13 to 11) TnDIV2-0(TmDIV2-0) bits are used for selecting dividing rate of operation clock . The dividing rate is assigned by TM0CON，TM2CON，TM4CON，TM6CON at 16bit timer mode. TnDIV2 TnDIV1 TnDIV0...
Page 178: Timer Start Register 0 (Tmstr0)
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.2.5 Timer Start Register 0 (TMSTR0) Address: 0F330H Access: W Access size: 8 bits Initial value: 00H T7RUN T6RUN T5RUN TMSTR0 T4RUN T3RUN T2RUN T1RUN T0RUN Initial value TMSTR0 is a special function (SFR) to control timer 0 to timer 7. Description of Bits •...
Page 179: Timer Stop Register 0 (Tmstp0)
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.2.6 Timer Stop Register 0 (TMSTP0) Address: 0F332H Access: W Access size: 8 bits Initial value: 00H TMSTP0 T7STP T6STP T5STP T4STP T3STP T2STP T1STP T0STP Initial value TMSTP0 is a special function (SFR) to control a timer 0 to timer 7. Description of Bits •...
Page 180: Timer Status Register 0 (Tmstat0)
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.2.7 Timer Status Register 0 (TMSTAT0) Address: 0F334H Access: R Access size: 8 bits Initial value: 00H TMSTAT0 T7STAT T6STAT T5STAT T4STAT T3STAT T2STAT T1STAT T0STAT Initial value TMSTAT0 is a special function (SFR) to control timer 0 to timer 7. Description of Bits •...
Page 181: Description Of Operation
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.3 Description of operation 8.3.1 Normal timer mode operation When the TnRUN bit of timer n register0(TMSTR0) are set to 1, The timer counters(TMnC) is in operation state(TnSTAT =”1”) by the first falling edge of the timer clock(TnCK) that are selected by the Timer control register(TMnCON), and start count up by the second falling edge.
Page 182: One Shot Timer Mode Operation
ML620Q503/Q504 User’s Manual Chapter 8 Timers 8.3.2 One shot timer mode operation When TMnCON register TnOST bit set to “1”, Timer operate one-shot timer mode. In one-shot timer mode, When the count value (TMnC) and the timer 0 to 7 data register (TMnD) coincide, TnRUN bits are cleared automatically .
Page 183: Function Timer(Ftm)
Chapter 9 Function Timer(FTM)
Page 184: General Description
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9 Function Timer (FTM) 9.1 General Description FTM is a 16-bit multifunction timer with the capture and PWM functions in addition to the timer function. It can be started/stopped using an external input signal and a signal from another timer as a trigger. The LSI includes four channels of the multifunction timer.
Page 185: Configuration
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.1.2 Configuration Figure 9-1 shows the configuration of the FTM circuit. Emergency FTMnTGO FTnINT Int controller stop CMP*TGO FTMnINT control circuits Write FTnC FTMnP Output controller EXI*TGO FTnSTAT Trigger FTMnN START controller TM*INT STOP Period Event A...
Page 186: List Of Pins
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) P02/TMOUT0 FTM0P P03/TMOUT1 FTM0N P22/TMOUT2 FTM1P P23/TMOUT3 FTM1N TMOUTn P32/TMOUT4 FTM2P P33/TMOUT5 P36/TMOUT6 FTM2N P37/TMOUT7 FTM3P P42/TMOUT8 FTM3N P43/TMOUT9 FTMOSnN P46/TMOUTA FTOSLn0/1 P47/TMOUTB P52/TMOUTC P53/TMOUTD P56/TMOUTE Data bus P57/TMOUTF FTOSLn0/1 : FTM output selection register n0/1 (n = 0 to F) Figure 9-1 (b) Configuration of FTM Output Selection Circuit 9.1.3 List of Pins...
Page 187: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2 Description of Registers 9.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) – 0F400 FTM0 period register FT0P FFFF 0F402 FTM0 event register A – FT0EA 0000 0F404 FTM0 event register B –...
Page 188 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F43A FT1INTSL 8/16 FTM1 interrupt status register FT1INTS 0F43B FT1INTSH 0F43C FT1INTCL 8/16 FTM1 interrupt clear register FT1INTC 0F43D FT1INTCH 0F440 FTM2 period register –...
Page 189 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F47A FT3INTSL 8/16 FTM3 interrupt status register FT3INTS 0F47B FT3INTSH 0F47C FT3INTCL 8/16 FTM3 interrupt clear register FT3INTC 0F47D FT3INTCH 0F480 FTO0SL 8/16 FTM output 01 select register FTO01SL 0F481 FTO1SL...
Page 190: Ftmn Period Register (Ftnp : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.2 FTMn Period Register (FTnP : n=0,1,2,3) Address: 0F400H(FT0P), 0F420H(FT1P), 0F440H(FT2P), 0F460H(FT3P) Access: R/W Access size: 16 bits Initial value: FFFFH FTnP7 FTnP6 FTnP5 FTnP4 FTnP3 FTnP2 FTnP1 FTnP0 Initial value FTnP15 FTnP14 FTnP13 FTnP12 FTnP11...
Page 191: Ftmn Event Register A (Ftnea : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.3 FTMn Event Register A (FTnEA : n=0,1,2,3) Address: 0F402H(FT0EA), 0F422H(FT1EA), 0F442H(FT2EA), 0F462H(FT3EA) Access: R/W Access size: 16 bits Initial value: 0000H FTnEA7 FTnEA6 FTnEA5 FTnEA4 FTnEA3 FTnEA2 FTnEA1 FTnEA0 Initial value FTnEA15 FTnEA14 FTnEA13 FTnEA12...
Page 192: Ftmn Event Register B (Ftneb : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.4 FTMn Event Register B (FTnEB : n=0,1,2,3) Address: 0F404H(FT0EB), 0F424H(FT1EB), 0F444H(FT2EB), 0F464H(FT3EB) Access: R/W Access size: 16 bits Initial value: 0000H FTnEB7 FTnEB6 FTnEB5 FTnEB4 FTnEB3 FTnEB2 FTnEB1 FTnEB0 Initial value FTnEB15 FTnEB14 FTnEB13 FTnEB12...
Page 193: Ftmn Deadtime Register (Ftndt : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.5 FTMn Dead Time Register (FTnDT : n=0,1,2,3) Address: 0F406H(FT0DT), 0F426H(FT1DT), 0F446H(FT2DT), 0F466H(FT3DT) Access: R/W Access size: 16 bits Initial value: 0000H FTnDT7 FTnDT6 FTnDT5 FTnDT4 FTnDT3 FTnDT2 FTnDT1 FTnDT0 Initial value FTnDT15 FTnDT14 FTnDT13 FTnDT12...
Page 194: Ftmn Counter Register (Ftnc : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.6 FTMn Counter Register (FTnC : n=0,1,2,3) Address: 0F408H(FT0C), 0F428H(FT1C), 0F448H(FT2C), 0F468H(FT3C) Access: R/W Access size: 16 bits Initial value: 0000H FTnC7 FTnC6 FTnC5 FTnC4 FTnC3 FTnC2 FTnC1 FTnC0 Initial value FTnC15 FTnC14 FTnC13 FTnC12 FTnC11...
Page 195: Ftmn Control Register 0 (Ftncon0 : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.7 FTMn Control Register 0 (FTnCON0 : n=0,1,2,3) Address: 0F40AH(FT0CON0), 0F42AH(FT1CON0), 0F44AH(FT2CON0), 0F46AH(FT3CON0) Access: R/W Access size: 8 bits Initial value: 00H FTnCON0 – – FTnSDN – FTnEMGEN – FTnTGEN FTnRUN Initial value FTnCON0 is a special function register (SFR) used to set the function of FTMn.
Page 196: Ftmn Control Register 1 (Ftncon1 : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.8 FTMn Control Register 1 (FTnCON1 : n=0,1,2,3) Address: 0F40BH(FT0CON1), 0F42BH(FT1CON1), 0F44BH(FT2CON1), 0F46BH(FT3CON1) Access: R/W Access size: 8 bits Initial value: 00H FTnCON1 FTnSTAT FTnFLGC FTnFLGB FTnFLGA – – – FTnUD Initial value FTnCON1 is a special function register (SFR) used to set the function of FTMn.
Page 197 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) • FTnFLGC (bit 6) Indicates the control state by the CST bit of FTMn. When FTnC is read, it is cleared. FTnMD FTnFLGC Description TIMER Start enable state by event trigger (initial value) PWM1/2 Start disable state by event trigger CAPTURE...
Page 198: Ftmn Mode Register (Ftnmod : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.9 FTMn Mode Register (FTnMOD : n=0,1,2,3) Address: 0F40CH(FT0MODL/FT0MOD), 0F40DH(FT0MODH), 0F42CH(FT1MODL/FT1MOD), 0F42DH(FT1MODH), 0F44CH(FT2MODL/FT2MOD), 0F44DH(FT2MODH), 0F46CH(FT3MODL/FT3MOD), 0F46DH(FT3MODH) Access: R/W Access size: 8/16 bit Initial value: 0000H FTnMODL FTnOST FTnDTEN – – – – FTnMD1 FTnMD0 Initial value FTnMODH...
Page 199 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) • FTnOST (bit 7) Sets auto-reload/one-shot mode of FTMn. FTnMD FTnOST Description Auto-reload mode (initial value) TIMER PWM1/2 One-shot mode Auto mode Even if the capture is performed once, the data of EA and EB is overwritten (updated) when the next capture is performed.
Page 200: Ftmn Clock Register (Ftnclk : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.10 FTMn Clock Register (FTnCLK : n=0,1,2,3) Address: 0F40EH(FT0CLKL/FT0CLK), 0F40FH(FT0CLKH), 0F42EH(FT1CLKL/FT1CLK), 0F42FH(FT1CLKH), 0F44EH(FT2CLKL/FT2CLK), 0F44FH(FT2CLKH), 0F46EH(FT3CLKL/FT3CLK), 0F46FH(FT3CLKH) Access: R/W Access size: 8/16 bit Initial value: 0000H FTnCLKL – FTnCKD2 FTnCKD1 FTnCKD0 – – FTnCK1 FTnCK0 Initial value FTnCLKH...
Page 201 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) • FTnXCK2-0 (bits 10 to 8) Selects the source when selecting EXTCLK as a timer clock source of FTMn. FTnMD FTnXCK Description TMCKI0 (initial value) TMCKI1 TMCKI2 TIMER TMCKI3 CAPTURE TMCKI4 PWM1/2 TMCKI5 TMCKI6 TMCKI7 FEUL620Q504...
Page 202: Ftmn Trigger Register 0 (Ftntrg0 : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.11 FTMn Trigger Register 0 (FTnTRG0 : n=0,1,2,3) Address: 0F410H(FT0TRG0L/FT0TRG0), 0F411H(FT0TRG0H), 0F430H(FT1TRG0L/FT1TRG0), 0F431H(FT1TRG0H), 0F450H(FT2TRG0L/FT2TRG0), 0F451H(FT2TRG0H), 0F470H(FT3TRG0L/FT3TRG0), 0F471H(FT3TRG0H) Access: R/W Access size: 8/16 bit Initial value: 0000H FTnTRG0L – – – – FTnCST FTnEXCL FTnST1 FTnST0 Initial value...
Page 203 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) • FTnCST (bit 3) Selects the operation mode of starting the counter by trigger event. FTnMD FTnCST Description A trigger event always starts the counter when it is stopped (except TIMER for emergency stop) (initial value) CAPTURE A trigger event does not start the counter before FTnC is read when PWM1/2...
Page 204: Ftmn Trigger Register 1 (Ftntrg1 : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.12 FTMn Trigger Register 1 (FTnTRG1 : n=0,1,2,3) Address: 0F412H(FT0TRG1L/FT0TRG1), 0F413H(FT0TRG1H), 0F432H(FT1TRG1L/FT1TRG1), 0F433H(FT1TRG1H), 0F452H(FT2TRG1L/FT2TRG1), 0F453H(FT2TRG1H), 0F472H(FT3TRG1L/FT3TRG1), 0F473H(FT3TRG1H) Access: R/W Access size: 8/16 bit Initial value: 0000H FTnTRG1L – – FTnEST1 FTnEST0 – – FTnTRM1 FTnTRM0 Initial value FTnTRG1H...
Page 205: Ftmn Interrupt Enable Register (Ftninte: N = 0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.13 FTMn Interrupt Enable Register (FTnINTE: n = 0,1,2,3) Address: 0F418H(FT0INTEL/FT0INTE), 0F419H(FT0INTEH), 0F438H(FT1INTEL/FT1INTE), 0F439H(FT1INTEH), 0F458H(FT2INTEL/FT2INTE), 0F459H(FT2INTEH), 0F478H(FT3INTEL/FT3INTE), 0F479H(FT3INTEH) Access: R/W Access size: 8/16 bit Initial value: 0000H FTnINTEL – – – FTnIETR FTnIETS FTnIEB FTnIEA FTnIEP...
Page 206 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) • FTnIETS (bit 3) Sets the trigger counter stop interrupt enable of FTMn. FTnMD FTnIETS Description TIMER Trigger counter stop interrupt disabled (initial value) CAPTURE Trigger counter stop interrupt enabled PWM1/2 • FTnIETR (bit 4) Sets the trigger counter start interrupt enable of FTMn.
Page 207: Ftmn Interrupt Status Register (Ftnints : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.14 FTMn Interrupt Status Register (FTnINTS : n=0,1,2,3) Address: 0F41AH(FT0INTSL/FT0INTS), 0F41BH(FT0INTSH), 0F43AH(FT1INTSL/FT1INTS), 0F43BH(FT1INTSH), 0F45AH(FT2INTSL/FT2INTS), 0F45BH(FT2INTSH), 0F47AH(FT3INTSL/FT3INTS), 0F47BH(FT3INTSH) Access: R Access size: 8/16 bit Initial value: 0000H FTnINTSL – – FTnISES FTnISTR FTnISTS FTnISB FTnISA FTnISP Initial value...
Page 208 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) • FTnISB (bit 2) Indicates the state of event timing B interrupt of FTMn. FTnMD FTnISB Description TIMER Event timing B interrupt has not occurred (initial value) PWM1/2 Event timing B interrupt has occurred This bit is cleared when writing 1 to FTnIB CAPTURE Capture B interrupt has not occurred...
Page 209: Ftmn Interrupt Clear Register (Ftnintc : N=0,1,2,3)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.15 FTMn Interrupt Clear Register (FTnINTC : n=0,1,2,3) Address: 0F41CH(FT0INTCL/FT0INTC), 0F41DH(FT0INTCH), 0F43CH(FT1INTCL/FT1INTC), 0F43DH(FT1INTCH), 0F45CH(FT2INTCL/FT2INTC), 0F45DH(FT2INTCH), 0F47CH(FT3INTCL/FT3INTC), 0F47DH(FT3INTCH) Access: W Access size: 8/16 bit Initial value: 0000H FTnINTCL – – FTnICES FTnICTR FTnICTS FTnICB FTnICA FTnICP Initial value...
Page 210: Ftm Output Nm Select Register (Ftonmsl : N = 0,2,4,6,8,A,C,E, M=N+1)
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.2.16 FTM Output nm Select Register (FTOnmSL : n = 0,2,4,6,8,A,C,E, m=n+1) Address: 0F480H(FTO0SL/FTO01SL), 0F481H(FTO1SL), 0F482H(FTO2SL/FTO23SL), 0F483H(FTO3SL), 0F484H(FTO4SL/FTO45SL), 0F485H(FTO5SL), 0F486H(FTO6SL/FTO67SL), 0F487H(FTO7SL), 0F488H(FTO8SL/FTO89SL), 0F489H(FTO9SL), 0F48AH(FTOASL/FTOABSL), 0F48BH(FTOBSL), 0F48CH(FTOCSL/FTOCDSL), 0F48DH(FTODSL), 0F48EH(FTOESL/FTOEFSL), 0F48FH(FTOFSL) Access: R/W Access size: 8/16 bit Initial value: 0000H FTOnSL FTOnSN...
Page 211 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) Description of Bits • FTOnS2-0 (bits 2 to 0)/FTOmS2-0 (bits 10 to 8) These bits used to select the FTM output that is assigned TMOUTx(X=0-F) output signal. FTOnS2/ FTOnS1/ FTOnS0/ Description FTOmS2 FTOmS1 FTOmS0 FTM0P (Initial value) FTM0N...
Page 212: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3 Description of Operation This operates as timer, capture, or PWM according to the mode set in FTnMD1-0. This section describes start/stop by software/event trigger, emergency stop, interrupt processing, and output control for each mode. FTMn has four types of operation mode: TIMER, CAPTURE, PWM1, and PWM2.
Page 213 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) The period is calculated as follows: FTnP + 1 (FTnP : 0001H to FFFFH) priod FTnCK [Hz] 6: Output setting (FTOSL*, Each Port Setting) Set which output to which port, and reverse. 7: Control start/stop (FTnCON0) Allow the software start or event trigger reception.
Page 214: Counter Operation
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.2 Counter Operation The internal counter of FTM operates in the same way in all the modes. It counts up until the setting value of the FTMn period register (FTnP). At overflow in auto-reload mode (FTnOST bit of the FTMn mode register (FTnMOD) is "0"), the counter is cleared and continues counting again.
Page 215: Timer Mode Operation
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.3 TIMER Mode Operation The TIMER mode controls the interrupt generation and output signal using the counter overflow. 9.3.3.1 Output Waveform in TIMER Mode In the timer output auto-reload modem, the output is toggled for each period. If the counter value is "0000H", FTMnP starts with L and FTMnN starts with H when FTnRUN bit of the FTMn control register 0 (FTnCON0) is set to "1".
Page 216 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) FTnP Counter FTnDT FTnSTAT Without dead time FTMnP FTMnN With dead time FTMnP FTMnN (b) TIMER mode output waveform (auto-reload mode) FEUL620Q504 9–33...
Page 217 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) FTnP BUF Counter FTnEB BUF FTnEA BUF FTnDT BUF FTnSTAT FTnFLGA FTnFLGB (FTnDTEN = 0) (Auto-reload mode) FTMnP FTMnN (One-shot mode) FTMnP FTMnN (FTnDTEN = 0) (Auto-reload mode) FTMnP FTMnN (One-shot mode) FTMnP FTMnN FTnISA FTnISB...
Page 218: Pwm1 Mode Operation
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.4 PWM1 Mode Operation The PWM1 mode generates synchronization output pulses with the period set in FTnP. The duties of the output FTMnP and FTMnN are set in FTnEA and FTnEB respectively. 9.3.4.1 Output Waveform in PWM1 Mode In the Auto-reload mode, the initial values of FTMnP and FTMnN are L, and they change to H at start.
Page 219 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) FTnP Counter FTnEA FTnEB FTnDT FTnSTAT Without dead time FTMnP FTMnN With dead time FTMnP FTMnN (b) PWM1 mode output waveform (auto-reload mode) Figure 9-3 waveform in PWM1 mode FEUL620Q504 9–36...
Page 220: Pwm2 Mode Operation
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.5 PWM2 Mode Operation The PWM2 mode generates a complementary output pulse with the cycle set in FTnP. Set the duties of the output FTMnP/N in FTnEA. FTnEB is not used. 9.3.5.1 Output Waveform in PWM2 Mode In the Auto-reload mode, the initial values of FTMnP and FTMnN are L, and FTMnP changes to H at start.
Page 221 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) FTnP FTnEA+FTnDT FTnEA Counter FTnDT FTnSTAT Without dead time FTMnP FTMnN With dead time FTMnP FTMnN (b) PWM2 mode output waveform (auto-reload mode) FEUL620Q504 9–38...
Page 222 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) FTnP BUF Counter FTnEB BUF FTnEA BUF FTnDT BUF FTnSTAT FTnFLGA FTnFLGB (FTnDT = 0) (Auto-reload mode) FTMnP FTMnN (One-shot mode) FTMnP FTMnN (FTnDT > 0) (Auto-reload mode) FTMnP FTMnN (One-shot mode) FTMnP FTMnN FTnISA FTnISB...
Page 223: Capture Mode Operation
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.6 CAPTURE Mode Operation The CAPTURE mode stores the count value at the time when an event trigger source is generated, to the FTnEA/FTnEB register. The event trigger source to be captured is common to that used at counter start/stop. Stored data in FTnEA Counter value at the time when an event trigger rising edge is generated Stored data in FTnEB...
Page 224 ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) The operation after capture depends on the FTnOST bit of the FTnMOD register. When FTnOST=0 (auto mode) After the counter restarts at the next rising of EXI0, the value of FTnEA is updated at falling of EXI0. When FTnOST=1 (single mode) After the counter restarts at the next rising of EXI0, the value of FTnEA is not updated at falling of EXI0.
Page 225: Event/Emergency Stop Trigger Control
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.7 Event/Emergency Stop Trigger Control 9.3.7.1 Trigger Signal FTMn can receive two types of trigger signal: event trigger and emergency stop trigger. The event trigger is used as counter start/stop or trigger of capture. EXI0-7 (external interrupts), TIMER0-7 interrupts, or FTM0-3 triggers can be selected as the trigger source.
Page 226: Start/Stop Operations By Eventtrigger
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.7.2 Start/Stop Operations by Event Trigger Here is the setting used to control the counter by event triggers. 1) FTnTRG0 setting Enable/Disable counter start/stop by event triggers Set whether or not to clear the counter at stop by an event trigger Set whether or not to accept the next counter start after stop by an event trigger Set the event trigger source (EXI0-7TGO, TIMER0-7INT, FTM0-3TGO) 2) FTnTRG1 setting...
Page 227: Emergency Stopoperation
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.7.3 Emergency Stop Operation When FTnEMGEN is set to "1", the emergency stop function is enabled. Set this bit after the trigger source is selected in FTnEST. If an emergency stop trigger input (rising edge) is detected, the counter stops, the output is set to L, and an emergency stop interrupt occurs.
Page 228: Output At Counter Stop
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.8 Output at Counter Stop The FTMnP and FTMnN states depend on the setting of FTnSTPO when the counter stops by a software/Event trigger. If FTnSTPO is "0", FTMnP/FTMnN is set to "L" at the same time as stop. If the counter is restarted in this state, the FTMnP/FTMnN outputs keep "L"...
Page 229: Changing Period, Event A/B, And Dead Time During Operation
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.9 Changing Period, Event A/B, and Dead Time during Operation The period, event A/B, and dead time can be changed in the next cycle when the timer is counting. To do so, set desired registers (FTnP, FTnEA, FTnEB, FTnDT, etc.), and then write "1" to the FTnUD bit of the FTnCON1 register to request the update.
Page 230: Interrupt Source
ML620Q503/Q504 User's Manual Chapter 9 Function Timer(FTM) 9.3.10 Interrupt Source This section describes the interrupt source and how to clear it. When a target interrupt enable (FTnIE*) is set to "1", the interrupt status is enabled, and the interrupt controller is notified of the source.
Page 231: Watchdog Timer
Chapter 10 Watchdog Timer...
Page 232: Overview
ML620Q503/Q504 User’s Manual Chapter 10 Watchdog Timer 10 Watchdog Timer 10.1 Overview Watchdog timer is free run counter that is used for detection of program abnormal behavior. The watchdog timer start count automatically after system reset release and requests WDT interrupt when the first overflow occurs.
Page 233: Description Of Registers
ML620Q503/Q504 User’s Manual Chapter 10 Watchdog Timer 10.2 Description of Registers 10.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F00E Watchdog timer control register WDTCON – 0F00F Watchdog timer mode register WDTMOD – FEUL620Q504 10–2...
Page 234: Watchdog Timer Control Register (Wdtcon)
ML620Q503/Q504 User’s Manual Chapter 10 Watchdog Timer 10.2.2 Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: R/W Access size: 8 bits Initial value: 00H WDTCON WDP/d0 Initial value WDTCON is a special function register (SFR) to control the Watchdog Timer. When write to WDTCON, the value of the internal pointer (WDP) is reversed .
Page 235: Watchdog Timer Mode Register (Wdtmod)
ML620Q503/Q504 User’s Manual Chapter 10 Watchdog Timer 10.2.3 Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: R/W Access size: 8 bits Initial value: 82H – – – – – WDTMOD HLTEN WDT1 WDT0 Initial value WDTMOD is a special function register to set the overflow period of theWDT counter. This register requires byte access always.
Page 236: Description Of Operation
ML620Q503/Q504 User’s Manual Chapter 10 Watchdog Timer 10.3 Description of Operation The WDT counter starts counting after the system reset has been released and the low-speed clock(LSCLK) oscillation start. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" when WDP is "1".
Page 237 ML620Q503/Q504 User’s Manual Chapter 10 Watchdog Timer Figure 10-2 shows an example of watchdog timer operation. Program Low-speed Occurrence of start oscillation start abnormality ① WDTMOD RESET_N WDTMOD setting setting System reset    Data: WDTCON Write WDTP Internal pointer Overflow WDT counter ⑥Occurrence of...
Page 238: The Process Example When Not Using Watchdog Timer
ML620Q503/Q504 User’s Manual Chapter 10 Watchdog Timer 10.3.1 The process example when not using Watchdog Timer Watchdog timer cannot be stopped. Even when the watchdog timer function is not used as failsafe measures, it is necessary to clear WDT counter. The example program which clears WDT counter at WDT interrupt occurs, and controls the system reset by WDT is shown.
Page 239: Synchronous Serial Port
Chapter 11 Synchronous Serial Port (SSIO)
Page 240: Overview
ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) 11 Synchronous Serial Port 11.1 Overview This LSI includes one channel of the 8/16-bit synchronous serial port (SSIO) and can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable pin. 11.1.1 Features •...
Page 241: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) 11.2 Description of Registers 11.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F700 SIO0BUFL 8/16 Serial port 0 transmit/receive SIO0BUF buffer 0F701 SIO0BUFH 0F702 Serial port 0 control register SIO0CON –...
Page 242 ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) 11.2.2 Serial Port 0 Transmit/Receive Buffer (SIO0BUF) Address: 0F700H Access: R/W Access size: 8/16 bits Initial value: 0000H SIO0BUFL S0B7 S0B6 S0B5 S0B4 S0B3 S0B2 S0B1 S0B0 Initial value SIO0BUFH S0B15 S0B14 S0B13 S0B12...
Page 243 ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) 11.2.3 Serial Port 0 Control Register (SIO0CON) Address: 0F702H Access: R/W Access size: 8 bits Initial value: 00H – – – – – – – S0EN Initial value SIO0CON is a special function register (SFR) to control the synchronous serial port 0. Description of Bits •...
Page 244: Serial Port Mode Register (Sio0Mod)
ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) 11.2.4 Serial Port 0 Mode Register (SIO0MOD) Address: 0F704H Access: R/W Access size: 8/16bits Initial value: 0000H SIO0MOD0 – – – – S0LG S0MD1 S0MD0 S0DIR Initial value SIO0MOD1 – – S0NEG S0CKT –...
Page 245 ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) • S0CK2-0 (bits 10 to 8) The S0CK2-0 bits are used to select the transfer clock of the synchronous serial port. When the internal clock is selected, this LSI is set to master mode and when the external clock is selected, it is set to slave mode. S0CK2 S0CK1 S0CK0...
Page 246: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) 11.3 Description of Operation 11.3.1 Transmit Operation When “1” is written to the S0MD1 bit and “0” is written to the S0MD0 bit of the serial mode register (SIO0MOD), this LSI is set to a transmit mode. When transmit data is written to the serial port transmit/receive buffer (SIO0BUF) and the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission starts.
Page 247 ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) S0EN SCK0 SIO0TRL Transmit data SOUT0 SIO0INT Figure 11-4 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 (8-bit Length, LSB first, Positive Logic) S0EN SCK0 SIO0TRL Transmit data SOUT0 SIO0INT Figure 11-5 Transmit Operation Waveforms of Synchronous Serial Port...
Page 248: Receive Operation
ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) 11.3.2 Receive Operation When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD), this LSI is set to a receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, reception starts.
Page 249 ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) S0EN SCK0 SIN0 Shift register SIO0RCL Receive data SIO0INT Figure 11-8 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 1 (8-bit Length, MSB first, Positive Logic) S0EN SCK0 SIN0 Shift register SIO0RCL Receive data...
Page 250: Transmit/Receive Operation
ML620Q503/Q504 User's Manual Chapter 11 Synchronous Serial Port (SSIO) 11.3.3 Transmit/Receive Operation When “1” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD), this LSI is set to a transmit/receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission/reception starts.
Page 251: Synchronous Serial Port With Fifo (Ssiof)
Chapter 12 Synchronous Serial Port with FIFO (SSIOF)
Page 252: General Description
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12 Synchronous Serial Port with FIFO (SSIOF) 12.1 General Description The synchronous serial port with FIFO (SSIOF) can communicate with peripherals and other MCUs. The use of SSIOF requires the function setting of the ports 2, 3, 4 and 5. For the port function setting, see Chapter 19 "Port 2", Chapter 20 "Port 3", Chapter 21 "Port 4", and Chapter 22 "Port 5".
Page 253: Configuration
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.1.2 Configuration Figure 12-1 shows the configuration of the SSIOF. Tfifo_H Tfifo_L SOUTF0 Tshifter Tshifter "1" "1" P20/P34/ P44/P54 SINF0 Rshifter Rshifter P21/P35/ P45/P55 Rfifo_H Rfifo_L SYSCLK Control SCKF0 section P22/P36/ P46/P56 HSCLK...
Page 254: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2 Description of Registers 12.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F780 SF0CTRLL 8/16 SIOF0 control register SF0CTRL 0F781 SF0CTRLH 0F782 SF0INTCL 8/16 SIOF0 interrupt control register SF0INTC 0F783 SF0INTCH...
Page 255: Siof0 Control Register (Sf0Ctrl)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.2 SIOF0 Control Register (SF0CTRL) Address: 0F780H Access: R/W Access size: 8/16 bits Initial value: 0000H SF0CTRLL – SF0LSB SF0SIZ SF0MST SF0SPE SF0CPOL SF0CPHA SF0MDFE Initial value SF0CTRLH – – –...
Page 256 ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO • SF0LSB (bit 4) SF0LSB sets the data transfer order. SF0LSB Description LSB first (initial value) MSB first • SF0CPHA (bit 5) SF0CPHA sets the serial clock phase. SF0CPHA Description The data is sampled at the first edge and shifted at the second edge (initial value) The data is shifted at the first edge and sampled at the second edge •...
Page 257: Siof0 Interrupt Control Register (Sf0Intc)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.3 SIOF0 Interrupt Control Register (SF0INTC) Address: 0F782H Access: R/W Access size: 8/16 bits Initial value: 0000H SF0INTCL – – – SF0MFIE SF0ORIE SF0FIE SF0RFIE SF0TFIE Initial value SF0INTCH – –...
Page 258 ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO • SF0MFIE (bit 4) SF0MFIE sets whether or not to enable the SSIOF mode fault interrupt. SF0MFIE Description Interrupt disabled (initial value) Interrupt enabled • SF0TFIC1-0 (bits 9 to 8) SF0TFIC1-0 set the remaining byte count interrupt control for the transmit FIFO.
Page 259: Siof0 Transfer Interval Control Register (Sf0Trac)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.4 SIOF0 Transfer Interval Control Register (SF0TRAC) Address: 0F784H Access: R/W Access size: 16 bits Initial value: 0002H SF0DTL7 SF0DTL6 SF0DTL5 SF0DTL4 SF0DTL3 SF0DTL2 SF0DTL1 SF0DTL0 Initial value – – –...
Page 260: Siof0 Baud Rate Register (Sf0Brr)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.5 SIOF0 Baud Rate Register (SF0BRR) Address: 0F786H Access: R/W Access size: 16 bits Initial value: 5002H SF0BR7 SF0BR6 SF0BR5 SF0BR4 SF0BR3 SF0BR2 SF0BR1 SF0BR0 Initial value – – SF0BR9 SF0BR8 SF0LAG1 SF0LAG0...
Page 261 ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO • SF0LAG1-0 (bits 15 to 14) SF0LAG1-0 set the SCKF0-SSF0(H) delay interval (setting enabled only in Master mode). SF0LAG1 SF0LAG0 Description 0.5 X SCK 0.5 X SCK (initial value) 1.0 X SCK 1.5 X SCK FEUL620Q504 12–10...
Page 262: Siof0 Status Register (Sf0Srr)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.6 SIOF0 Status Register (SF0SRR) Address: 0F788H Access: R Access size: 8/16 bits Initial value: 1400H SF0SRRL – – SF0SPIF SF0MDF SF0ORF SF0FI SF0RFI SF0TFI Initial value SF0SRRH – – –...
Page 263 ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO • SF0ORF (bit 3) SF0ORF indicates the overrun error flag. SF0ORF Description Normal (initial value) An overrun error occurred (an interrupt is generated) • SF0MDF (bit 4) SF0MDF indicates a mode fault. SF0MDF Description Normal (initial value)
Page 264 ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO • SF0RFE (bit 12) SF0RFE indicates the receive FIFO Empty. SF0RFE Description Not Empty Empty (No interrupt is generated) (initial value) FEUL620Q504 12–13...
Page 265: Siof0 Status Clear Register (Sf0Src)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.7 SIOF0 Status Clear Register (SF0SRC) Address: 0F78AH Access: W Access size: 8/16 bits Initial value: 0000H – – SF0SPIFC SF0MDFC SF0ORFC SF0FC SF0RFC SF0TFC SF0SRCL Initial value SF0IRQ – –...
Page 266 ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO [Note] Write "1" to SF0IRQ bit while there is any unprocessed interrupt source and processing all the interrupt sources before exiting the interrupt vector will cause re-entry to the interrupt vector with no interrupt source after exiting the interrupt vector.
Page 267: Siof0 Fifo Status Register (Sf0Fsr)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.8 SIOF0 FIFO Status Register (SF0FSR) Address: 0F78CH Access: R Access size: 8/16 bits Initial value: 0000H SF0FSRL SF0TFD2 SF0TFD1 SF0TFD0 Initial value SF0FSRH SF0RFD2 SF0RFD1 SF0RFD0 Initial value SF0FSR is a special function register (SFR) used to indicate the count transmitted and received by FIFO. Description of Bits •...
Page 268: Siof0 Write Data Register (Sf0Dwr)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.9 SIOF0 Write Data Register (SF0DWR) Address: 0F78EH Access: R/W Access size: 8/16 bits Initial value: 0000H SF0DWRL SF0WD7 SF0WD6 SF0WD5 SF0WD4 SF0WD3 SF0WD2 SF0WD1 SF0WD0 Initial value SF0DWRH SF0WD9 SF0WD8 SF0WD15 SF0WD14...
Page 269: Siof0 Read Data Register (Sf0Drr)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.2.10 SIOF0 Read Data Register (SF0DRR) Address: 0F790H Access: R Access size: 8/16 bits Initial value: 0000H SF0DRRL SF0RD7 SF0RD6 SF0RD5 SF0RD4 SF0RD3 SF0RD2 SF0RD1 SF0RD0 Initial value SF0DRRH SF0RD9 SF0RD8 SF0RD15 SF0RD14...
Page 270: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3 Description of Operation 12.3.1 Master Mode and Slave Mode Master mode and Slave mode are provided as the transmit/receive mode. This is selected by the SF0MST bit of the SIOF0 control register. SF0BR (baud rate), SF0LEAD (SSF0-SCKF0 delay interval), and SF0LAG (SCKF0-SSF0 delay interval) of the SIOF0 baud rate register and SF0DTL (minimum data transfer interval) of the SIOF0 transfer interval control register determine SCKF0 and SSF0 operations and are only valid during the master operation.
Page 271: Serial Clock Baud Rate
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.4 Data Transfer Timing When SF0CPHA Is "1" Figure 12-3 shows the data transfer timing when SF0CPHA is "1". For the SCKF0, two cases are shown (SF0CPOL is "0" and "1"). SSF0 is the slave selection input in Slave mode.
Page 272: Transfer Size
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.6 Transfer Size The transfer size can be selected in 8 bits (byte) or 16 bits (word). Transfer data read/write must be adjusted to the transfer size. As the number of FIFO stages is the same for both byte and word, the number of transfers is the same.
Page 273: Transfer Interval Setting
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.7 Transfer Interval Setting LEAD (SSF0-SCKF0 time), LAG (SCKF0-SSF0(H) time), and TDTL (SSF0(H)-SSF0(H)) can be set to adjust the speed to the slave. This setting is only valid in Master mode. It is ignored in Slave mode. Setting during transferring is invalid.
Page 274 ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO SCKF0 Cycle Continuous clock SCKF0 Continuous data SOUTF0/ SINF0 SSF0 LEAD Figure 12-7 Transfer Interval (When SF0DTL Is "0") FEUL620Q504 12–23...
Page 275: Transmit Operation (Master Mode)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.8 Transmit Operation (Master Mode)  Write the necessary values to SF0CTRL, SF0INTC, SF0BRR, and SF0TRAC, set the SF0MST bit to Master mode, and set the SF0SPE bit to enable the SSIOF transfer. ...
Page 276: Receive Operation (Master Mode)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.9 Receive Operation (Master Mode) The master mode of the synchronous serial with FIFO starts by setting data in a transmission buffer. Data needs to be set into a transmission buffer even master mode reception only. ...
Page 277: Fifo Operation
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.10 FIFO Operation SSIOF includes the receive FIFO of 4 words and the transmit FIFO of 4 words. The FIFO state is indicated in the SF0TFF, SF0TFE, SF0RFF, and SF0RFE bits of SF0SRR, and the SF0TFD and SF0RFD bits of SF0FSR. There are three FIFO states, Full (SF0TFF and SF0RFF), Empty (SF0TFE and SF0RFE), and Depth (SF0TFD and SF0RFD).
Page 278 ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.14 Transfer When Slave Has Different Number of FIFO Transfer Bytes/Words (1) The master sends data only when the transmitted data is already written in FIFO. (2) As the slave's transmit data count is determined by the master, data is transferred as follows if the number of FIFO transfer bytes/words of slave is different from that of the master.
Page 279: Mode Fault (Mdf)
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.15 Mode Fault (MDF) A mode fault error occurs if the SSF0 signal becomes low level in Master mode. (SF0SRR's SF0MDF is set.) If this bit becomes 1, it indicates that there is risk of two or more masters competing for the bus. When a mode fault error occurs, SSIOF performs the following operations since there is a risk of bus latch-up: Automatically sets the SF0MST bit of SF0CTRL to 0 (slave).
Page 280: Interrupt Source
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.16 Interrupt Source 12.3.16.1 SSIOF Interrupt Source There are the following five types. • Mode fault If a mode fault (multi-master bus contention) occurs, SF0MDF of SF0SRR is set and a mode fault interrupt is generated.
Page 281: Interrupt Processing Flow
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.16.4 Interrupt processing flow Figure 12-13 show the processing flow in the receiving operation of the slave mode. SSIOF Interrupt occurrence (=0) (Interrupt factor check) SF0SRR.SF0RFI Other factor (=1) processing (Clear processing of SF0RFI) Write “1”...
Page 282: Hi-Z Operation
ML620Q503/Q504 User's Manual Chapter 12 Synchronous Serial Port with FIFO 12.3.17 Hi-Z Operation Figure 12-14 shows an example of using Hi-Z (SF0MOZ, SF0SOZ, and SF0SSZ). The Hi-Z transmit interval of the master is limited to the IDLE time shown below. To reduce the effect of noise in the Hi-Z state, "1"/"0"...
Page 283: Uart
Chapter 13 UART...
Page 284: General Description
ML620Q503/Q504 User's Manual Chapter 13 UART 13 UART 13.1 General Description This LSI includes one channel of UART (Universal Asynchronous Receiver Transmitter), a full-duplex communication start-stop synchronous serial interface. For input clocks, see Chapter 6, "Clock Generation Circuit". To use the UART, it needs to set the secondary and quartic functions of the ports 0, 3, 4, and 5. For the port function setting, see Chapter 17 "Port 0", Chapter 20 "Port 3", Chapter 21 "Port 4", and Chapter 22 "Port5".
Page 285: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 13 UART 13.1.3 List of Pins Pin Name Function RXD0 UART0 data input pin TXD0 UART0 data output pin 13.2 Description of Registers 13.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F710 UART0 receive buffer UA0BUF...
Page 286: Uart0 Receive Buffer (Ua0Buf)
ML620Q503/Q504 User's Manual Chapter 13 UART 13.2.2 UART0 Receive Buffer (UA0BUF) Address: 0F710H Access: R/W Access size: 8 bits Initial value: 00H UA0BUF U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 Initial value UA0BUF is a special function register (SFR) used to store the received data. Since data received at termination of reception is stored in UA0BUF, read the contents of UA0BUF using the UART0 interrupt at termination of reception.
Page 287: Uart0 Control Register (Ua0Con)
ML620Q503/Q504 User's Manual Chapter 13 UART 13.2.4 UART0 Control Register (UA0CON) Address: 0F711H Access: R/W Access size: 8 bits Initial value: 00H UA0CON – – – – – – – U0EN Initial value UA0CON is a special function register (SFR) used to start/stop communication of the UART. Description of Bits •...
Page 288: Uart0 Transmit Monitor Register (Ua1Con)
ML620Q503/Q504 User's Manual Chapter 13 UART 13.2.5 UART0 Transmit Monitor Register (UA1CON) Address: 0F719H Access: R/W Access size: 8 bits Initial value: 00H UA1CON – – – – – – – U1EN Initial value UA1CON is a special function register(SFR) which indicate UART transmission status. Description of Bits •...
Page 289: Uart0 Mode Register (Ua0Mod)
ML620Q503/Q504 User's Manual Chapter 13 UART 13.2.6 UART0 Mode Register (UA0MOD) Address: 0F712H Access: R/W Access size: 8/16 bit Initial value: 0000H UA0MOD0 – U0RSS – – – U0CK1 U0CK0 – Initial value UA0MOD1 – U0DIR U0NEG U0STP U0PT1 U0PT0 U0LG1 U0LG0 Initial value...
Page 290 ML620Q503/Q504 User's Manual Chapter 13 UART • U0PT1-0 (bits 11 to 10) The U0PT1-0 bits are used to select "even parity", "odd parity", or "no parity" in the communication of the UART. U0PT1 U0PT0 Description Even parity (initial value) Odd parity No parity bit •...
Page 291: Uart0 Baud Rate Registers (Ua0Brt)
ML620Q503/Q504 User's Manual Chapter 13 UART 13.2.7 UART0 Baud Rate Register (UA0BRT) Address: 0F714H Access: R/W Access size: 8/16 bit Initial value: 0FFFH UA0BRTL U0BR7 U0BR6 U0BR5 U0BR4 U0BR3 U0BR2 U0BR1 U0BR0 Initial value UA0BRTH – – – – U0BR11 U0BR10 U0BR9 U0BR8...
Page 292: Uart0 Receive Status Register (Ua0Stat)
ML620Q503/Q504 User's Manual Chapter 13 UART 13.2.8 UART0 Receive Status Register (UA0STAT) Address: 0F716H Access: R/W Access size: 8 bits Initial value: 00H UA0STAT – – – – – U0PER U0OER U0FER Initial value UA0STAT is a special function register (SFR) used to indicate the UART state in receive operations. When any data is written to UA0STAT, all the flags are initialized to "0".
Page 293: Uart0 Transmit Status Register (Ua1Stat)
ML620Q503/Q504 User's Manual Chapter 13 UART 13.2.9 UART0 Transmit Status Register (UA1STAT) Address: 0F71EH Access: R/W Access size: 8 bits Initial value: 00H UA1STAT – – – – U1FUL – – – Initial value UA1STAT is a special function register (SFR) used to indicate the UART state in transmit operations. When any data is written to UA1STAT, all the flags are initialized to "0".
Page 294: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 13 UART 13.3 Description of Operation 13.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can be selected as data bit.
Page 295: Baud Rate
ML620Q503/Q504 User's Manual Chapter 13 UART 13.3.2 Baud Rate Baud rates are generated by the baud rate generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (U0CK1, U0CK0) of the UART0 mode register 0 (UA0MOD0). The count value of the baud rate generator can be set by writing it in the UART0 baud rate register (UA0BRT).
Page 296: Transmitted Data Direction
ML620Q503/Q504 User's Manual Chapter 13 UART 13.3.3 Transmitted Data Direction Figure 13-4 shows the relationship between the transmit/receive buffer and the transmit/receive data. Transmit:n=1, Receive:n=0 Data length: 8 bits LSB transmission LSB reception UnB7 UnB6 UnB5 UnB3 UnB2 UnB0 UnB4 UnB1 MSB transmission MSB reception...
Page 297: Transmit Operation
ML620Q503/Q504 User's Manual Chapter 13 UART 13.3.4 Transmit Operation Transmission is started by setting the U0EN bit of the UART0 control register (UA0CON) to "1" and set transfer data to UA1BUF. The order of UA0EN setting and UA1BUF setting does not matter. Figure 13-5 shows the operation timing for transmission.
Page 298 ML620Q503/Q504 User's Manual Chapter 13 UART Figure 13-5 Operation Timing in Transmission FEUL620Q504 13–15...
Page 299: Receive Operation
ML620Q503/Q504 User's Manual Chapter 13 UART 13.3.5 Receive Operation Select the receive data pin using the U0RSEL bit of the UART0 mode register 0 (UA0MOD0). Reception is started by setting the U0EN bit of the UART0 control register (UA0CON) to "1". Figure 13-6 shows the operation timing for reception.
Page 300 ML620Q503/Q504 User's Manual Chapter 13 UART Figure 13-6 Operation Timing in Reception FEUL620Q504 13–17...
Page 301: Detection Of Start Bit
ML620Q503/Q504 User's Manual Chapter 13 UART 13.3.5.1 Detection of Start Bit The start bit is sampled with the baud rate generator clock (OSCLK). Therefore, the start bit detection may be delayed for one cycle of the baud rate generator clock at the maximum. Figure 13-7 shows the start bit detection timing.
Page 302: Receive Margin
ML620Q503/Q504 User's Manual Chapter 13 UART 13.3.5.3 Receive Margin If there is an error between the sender baud rate and the baud rate generated by the baud rate generator of this LSI, the error accumulates until the last stop bit loading in one frame, decreasing the receive margin. Figure 13-9 shows the baud rate errors and receive margin waveforms.
Page 303: Uart With Fifo (Uartf)
Chapter 14 UART with FIFO (UARTF)
Page 304: General Description
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14 UART with FIFO (UARTF) 14.1 General Description The UART with FIFO (UARTF) functions as the input/output interface, carries out serial-to-parallel conversion of the data sent from the peripheral devices, and also converts the parallel data sent from the CPU into serial data. The UARTF has a 4-byte FIFO for transmission and reception, capable of storing up to 4 bytes of data during transmission/reception in the FIFO mode.
Page 305: Configuration
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.1.2 Configuration Figure 14-1 shows the configuration of the UARTF. BUF(RBR) RXDF0 4Byte P20/P34/ Bus signal FIFO Receive P44/P54 control BUF(DLR) Baud rate generation Transmiss ion control 4Byte FIFO BUF(THR) TXDF0 P21/P35/ P45/P55 Interrupt control...
Page 306: List Of Pins
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.1.3 List of Pins Pin Name Function RXDF0 UARTF0 data input pin TXDF0 UARTF0 data output pin 14.2 Description of Registers 14.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F7C0...
Page 307: Uartf0 Transmit/Receive Buffer (Uaf0Buf)
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.2.2 UARTF0 Transmit/Receive Buffer (UAF0BUF) Address: 0F7C0H Access: R/W Access size: 8/16 bits Initial value: Undefined UAF0BUFL UF0B7 UF0B6 UF0B5 UF0B4 UF0B3 UF0B2 UF0B1 UF0B0 Initial value UAF0BUFH UF0B15 UF0B14 UF0B13 UF0B12 UF0B11 UF0B10 UF0B9...
Page 308: Uartf0 Interrupt Enable Register (Uaf0Ier)
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.2.3 UARTF0 Interrupt Enable Register (UAF0IER) Address: 0F7C2H Access: R/W Access size: 8/16 bits Initial value: 0000H UAF0IERL – – – – – UF0ELSI UF0ETBEI UF0ERBFI Initial value UAF0IERH – – – –...
Page 309: Uartf0 Interrupt Status Register (Uaf0Iir)
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.2.4 UARTF0 Interrupt Status Register (UAF0IIR) Address: 0F7C4H Access: R Access size: 8/16 bits Initial value: 0001H UAF0IIRL – – UF0IRID2 UF0IRID1 UF0IRID0 UF0IRP UF0FMD1 UF0FMD0 Initial value UAF0IIRH – – – –...
Page 310 ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) • UF0IRID2-0 (bits 3 to 1) UF0IRID2-0 indicate the interrupt source of the UARTF0 interrupt. LVL=1 is the highest priority. The highest-priority interrupt source is notified. UF0IRID Flag Source Reset Process 2 to 0 –...
Page 311: Uartf0 Mode Register (Uaf0Mod)
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.2.5 UARTF0 Mode Register (UAF0MOD) Address: 0F7C6H Access: R/W Access size: 8/16 bits Initial value: 0000H UAF0MODL UF0BC UF0PT2 UF0PT1 UF0PT0 UF0STP UF0LG1 UF0LG0 UF0DLAB Initial value UAF0MODH UF0FTL1 UF0FTL0 – – –...
Page 312 ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) • UF0BC (bit 6) UF0BC selects the break control of UARTF0. Turning this to "1" brings the UARTF0 data output (TXDF0) to the spacing state (logical 0). The control by this bit is valid only on the TXDF0 pin. This means that TXDF0 is masked but the transmit operation continues internally.
Page 313 ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) • UF0FTL1-0 (bits 15 to 14) UF0FTL1-0 select the trigger level for the receive FIFO interrupt. UF0FTL1 UF0FTL0 Description 1 byte (initial value) 2 bytes 3 bytes 4 bytes FEUL620Q504 14-10...
Page 314: Uartf0 Line Status Register (Uaf0Lsr)
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.2.6 UARTF0 Line Status Register (UAF0LSR) Address: 0F7C8H Access: R Access size: 8/16 bits Initial value: 0060H UAF0LSRL UF0RFE UF0BI UF0FER UF0PER UF0OER UF0DR UF0TEMT UF0THRE Initial value UAF0LSRH – – – –...
Page 315 ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) • UF0PER (bit 2) UF0PER indicates that a parity error occurred. This is enabled only when parity is enabled. This bit is cleared when UAF0LSR is read. In FIFO mode, this bit indicates that an error exists for the leading data. If a parity error occurs in the data that is not the leading data in the FIFO, it is not reflected to this bit.
Page 316 ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) • UF0TEMT (bit 6) UF0TEMT is set to "1" when both THR and the shift register for transmission (TSR) are empty. When a character is loaded into THR, this bit is cleared to "0" and remains "0" until the character is transferred from TXDF0.
Page 317: Uartf0 Clock Adjustment Register (Uaf0Caj)
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.2.7 UARTF0 Clock Adjustment Register (UAF0CAJ) Address: 0F7CAH Access: R/W Access size: 8/16 bits Initial value: 000DH UAF0CAJL – – – UF0CAJ4 UF0CAJ3 UF0CAJ2 UF0CAJ1 UF0CAJ0 Initial value UAF0CAJH – – – –...
Page 318: Uartf0 Interrupt Request Register (Uaf0Irq)
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.2.8 UARTF0 Interrupt Request Register (UAF0IRQ) Address: 0F7CCH Access: W Access size: 8/16 bits Initial value: 0000H UAF0IRQL – – – – – – – UF0IRQ Initial value UAF0IRQH – – – –...
Page 319: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.3 Description of Operation The UART is programmed with UAF0IER, UAF0MOD, DLR(UAF0BUF), and UAF0CAJ. These registers define the character length, number of stop bits, parity, baud rate, etc. Though the registers can be written in any order, UAF0IER needs to be written to last because it controls the interrupt enable.
Page 320: Data Reception
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.3.2 Data Reception Figure 14-4 shows the reception timing. Figure 14-5 shows the timing when the first byte in the receive FIFO is read, and Figure 14-6 the reception timing when the remaining bytes in the receive FIFO are read. The sampling clock is obtained by dividing the baud rate clock by 8.
Page 321 ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) RXDF0 Start Data bit (5～8) Parity Stop Sample CLK FIFO below Trigger Level UAF0INT (Received Data Available) FIFO at or above tSINT tRINT Trigger Level UAF0INT (Received Line Status) tRINT LSR read RBR read tSINT: MAX 3 Buad rate Clocks...
Page 322: Baud Rate Clock Generation
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.3.3 Baud Rate Clock Generation A baud rate is obtained by the following expression: Baud rate frequency = SYSCLK x (UAF0CAJ-1)/UAF0CAJ/(DLR[15:0] x 16) Although actually available baud rate for communication depends on the software processing, a 115200bps baud rate can be used for communication with the DLR=8 setting in an ideal state of 16MHz SYSCLK.
Page 323: Fifo Mode
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.3.4 FIFO Mode When the receive FIFO and reception interrupt are both enabled, reception interrupts are generated as follows: If the number of characters present within the FIFO exceeds the programmed trigger level, a received data read request interrupt is generated.
Page 324: Fifo Polled Mode
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.3.5 FIFO Polled Mode If FIFO is enabled and UF0ELSI, UF0ETBEI, and UF0ERBFI of UAF0IER are "0", the UART operates in the FIFO polled mode. Since the receiver section and transmitter section can be controlled separately, either one (or both) can be set to FIFO polled mode.
Page 325: Error Status
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.3.6 Error Status Overrun error An overrun error indicates that the data in RBR was not read before the next character was sent to RBR to overwrite the previous character. At this time, UF0OER of UAF0LSR is set. Parity error A parity error indicates that the parity of the received data and the received parity bit did not match.
Page 326: Reset By Block Control Register
ML620Q503/Q504 User's Manual Chapter 14 UART with FIFO(UARTF) 14.3.7 Reset By Block Control Register If using DUAF0 bit of BLKCON23 register as block reset, a sequence is the following: 1) Set DUAF0 bit to 1. If it is in the UARTF is transmission state, the TXD output will become indetermination. 2) Set DUAF0 bit to 0 again.
Page 327: I 2 C Bus Interface
Chapter 15 C Bus Interface...
Page 328: General Description
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15 I C Bus Interface 15.1 General Description The I C bus interface operates as the master device of I C bus and can communicate with the slave device. This LSI includes two channels of I C bus interface.
Page 329: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.2 Description of Registers 15.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) – 0F740 C bus 0 receive data register I2C0RD 0F742 C bus 0 slave address register I2C0SA –...
Page 330: C Bus N Receive Data Register (I2Cnrd : N=0,1)
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.2.2 I C Bus n Receive Data Register (I2CnRD : n=0,1) Address: 0F740H(I2C0RD), 0F750H(I2C1RD) Access: R Access size: 8 bits Initial value: 00H I2CnRD I2nR7 I2nR6 I2nR5 I2nR4 I2nR3 I2nR2 I2nR1 I2nR0 Initial value I2CnRD is a read-only special function register (SFR) to store the received data.
Page 331: C Bus N Slave Address Register (I2Cnsa : N=0,1)
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.2.3 I C Bus n Slave Address Register (I2CnSA : n=0,1) Address: 0F742H(I2C0SA), 0F752H(I2C1SA) Access: R/W Access size: 8 bits Initial value: 00H I2CnSA0 I2nA6 I2nA5 I2nA4 I2nA3 I2nA2 I2nA1 I2nA0 I2nRW Initial value I2CnSA is a special function register (SFR) to set the address and the transmit/receive mode of the slave device.
Page 332: C Bus N Transmit Data Register (I2Cntd : N=0,1)
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.2.4 I C Bus n Transmit Data Register (I2CnTD : n=0,1) Address: 0F744H(I2C0TD), 0F754H(I2C1TD) Access: R/W Access size: 8 bits Initial value: 00H I2CnTD0 I2nT7 I2nT6 I2nT5 I2nT4 I2nT3 I2nT2 I2nT1 I2nT0 Initial value I2CnTD is a special function register (SFR) used to set the transmitted data.
Page 333: C Bus N Control Register (I2Cncon : N=0,1)
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.2.5 I C Bus n Control Register (I2CnCON : n=0,1) Address: 0F746H(I2C0CON0/I2C0CON), 0F747H(I2C0CON1), 0F756H(I2C1CON0/I2C1CON), 0F757H(I2C1CON1) Access: R/W Access size: 8/16 bits Initial value: 0000H I2CnCON0 I2nACT – – – – I2nRS I2nSP I2nST Initial value...
Page 334 ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface • I2nRS (bit 2) The I2nRS bit is a write-only bit used to request a restart. When this bit is set to “1” during data communication, the I C bus shifts to the restart condition and communication restarts from the slave address.
Page 335: C Bus N Mode Register (I2Cnmod : N=0,1)
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.2.6 I C Bus n Mode Register (I2CnMOD : n=0,1) Address: 0F748H(I2C0MODL/I2C0MOD), 0F749H(I2C0MODH), 0F758H(I2C1MODL/I2C1MOD), 0F759H(I2C1MODH) Access: R/W Access size: 8/16 bits Initial value: 0200H I2CnMODL – – – – I2nDW1 I2nDW0 I2nMD I2nEN Initial value...
Page 336 ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface • I2nDW1-0 (bits 3 to 2) The I2nDW1-0 bits are used to set the communication speed reduction rate of the I C bus interface. Set this bit so that the communication speed does not exceed 100kbps/400kbps. I2nDW1 I2nDW0 Description...
Page 337: C Bus N Status Register (I2Cnstat : N=0,1)
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.2.7 I C Bus n Status Register (I2CnSTAT : n=0,1) Address: 0F74AH(I2C0STAL/I2C0STAT), 0F74BH(I2C0STAH) 0F75AH(I2C1STAL/I2C1STAT), 0F75BH(I2C1STAH) Access: R Access size: 8/16 bits Initial value: 0000H I2CnSTAL – – – – – I2nER I2nACR –...
Page 338: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.3 Description of Operation 15.3.1 Communication Operation Mode Communication is started when communication mode is selected by using the I C bus n mode register (I2CnMOD), the I C function is enabled by using the I2nEN bit, a slave address and a data communication direction are set in the I C bus n slave address register (I2CnSA), and “1”...
Page 339: Control Register Setting Wait State
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.3.1.6 Control Register Setting Wait State When the LSI shifts to the control register setting wait state, an I C bus n interface interrupt (I2CnINT) is generated. In the control register setting wait state, the transmit error flag (I2nER) of the I C bus n status register (I2CnSTAT) and acknowledgment receive data (I2nACR) are confirmed and at data reception, the contents of I2CnRD are read in the CPU and the next operation mode is selected.
Page 340 ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.3.2 Communication Operation Timing Figures 15-2 to 15-4 show the operation timing and control method for each communication mode. Start Stop Restart Reception of Transmission Transmission of condition condition condition acknowledg Non- ment acknowledgment...
Page 341 ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface Figure 15-5 shows the operation timing and control method when an acknowledgment error occurs. Acknowledge error Register I2CnSA=”xxxxxxx0B” setting I2CnCON=”01H” I2CnCON=”02H” Value of I2CnSA I2CnINT I2nST Value of I2CnRD I2CnSA I2nACR Figure 15-5 Operation Suspend Timing at Occurrence of Acknowledgment Error When the values of the transmitted bit and the SDA pin do not coincide, the I2nER bit of the I C bus n status...
Page 342: Operation Waveforms
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.3.3 Operation Waveforms Figure 15-7 shows the operation waveforms of the SDA and SCL signals. Table 15-2 shows the relationship between communication speeds and 1/mOSCLK clock counts. Start Restart Stop condition condition condition HD:STA...
Page 343: Pin Settings
ML620Q503/Q504 User's Manual Chapter 15 I C Bus Interface 15.3.4 Pin Settings To enable the I C function, the applicable bit of each related port register needs to be set. See Chapter 20, “Port 3”, Chapter 21, “Port 4”, and Chapter 22, “Port 5” for details about the port registers. For SCLn and SDAn, the ports can be selected from several possibilities.
Page 344: Port Xt
Chapter 16 Port XT...
Page 345: General Description
ML620Q503/Q504 User's Manual Chapter 16 Port XT 16 Port XT 16.1 General Description This LSI includes a 2-bit input port, port XT (PXT0, PXT1). It can function as an external interrupt input, a low-speed crystal oscillation pin, or an external clock input pin. When it is used as a low-speed crystal oscillation pin, the PXT1 pin functions as an output pin if the crystal oscillation mode is selected with the XTM1 to XTM0 bits of the FCON2 register.
Page 346: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 16 Port XT 16.2 Description of Registers 16.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) Depends on 0F208 Port XT data register PXTD – pin state 0F209 Port XT direction register PXTDIR –...
Page 347: Port Xt Data Register (Pxtd)
ML620Q503/Q504 User's Manual Chapter 16 Port XT 16.2.2 Port XT Data Register (PXTD) Address: 0F208H Access: R Access size: 8 bits Initial value: Depends on pin state PXTD PXT1D PXT0D – – – – – – Initial value PXTD is a read-only special function register (SFR) used to read the input level of the port XT pin. Description of Bits •...
Page 348: Port Xt Direction Register (Pxtdir)
ML620Q503/Q504 User's Manual Chapter 16 Port XT 16.2.3 Port XT Direction Register (PXTDIR) Address: 0F209H Access: R/W Access size: 8 bits Initial value: 00H PXT01DIR PXTDIR – – – – – – – Initial value PXTD is a special function register (SFR) used to enable the input port function of the port XT pin. Description of Bits •...
Page 349: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 16 Port XT 16.3 Description of Operation 16.3.1 Input Port Function In the initial state after system reset, input is disabled for both the pins of the port XT. When the pins of the port XT are set to the input state by the port XT direction register (PXTDIR), their input level can be read by reading the port XT data register (PXTD).
Page 350 Chapter 17 Port 0...
Page 351: Overview
ML620Q503/Q504 User’s Manual Chapter 17 Port 0 17 Port 0 17.1 Overview This LSI includes Port 0 (P00 to P05), which is a 6-bit input/output port. These ports can also be used as the SA-ADC, RC-ADC, SSIO, UART, FTM output pins. See the following chapters for reference: FTM: Chapter 9 “Function Timer”...
Page 352: List Of Pins
ML620Q503/Q504 User’s Manual Chapter 17 Port 0 17.1.3 List of Pins Fourthly function Pin name Primary function Secondary function Tertiary function P00/EXI00/AIN8/ Input/output port/ Oscillation IN0/ SSIO data output UART data input External Interrupt/ waveform input pin SOUT0/ SOUT0 RXD0 SA-ADC AIN8 for RC-ADC IN0 RXD0...
Page 353: Description Of Registers
ML620Q503/Q504 User’s Manual Chapter 17 Port 0 17.2 Description of Registers 17.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F210 Port 0 data register – 0F211 Port 0 direction register P0DIR – 0F212 P0CON0 8/16 Port 0 control register P0CON 0F213...
Page 354: Port 0 Data Register (P0D)
ML620Q503/Q504 User’s Manual Chapter 17 Port 0 17.2.2 Port 0 Data Register (P0D) Address: 0F210H Access: R/W Access size: 8 bits Initial value: 00H – – P05D P04D P03D P02D P01D P00D Initial value P0D is a special function register (SFR) to set the value to be output to the Port 0 pin or to read the input level of the Port 0.
Page 355: Port 0 Direction Register (P0Dir)
ML620Q503/Q504 User’s Manual Chapter 17 Port 0 17.2.3 Port 0 Direction Register (P0DIR) Address: 0F211H Access: R/W Access size: 8 bits Initial value: 00H P0DIR – – P05DIR P04DIR P03DIR P02DIR P01DIR P00DIR Initial value P0DIR is a special function register (SFR) to select the input/output mode of Port 0. Description of Bits •...
Page 356 ML620Q503/Q504 User’s Manual Chapter 17 Port 0 17.2.4 Port 0 Control Register (P0CON) Address: 0F212H Access: R/W Access size: 8/16 bits Initial value: 0000H P0CON0 – – P05C0 P04C0 P03C0 P02C0 P01C0 P00C0 Initial value P0CON1 – – P05C1 P04C1 P03C1 P02C1 P01C1...
Page 357 ML620Q503/Q504 User’s Manual Chapter 17 Port 0 When output mode is selected When input mode is selected Setting of P02 pin (P02DIR bit = “0”) (P02DIR bit = “1”) P02C1 P02C0 Description P02 pin: High-impedance output (initial P02 pin: High-impedance input value) P02 pin: P-channel open drain output P02 pin: Input with a pull-down resistor...
Page 358 ML620Q503/Q504 User’s Manual Chapter 17 Port 0 17.2.5 Port 0 Mode Register (P0MOD) Address: 0F214H Access: R/W Access size: 8/16 bits Initial value: 0000H P0MOD0 – – P05MD0 P04MD0 P03MD0 P02MD0 P01MD0 P00MD0 Initial value P0MOD1 – – P05MD1 P04MD1 P03MD1 P02MD1 P01MD1...
Page 359 ML620Q503/Q504 User’s Manual Chapter 17 Port 0 • P03MD1-0 (bit 11,3) The P03MD1-0 bits are used to select the primary or secondary or fourthly function of the P03 pin. P03MD1 P03MD0 Description General-purpose input/output mode / External Interrupt (initial value) Reference resistor connection pin for RC-ADC (RS0) Prohibited FTM output (TMOUT1)
Page 360: Description Of Operation
ML620Q503/Q504 User’s Manual Chapter 17 Port 0 17.3 Description of Operation 17.3.1 Input/Output Port Functions For each pin of Port 0, either output or input is selected by setting the Port 0 direction register (P0DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 0 control registers 0 and 1 (P0CON0 and P0CON1).
Page 361 Chapter 18 Port 1...
Page 362: Port1
ML620Q503/Q504 User’s Manual Chapter 18 Port 1 18 Port 1 18.1 Overview This LSI incorporates a 2-bit input port, Port 1 (P10, P11). Port 1 can have a high-speed oscillation pin or an external clock input pin. When the port is used as a high-speed oscillation pin, the P11 pin functions as an output pin if crystal/ceramic oscillation mode is selected with the OSCM1–0 bits of the FCON0 register.
Page 363: List Of Pins
ML620Q503/Q504 User’s Manual Chapter 18 Port 1 18.1.3 List of Pins Pin name Primary function Input /output port P10/OSC0 High-speed crystal/ceramic oscillation pin P11/OSC1/ Input /output port CLKIN High-speed crystal/ ceramic oscillation pin/ external clock input pin 18.2 Description of Registers 18.2.1 List of Registers Address Symbol...
Page 364: Port 1 Data Register (P1D)
ML620Q503/Q504 User’s Manual Chapter 18 Port 1 18.2.2 Port 1 Data Register (P1D) Address: 0F218H Access: R/W Access size: 8 bits Initial value: 00H – – – – – – P11D P10D Initial value P1D is a special function register (SFR) to set the value to be output to the Port 1 pin or to read the input level of the Port 1.
Page 365: Port 1 Direction Register (P1Dir)
ML620Q503/Q504 User’s Manual Chapter 18 Port 1 18.2.3 Port 1 Direction Register (P1DIR) Address: 0F219H Access: R/W Access size: 8 bits Initial value: 00H P1DIR – – – – – – P11DIR P10DIR Initial value P0DIR is a special function register (SFR) to select the input/output mode of Port 0. Description of Bits •...
Page 366 ML620Q503/Q504 User’s Manual Chapter 18 Port 1 18.2.4 Port 1 Control Register (P1CON) Address: 0F21AH Access: R/W Access size: 8/16 bits Initial value: 0000H P1CON0 – – – – – – P11C0 P10C0 Initial value P1CON1 – – – – –...
Page 367: Description Of Operation
ML620Q503/Q504 User’s Manual Chapter 18 Port 1 18.3 Description of Operation 18.3.1 Input/Output Port Function For each pin of Port 1, either output or input is selected by setting the Port 1 direction register (P1DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 1 control registers 0 and 1 (P1CON0 and P1CON1).
Page 368: Port2
Chapter 19 Port2...
Page 369: Overview
ML620Q503/Q504 User’s Manual Chapter 19 Port 2 19 Port 2 19.1 Overview This LSI includes Port 2 (P20 to P23) which is an 4-bit input/output port. This port can have external interrupts, SA-ADC, RC-ADC, SSIOF, UARTF and FTIMER output functions as secondary, tertiary and quartic functions.
Page 370 ML620Q503/Q504 User’s Manual Chapter 19 Port 2 19.1.3 List of Pins Pin name Primary function Secondary function Tertiary function Fourthly function P20/EXI20/AIN4/ Input/output port RC oscillation IN1/ SSIOF data output UARTF data input External interrupt waveform input pin SOUTF0/ SOUTF0 RXDF0 SA-ADC AIN4 for RC-ADC IN1...
Page 371: Description Of Registers
ML620Q503/Q504 User’s Manual Chapter 19 Port 2 19.2 Description of Registers 19.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F220 Port 2 data register – 0F221 Port 2 direction register P2DIR – 0F222 P2CON0 8/16 Port 2 control register P2CON 0F223...
Page 372: Port 2 Data Register (P2D)
ML620Q503/Q504 User’s Manual Chapter 19 Port 2 19.2.2 Port 2 Data Register (P2D) Address: 0F220H Access: R/W Access size: 8 bits Initial value: 00H – – – – P23D P22D P21D P20D Initial value P2D is a special function register (SFR) to set the value to be output to the Port 2 pin or to read the input level of the Port 2.
Page 373: Port 2 Direction Register (P2Dir)
ML620Q503/Q504 User’s Manual Chapter 19 Port 2 19.2.3 Port 2 Direction Register (P2DIR) Address: 0F221H Access: R/W Access size: 8 bits Initial value: 00H P2DIR – – – – P23DIR P22DIR P21DIR P20DIR Initial value P2DIR is a special function register (SFR) to select the input/output mode of Port 2. Description of Bits •...
Page 374 ML620Q503/Q504 User’s Manual Chapter 19 Port 2 19.2.4 Port 2 Control Register (P2CON) Address: 0F222H Access: R/W Access size: 8/16 bits Initial value: 0000H P2CON0 – – – – P23C0 P22C0 P21C0 P20C0 Initial value P2CON1 – – – – P23C1 P22C1 P21C1...
Page 375 ML620Q503/Q504 User’s Manual Chapter 19 Port 2 When output mode is selected When input mode is selected Setting of P23 pin (P23DIR bit = “0”) (P23DIR bit = “1”) P23C1 P23C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...
Page 376 ML620Q503/Q504 User’s Manual Chapter 19 Port 2 19.2.5 Port 2 Mode Register (P2MOD) Address: 0F224H Access: R/W Access size: 8/16 bits Initial value: 0000H P2MOD0 – – – – P23MD0 P22MD0 P21MD0 P20MD0 Initial value P2MOD1 – – – – P23MD1 P22MD1 P21MD1...
Page 377 ML620Q503/Q504 User’s Manual Chapter 19 Port 2 • P23MD1-0 (bit 11,3) The P23MD1-0 bits are used to select the primary, secondary, or tertiary function of the P23 pin. P23MD1 P23MD0 Description General-purpose input/output mode / External interrupt (initial value) Resistor sensor connection pin for measurement for RC-ADC (RT1) SSIOF enable input/output (SSF0) FTM output mode (TMOUT3)
Page 378: Description Of Operation
ML620Q503/Q504 User’s Manual Chapter 19 Port 2 19.3 Description of Operation 19.3.1 Input/Output Port Functions For each pin of Port 2, either output or input is selected by setting the Port 2 direction register (P2DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 2 control registers 0 and 1 (P2CON0 and P2CON1).
Page 379: Port 3
Chapter 20 Port 3...
Page 380: General Description
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20 Port 3 20.1 General Description This LSI includes an 8-bit input/output port, port 3 (P30 to P37). It can function as an external interrupt, a successive approximation type A/D converter input, and a comparator input, as well as an I C bus, a buzzer output, a synchronous serial port, a synchronous serial port with FIFO, a UART, a UART with FIFO, and a timer out output pin as the secondary, tertiary, or quartic function.
Page 381: Configuration
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20.1.2 Configuration Figure 20-1 shows the configuration of Port 3. Pull-up Data bus Pull-down Output for UART (TXD0) Controller Output for UART with FIFO (TXDF0) P3DIR Output for SSIO (SCK0, SOUT0) P3MOD, Output for SSIO with FIFO (SCKF0,SOUTF0) P3CON Output for I C bus (SDA0/1, SCL0/1)
Page 382: List Of Pins
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20.1.3 List of Pins Primary function Secondary Tertiary function Quartic function Pin name function P30/EXI30/CMP0P/ I/O port Synchronous UART C data I/O SDA0/ serial External interrupt data input SOUT0/ data output Comparator SDA0 RXD0 SOUT0 + side input 0...
Page 383: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20.2 Description of Registers 20.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F228 Port 3 data register – 0F229 Port 3 direction register P3DIR – 0F22A P3CON0 8/16 Port 3 control register P3CON 0F22B...
Page 384: Port 3 Data Register (P3D)
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20.2.2 Port 3 Data Register (P3D) Address: 0F228H Access: R/W Access size: 8 bits Initial value: 00H P37D P36D P35D P34D P33D P32D P31D P30D Initial value P3D is a special function register (SFR) to set the value to be output to the Port 3 pin or to read the input level of the Port 3.
Page 385 ML620Q503/Q504 User's Manual Chapter 20 Port 3 P37D Description Output or input level of the P37 pin: ”L” Output or input level of the P37 pin: ”H” FEUL620Q504 20–6...
Page 386: Port 3 Direction Register (P3Dir)
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20.2.3 Port 3 Direction Register (P3DIR) Address: 0F229H Access: R/W Access size: 8 bits Initial value: 00H P3DIR P37DIR P36DIR P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Initial value P3DIR is a special function register (SFR) to select the input/output mode of Port 3. Description of Bits •...
Page 387 ML620Q503/Q504 User's Manual Chapter 20 Port 3 [Note] The P34 to P37 pins are assigned to successive approximation type A/D converter input or comparator input. If it is used as a successive approximation type A/D converter input or comparator input, set the appropriate port to the output mode. FEUL620Q504 20–8...
Page 388: Port 3 Control Register (P3Con)
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20.2.4 Port 3 Control Register (P3CON) Address: 0F22AH Access: R/W Access size: 8/16 bit Initial value: 0000H P3CON0 P37C0 P36C0 P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Initial value P3CON1 P37C1 P36C1 P35C1 P34C1 P33C1 P32C1 P31C1...
Page 389 ML620Q503/Q504 User's Manual Chapter 20 Port 3 When output mode is selected When input mode is selected Setting of P32 pin (P32DIR bit = “0”) (P32DIR bit = “1”) P32C1 P32C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...
Page 390 ML620Q503/Q504 User's Manual Chapter 20 Port 3 When output mode is selected When input mode is selected Setting of P37 pin (P37DIR bit = “0”) (P37DIR bit = “1”) P37C1 P37C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...
Page 391: Port 3 Mode Register (P3Mod)
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20.2.5 Port 3 Mode Register (P3MOD) Address: 0F22CH Access: R/W Access size: 8/16 bit Initial value: 0000H P3MOD0 P37MD0 P36MD0 P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Initial value P3MOD1 P37MD1 P36MD1 P35MD1 P34MD1 P33MD1 P32MD1 P31MD1...
Page 392 ML620Q503/Q504 User's Manual Chapter 20 Port 3 • P32MD1-0 (bits 10,2) The P32MD1-0 bits are used to select the primary, secondary, tertiary, or quartic function of the P32 pin. P32MD1 P32MD0 Description General-purpose input/output mode, External interrupt mode (initial value) Prohibited Synchronous serial port clock input/output mode (SCK0) FTM output mode (TMOUT4)
Page 393 ML620Q503/Q504 User's Manual Chapter 20 Port 3 • P36MD1-0 (bits 14,6) The P36MD1-0 bits are used to select the primary, secondary, tertiary, or quartic function of the P36 pin. Description P36MD1 P36MD0 General-purpose input/output mode, External interrupt mode (initial value) Prohibited Synchronous serial port with FIFO clock input/output mode (SCKF0) FTM output mode (TMOUT6)
Page 394: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 20 Port 3 20.3 Description of Operation 20.3.1 Input/Output Port Functions For each pin of Port 3, either output or input is selected by setting the Port 3 direction register (P3DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 3 control registers 0 and 1 (P3CON0 and P3CON1).
Page 395: Port 4
Chapter 21 Port 4...
Page 396: General Description
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21 Port 4 21.1 General Description This LSI includes an 8-bit input/output port, port 4 (P40 to P47). It can function as an external interrupt, as well as an I C bus, a buzzer output, low/high speed clock output, a synchronous serial port, a synchronous serial port with FIFO, a UART, a UART with FIFO, and a timer out output pin as the secondary, tertiary, or quartic function.
Page 397: Configuration
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21.1.2 Configuration Figure 21-1 shows the configuration of Port 4. Pull-up Output for UART (TXD0) Data bus Pull-down Output for UART with FIFO (TXDF0) Controller Output for SSIO (SCK0, SOUT0) Output for SSIO with FIFO (SCKF0,SOUTF0) P4DIR P4MOD0,1, Output for I...
Page 398: List Of Pins
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21.1.3 List of Pins Primary function Secondary Tertiary function Quartic function Pin name function P40/EXI40/LED/ Synchronous I/O port UART SDA0/ C data I/O serial data input External interrupt SOUT0/ data output SDA0 RXD0 LED direct drive SOUT0 RXD0...
Page 399: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21.2 Description of Registers 21.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F230 Port 4 data register – 0F231 Port 4 direction register P4DIR – 0F232 P4CON0 8/16 Port 4 control register P4CON 0F233...
Page 400: Port 4 Data Register (P4D)
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21.2.2 Port 4 Data Register (P4D) Address: 0F230H Access: R/W Access size: 8 bits Initial value: 00H P47D P46D P45D P44D P43D P42D P41D P40D Initial value P4D is a special function register (SFR) to set the value to be output to the Port 4 pin or to read the input level of the Port 4.
Page 401 ML620Q503/Q504 User's Manual Chapter 21 Port 4 P47D Description Output or input level of the P47 pin: ”L” Output or input level of the P47 pin: ”H” FEUL620Q504 21-6...
Page 402: Port 4 Direction Register (P4Dir)
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21.2.3 Port 4 Direction Register (P4DIR) Address: 0F231H Access: R/W Access size: 8 bits Initial value: 00H P4DIR P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Initial value P4DIR is a special function register (SFR) to select the input/output mode of Port 4. Description of Bits •...
Page 403: Port 4 Control Register (P4Con)
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21.2.4 Port 4 Control Register (P4CON) Address: 0F232H Access: R/W Access size: 8/16 bit Initial value: 0000H P4CON0 P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Initial value P4CON1 P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1...
Page 404 ML620Q503/Q504 User's Manual Chapter 21 Port 4 When output mode is selected When input mode is selected Setting of P42 pin (P42DIR bit = “0”) (P42DIR bit = “1”) P42C1 P42C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...
Page 405 ML620Q503/Q504 User's Manual Chapter 21 Port 4 When output mode is selected When input mode is selected Setting of P47 pin (P47DIR bit = “0”) (P47DIR bit = “1”) P47C1 P47C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...
Page 406: Port 4 Mode Register (P4Mod)
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21.2.5 Port 4 Mode Register (P4MOD) Address: 0F234H Access: R/W Access size: 8/16 bit Initial value: 0000H P4MOD0 P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Initial value P4MOD1 P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1...
Page 407 ML620Q503/Q504 User's Manual Chapter 21 Port 4 • P42MD1-0 (bits 10, 2) The P42MD1-0 bits are used to select the primary, secondary, tertiary, or quartic function of the P42 pin. P42MD1 P42MD0 Description General-purpose input/output mode, External interrupt mode (initial value) Prohibited Synchronous serial port clock input/output mode (SCK0)
Page 408 ML620Q503/Q504 User's Manual Chapter 21 Port 4 • P46MD1-0 (bits 14, 6) The P46MD1-0 bits are used to select the primary, secondary, tertiary, or quartic function of the P46 pin. Description P46MD1 P46MD0 General-purpose input/output mode, External interrupt mode (initial value) Low speed clock output mode(LSCLKO) Synchronous serial port with FIFO clock input/output mode (SCKF0)
Page 409: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 21 Port 4 21.3 Description of Operation 21.3.1 Input/Output Port Functions For each pin of Port 4, either output or input is selected by setting the Port 4 direction register (P4DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 4 control registers 0 and 1 (P4CON0 and P4CON1).
Page 410 Chapter 22 Port 5...
Page 411 ML620Q503/Q504 User's Manual Chapter 22 Port 5 22 Port 5 22.1 General Description This LSI includes an 8-bit input/output port, port 5 (P50 to P57). It can function as an external interrupt, a timer clock input, as well as an I C bus, a buzzer output, a synchronous serial port, a synchronous serial port with FIFO, a UART, a UART with FIFO, and a timer out output pin as the secondary, tertiary, or quartic function.
Page 412: Port5
ML620Q503/Q504 User's Manual Chapter 22 Port 5 22.1.2 Configuration Figure 22-1 shows the configuration of Port 5. Output for UART (TXD0) Pull-up Data bus Output for UART with FIFO (TXDF0) Pull-down Output for SSIO (SCK0, SOUT0) Controller Output for SSIO with FIFO P5DIR (SCKF0,SOUTF0) P5MOD...
Page 413: List Of Pins
ML620Q503/Q504 User's Manual Chapter 22 Port 5 22.1.3 List of Pins Primary Secondary Tertiary Quartic Pin name function function function function P50/EXI50/ Synchronous UART SDA0/ I/O port C data I/O serial data input data output SOUT0/ External interrupt SDA0 RXD0 SOUT0 RXD0 P51/EXI51/...
Page 414: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 22 Port 5 22.2 Description of Registers 22.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F238 Port 5 data register – 0F239 Port 5 direction register P5DIR – 0F23A P5CON0 8/16 Port 5 control register P5CON 0F23B...
Page 415: Port 5 Data Register (P5D)
ML620Q503/Q504 User's Manual Chapter 22 Port 5 22.2.2 Port 5 Data Register (P5D) Address: 0F238H Access: R/W Access size: 8 bits Initial value: 00H P57D P56D P55D P54D P53D P52D P51D P50D Initial value P5D is a special function register (SFR) to set the value to be output to the Port 5 pin or to read the input level of the Port 5.
Page 416 ML620Q503/Q504 User's Manual Chapter 22 Port 5 P57D Description Output or input level of the P57 pin: ”L” Output or input level of the P57 pin: ”H” FEUL620Q504 22-6...
Page 417: Port 5 Direction Register (P5Dir)
ML620Q503/Q504 User's Manual Chapter 22 Port 5 22.2.3 Port 5 Direction Register (P5DIR) Address: 0F239H Access: R/W Access size: 8 bits Initial value: 00H P5DIR P57DIR P56DIR P55DIR P54DIR P53DIR P52DIR P51DIR P50DIR Initial value P5DIR is a special function register (SFR) to select the input/output mode of Port 5. Description of Bits •...
Page 418 ML620Q503/Q504 User's Manual Chapter 22 Port 5 [Note] The P50 to P57 pins are assigned to successive approximation type A/D converter input. If it is used as a successive approximation type A/D converter input, set the appropriate port to the output mode.
Page 419: Port 5 Control Register (P5Con)
ML620Q503/Q504 User's Manual Chapter 22 Port 5 22.2.4 Port 5 Control Register (P5CON) Address: 0F23AH Access: R/W Access size: 8/16 bit Initial value: 0000H P5CON0 P57C0 P56C0 P55C0 P54C0 P53C0 P52C0 P51C0 P50C0 Initial value P5CON1 P57C1 P56C1 P55C1 P54C1 P53C1 P52C1 P51C1...
Page 420 ML620Q503/Q504 User's Manual Chapter 22 Port 5 When output mode is selected When input mode is selected Setting of P52 pin (P52DIR bit = “0”) (P52DIR bit = “1”) P52C1 P52C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...
Page 421 ML620Q503/Q504 User's Manual Chapter 22 Port 5 When output mode is selected When input mode is selected Setting of P57 pin (P57DIR bit = “0”) (P57DIR bit = “1”) P57C1 P57C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...
Page 422: Port 5 Mode Register (P5Mod)
ML620Q503/Q504 User's Manual Chapter 22 Port 5 22.2.5 Port 5 Mode Register (P5MOD) Address: 0F23CH Access: R/W Access size: 8/16 bit Initial value: 0000H P5MOD0 P57MD0 P56MD0 P55MD0 P54MD0 P53MD0 P52MD0 P51MD0 P50MD0 Initial value P5MOD1 P57MD1 P56MD1 P55MD1 P54MD1 P53MD1 P52MD1 P51MD1...
Page 423 ML620Q503/Q504 User's Manual Chapter 22 Port 5 • P52MD1-0 (bits 10, 2) The P52MD1-0 bits are used to select the primary, secondary, tertiary, or quartic function of the P52 pin. P52MD1 P52MD0 Description General-purpose input/output mode, External interrupt mode (initial value) Prohibited Synchronous serial port clock input/output mode (SCK0)
Page 424 ML620Q503/Q504 User's Manual Chapter 22 Port 5 • P56MD1-0 (bits 14, 6) The P56MD1-0 bits are used to select the primary, secondary, tertiary, or quartic function of the P56 pin. Description P56MD1 P56MD0 General-purpose input/output mode, External interrupt mode (initial value) Low speed clock output mode(LSCLKO) Synchronous serial port with FIFO clock input/output mode (SCKF0)
Page 425: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 22 Port 5 22.3 Description of Operation 22.3.1 Input/Output Port Functions For each pin of Port 5, either output or input is selected by setting the Port 5 direction register (P5DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 5 control registers 0 and 1 (P5CON0 and P5CON1).
Page 426: Melody Driver
Chapter 23 Melody Driver...
Page 427: Overview
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23 Melody Driver 23.1 Overview This LSI includes one channel of the melody driver. To use the melody driver, the secondary function of Port 3 or Port 4 or Port 5 should be set. For the respective port setting, see Chapter 20, "Port 3", Chapter 21, "Port 4"...
Page 428: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.2 Description of Registers 23.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F8C0 Melody 0 control register MD0CON – 0F8C1 Melody 0 tempo code register MD0TMP – 0F8C2 Melody 0 scale/tone length code MD0TON 8/16...
Page 429: Melody 0 Control Register (Md0Con)
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.2.2 Melody 0 Control Register (MD0CON) Address: 0F8C0H Access: R/W Access size: 8 bit Initial value: 00H MD0CON – – – – – – BZMD M0RUN Initial value MD0CON is a special function register (SFR) to control the melody and the buzzer. Description of Bits •...
Page 430: Melody 0 Tempo Code Register (Md0Tmp)
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.2.3 Melody 0 Tempo Code Register (MD0TMP) Address: 0F8C1H Access: R/W Access size: 8 bit Initial value: 00H MD0TMP – – – – M0TM3 M0TM2 M0TM1 M0TM0 Initial value MD0TMP is a special function register (SFR) to set the tempo code of a melody in the melody mode, or a buzzer output waveform type in the buzzer mode.
Page 431: Melody 0 Scale/Tone Length Code Register (Md0Tl)
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.2.4 Melody 0 Scale/Tone Length Code Register (MD0TL) Address: 0F8C2H Access: R/W Access size: 8/16 bit Initial value: 0000H MD0TON – M0TN6 M0TN5 M0TN4 M0TN3 M0TN2 M0TN1 M0TN0 Initial value MD0LEN – – M0LN5 M0LN4 M0LN3...
Page 432 ML620Q503/Q504 User's Manual Chapter 23 Melody Driver • M0LN5-0 (bits 13 to 8) When melody mode is selected (BZMD bit = “0”) Description M0LN5 to M0LN0 Sets the corresponding tone length code. For tone length codes, see Section 23.3.3, "Tone Length Codes". When buzzer mode is selected (BZMD bit = “1”) M0LN5 to M0LN3...
Page 433: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.3 Description of Operation 23.3.1 Operation of Melody Output Melody is output in the following procedure. (1) Select melody mode by setting the BZMD bit of the melody 0 control register (MD0CON) to “0”. (2) Set a melody tempo in the melody 0 tempo code register (MD0TMP).
Page 434: Example Of Using Melody Circuit
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.3.2 Example of Using Melody Circuit Figure 23-3 shows an example of a melody notation, and Table 23-1 shows note codes of melody examples. ＝120 ４４ Figure 23-3 Example of Melody Notation Table 23-1 Note Codes of Melody Examples Note code Note...
Page 435: Tempo Codes
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.3.3 Tempo Codes A tempo code is set in the melody 0 tempo code register (MD0TMP). Table 23-2 shows the correspondence between tempos (number of counts for one minute) and tempo codes. The tempo when all the bits are set to "0" is equal to the shortest tone length (the tempo when the only M0TP0 bit is set to "1").
Page 436 ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.3.4 Tone Length Codes A tone length code is set in the melody 0 tone length code register (MD0LEN). Table 23-3 shows the correspondence between tone lengths and tone length codes. The tone length when all the bits are set to "0" is equal to the shortest tone length (the tone length when the only M0LN0 bit is set to "1").
Page 437: Scale Codes
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.3.5 Scale Codes A scale code is set in the melody 0 scale code register (MD0TON). In the melody driver, a frequency that can be output is expressed by the following equation. 65536 Hz (where TN is an integer of 4 to 127.) ( TN + 1 ) The bit correspondence between TN and scale codes is expressed by the following equation.
Page 438: Operations Of Buzzer Output
ML620Q503/Q504 User's Manual Chapter 23 Melody Driver 23.3.6 Operations of Buzzer Output A buzzer sound is output in the following procedure. (1) Select a buzzer mode by setting the BZMD bit of the melody 0 control register (MD0CON) to “1”. (2) Select a buzzer output mode using the melody 0 tempo code register (MD0TMP).
Page 439: Rc Oscillation Type A/Dconverter (Rc-Adc)
Chapter 24 RC Oscillation type A/D Converter (RC-ADC)
Page 440: General Description
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24 RC Oscillation Type A/D Converter (RC-ADC) 24.1 General Description The RC oscillation type A-D Converter (RC-ADC) converts resistance values or capacitance values to digital values by counting the oscillator clock whose frequency changes according to the resistor or capacitor connected to the RC oscillator circuits.
Page 441: List Of Pins
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.1.3 List of Pins Pin name Function Channel 0 oscillation input pin Channel 0 reference capacitor connection pin Channel 0 reference resistor connection pin Pin for connection with a resistive/capacitive sensor for RCT0 measurement on Channel 0 Pin for connection with a resistive sensor for measurement on...
Page 442: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.2 Description of Registers 24.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F800 RADCA0L 8/16 RC-ADC counter A register 0 RADCA0 0F801 RADCA0H 0F802 RADCA1L 8/16 RC-ADC counter A register 1 RADCA1...
Page 443 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.2 RC-ADC Counter A Register 0 (RADCA0) Address: 0F800H Access: R/W Access size: 8/16 bits Initial value: 0000H RADCA0L RAA7 RAA6 RAA5 RAA4 RAA3 RAA2 RAA1 RAA0 Initial value RADCA0H RAA15 RAA14 RAA13...
Page 444 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.4 RC-ADC Counter B Register 0 (RADCB0) Address: 0F804H Access: R/W Access size: 8/16 bits Initial value: 0000H RADCB0L RAB7 RAB6 RAB5 RAB4 RAB3 RAB2 RAB1 RAB0 Initial value RADCB0H RAB15 RAB14 RAB13...
Page 445: Rc-Adc Mode Register (Radmod)
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.6 RC-ADC Mode Register (RADMOD) Address: 0F808H Access: R/W Access size: 8/16 bits Initial value: 0000H RADMODL RACK2 RACK1 RACK0 RADI Initial value RADMODH – – – – – – –...
Page 446 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter • RACK2-0 (bits 7 to 5) The RACK2-0 bits are used to select the base clock of Counter A (BSCLK). RACK2 RACK1 RACK0 Description LSCLK (initial value) OSCLK 1/2OSCLK 1/4OSCLK 1/8OSCLK 1/16OSCLK 1/32OSCLK...
Page 447: Rc-Adc Control Register (Radcon)
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.7 RC-ADC Control Register (RADCON) Address: 0F80AH Access: R/W Access size: 8/16 bits Initial value: 0000H RADCONL – – – – – – – RARUN Initial value RADCONH – – –...
Page 448: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.3 Description of Operation Counter A (RADCA0 and RADCA1) is a 24-bit binary counter for counting the base clock (BSCLK), which is used as the standard of time. Counter A can count up to 0FFFFFFH. Counter B (RADCB0 and RADCB1) is a 24-bit binary counter for counting the oscillator clock (RCCLK) of the RC oscillator circuits.
Page 449: Rc Oscillator Circuits
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.3.1 RC Oscillator Circuits RC-ADC performs A/D conversion by converting the oscillation frequency ratio between a reference resistor (or capacitor) and a resistive sensor (or capacitive sensor) such as a thermistor to digital data. By making RC oscillation occur both on the reference side and on the sensor side with the reference capacitor the error factor that the RS oscillator circuit itself is eliminated, thereby making it possible to perform the A/D conversion of the characteristics of the sensor itself.
Page 450 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter Table 24-2 Typical Values of the Proportional Constant k of RC Oscillator Circuits RCCLK VDD (V) CSn, CTn (pF) CVRn (pF) RSn, RTn (kΩ) (Typ.) RCCLK Note) n = 0, 1, 0-1 [Note] •Pins that are to be used for the RC-ADC function must be configured as secondary function input or output using the mode register (P0MOD0, P0MOD1, P2MOD0, P2MOD1) of the corresponding port.
Page 451 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter Figures 24-2 to 24-5 show the oscillator circuit configurations, the modes of oscillation for each configuration, and the OM3–0 bit settings. RCT0 oscillation mode Oscillates with the reference resistor RS0 and CS0 Oscillates with the sensor RT0 and CS0 Figure 24-2 When RCOSC0 Is Used for Measurement with One Resistive Sensor...
Page 452 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter oscillation mode Oscillates with the reference resistor RS1 and CS1 Oscillates with the sensor RT1 and CS1 Figure 24-5 When RCOSC1 Is Used for Measurement with One Resistive Sensor FEUL620Q504 24-13...
Page 453: Counter A/B Reference Modes
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.3.2 Counter A/B Reference Modes There are the following two modes of RC-ADC conversion operation: • Counter A reference mode (RADMOD RADI = “0”) In this mode, a gate time is determined by Counter A and the base clock (BSCLK), which is used as the time reference, then the RC oscillator clock (RCCLK) is counted by Counter B within the gate time to make the content of Counter B the A/D conversion value.
Page 454 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter   RARUN BSCLK BSCLK RCON  Overflow Counter A (100000H-nA0) (+1) (+2) (+3) 0000000H 0FFFFFCH 0FFFFFDH 0FFFFFEH 0FFFFFFH Gate time nA0 • t BSCLK CR oscillator circuit RCCLK Input waveform IN0/IN1 RCCLK ...
Page 455 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter When the RCON signal is set to “1”, Counter A starts counting of the base clock (BSCLK). When the RARUN bit is reset due to overflow of Counter B, Counter A stops counting. The final count value “nA1”...
Page 456: Example Of Use Of Rc Oscillation Type A/D Converter
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.3.3 Example of Use of RC Oscillation Type A/D Converter This section describes the method of performing A/D conversion for sensor values in Counter A and B reference modes by taking temperature measurement by a thermistor as an example. Figure 24-8 shows the configuration of 1-thermistor RC oscillator circuit using RCOSC0.
Page 457 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter To convert from an RT0 value to a digital value, the ratio is used between a) the RC oscillation frequency by the thermistor connected to the RT0 pin and the capacitor connected to the CS0 pin and b) the oscillation frequency by the reference resistor (which ideally should have no temperature characteristics) connected to the RS0 pin and the capacitor connected to the CS0 pin.
Page 458 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter Figure 24-14 shows, as an example of method, a timing diagram of one cycle of conversion from analog value RT0 to a digital value, that is, A/D conversion. Basically, one A/D conversion cycle must consist of two steps, as shown in Figure 24-14. The reason for requiring two steps is that the reference resistor and the thermistor must first be oscillated separately and then the ratio between the oscillation frequencies of them is used, as described above.
Page 459 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter Figure 24-14 Timing Diagram for 1 Cycle of A/D Conversion (Example) <First step>  Set the base clock to LSCLK (32.768kHz). (Write “00H” in FCON0.) Preset “1000000H – nA0” in Counter A. Preset “000000H”...
Page 460 ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter The content of Counter A at this time becomes the A/D conversion value nA1, which is expressed by the following expression: (RT0) RCCLK nB0• ... Expression C BSCLK From expressions B and C, nA1 is expressed by the following expression: (RT0) RCCLK nA0•...
Page 461: Monitoring Rc Oscillation
ML620Q503/Q504 User's Manual Chapter 24 RC Oscillation Type A/D Converter 24.3.4 Monitoring RC Oscillation The RC oscillator clock (RCCLK) can be output using the secondary function of the P05. See Chapter 17, “Port 0,” for the details of the secondary function of P05. Monitoring RC oscillation is useful for checking the characteristics of the RC oscillator circuit.
Page 462 Chapter 25 Successive Approximation Type A/D Converter (SA-ADC)
Page 463: Successive Approximation Type A/Dconverter (Sa-Adc)
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25 Successive Approximation Type A/D Converter (SA-ADC) 25.1 General Description The successive approximation type A-D converter (SA-ADC) has 12 channels with a built-in function supporting an electrostatic capacity type switch (touch sensor supported) in addition to the normal A/D conversion. 25.1.1 Features •...
Page 464 ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.1.3 List of Pins Pin name Function Successive approximation type A/D converter input pin 0 P34/AIN0 Use as P34 pin primary function Successive approximation type A/D converter input pin 1 P35/AIN1 Use as P35 pin primary function Successive approximation type A/D converter input pin 2...
Page 465: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.2 Description of Registers 25.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F820 SADR0L 8/16 SA-ADC result register 0 SADR0 0F821 SADR0H 0F822 SADR1L 8/16 SA-ADC result register 1 SADR1 0F823...
Page 466: Sa-Adc Result Register N (Sadrn) N=0 To 9, A, B
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.2 SA-ADC Result Register n (SADRn) n=0 to 9, A, B Address: 0F820H(SADR0L/SADR0), 0F821H(SADR0H), 0F822H(SADR1L/SADR1), 0F823H(SADR1H), 0F824H(SADR2L/SADR2), 0F825H(SADR2H), 0F826H(SADR3L/SADR3), 0F827H(SADR3H), 0F828H(SADR4L/SADR4), 0F829H(SADR4H), 0F82AH(SADR5L/SADR5), 0F82BH(SADR5H), 0F82CH(SADR6L/SADR6), 0F82DH(SADR6H), 0F82EH(SADR7L/SADR7), 0F82FH(SADR7H), 0F830H(SADR8L/SADR8), 0F831H(SADR8H), 0F832H(SADR9L/SADR9), 0F833H(SADR9H), 0F834H(SADRAL/SADRA), 0F835H(SADRAH), 0F836H (SADRBL/SADRB), 0F837H (SADRBH) Access: R Access size: 8/16 bits...
Page 467: Sa-Adc Control Register 0(Sadcon0)
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.3 SA-ADC Control Register 0(SADCON0) Address: 0F840H Access: R/W Access size: 8 bits Initial value: 22H SADCON0 – – SACD1 SACD0 – SATCM SACK SALP Initial value SADCON0 is a special function register (SFR) used to control the operation of the SA-ADC. Description of Bits •...
Page 468 ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter • SACD1-0 (bits 5 to 4) The SACD1-0 bits are used to set the counter frequency dividing of the SA-ADC conversion time. This setting is the dividing value of the clock selected by the SACK bit. The clock to be input to the SA-ADC should be 4MHz or less when OSCLK is selected, or 32.768kHz or less when LSCLK is selected.
Page 469: Sa-Adc Control Register1 (Sadcon1)
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.4 SA-ADC Control Register1 (SADCON1) Address: 0F841H Access: R/W Access size: 8 bits Initial value: 00H SADCON1 – – – – – – – SARUN Initial value SADCON is a special function register (SFR) used to control the operation of the SA-ADC. Description of Bits •...
Page 470: Sa-Adc Enable Register (Saden)
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.5 SA-ADC Enable Register (SADEN) Address: 0F842H Access: R/W Access size: 8/16 bits Initial value: 0000H SADENL SACH7 SACH6 SACH5 SACH4 SACH3 SACH2 SACH1 SACH0 Initial value SADENH – – –...
Page 471: Sa-Adc Touch Sensor Register (Sadtch)
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.6 SA-ADC Touch Sensor Register (SADTCH) Address: 0F844H Access: R/W Access size: 8/16 bits Initial value: 0000H SADTCHL SATCH7 SATCH6 SATCH5 SATCH4 SATCH3 SATCH2 SATCH1 SATCH0 Initial value SADTCHH – –...
Page 472: Sa-Adc Trigger Register (Sadtrg)
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.7 SA-ADC Trigger Register (SADTRG) Address: 0F846H Access: R/W Access size: 8/16 bits Initial value: 0000H SADTRGL – – – – – – – SAST0 Initial value SADTRGH – – –...
Page 473 ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter • SASTS4-0 (bits 12 to 8) This bit is used to select a trigger event for the A/D conversion. SASTS4 SASTS3 SASTS2 SASTS1 SASTS0 Description TM0INT TM1INT TM2INT TM3INT TM4INT TM5INT TM6INT TM7INT...
Page 474 ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.8 SA-ADC Accuracy Control Register (SADCVT) Address: 0F848H Access: R/W Access size: 8/16 bits Initial value: FFFFH SADCVTL SADCT7 SADCT6 SADCT5 SADCT4 SADCT3 SADCT2 SADCT1 SADCT0 Initial value SADCVTH SAPCT4 SAPCT3 SAPCT2 SAPCT1...
Page 475: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.3 Description of Operation 25.3.1 Setting of A/D Conversion Channels According to the table 25-2, set a bit corresponding to each channel on which the A/D conversion is performed. table 25-2, Setting channel SADCON0 SADEN SADTCH...
Page 476: Operation Of The Successive Approximation Type A/D Converter
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.3.2 Operation of the Successive Approximation Type A/D Converter For direct input, operate SA-ADC in the following procedure. (1) Normal mode Wait until the oscillation of the clock used for the A/D conversion is started and stabilized. When LSCLK is selected, it is revealed that the oscillation is stabilized by the fact that T128HZ of the low-speed time base counter register (LTBR) is set to “1”.
Page 477: Capacitive Touch Sensor Mode Operation
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter SACLK SARUN A/D operation Conversion time Conversion time signal 42.5μs@SACLK=4MHz 42.5μs@ SACLK=4MHz 488us@32.768kHz 488us@32.768kHz Channel 0 A/D conversion Channel 1 A/D conversion SADINT Figure 25-3 Operation Timing Diagram of SA-ADC 25.3.3 Capacitive Touch sensor mode operation To operate SA-ADC, complete the following procedure.
Page 478: Notes On Use Of Sa-Adc
ML620Q503/Q504 User's Manual Chapter 25 Successive Approximation Type A/D Converter 25.3.4 Notes on Use of SA-ADC SA-ADC has an internal capacitor of 51.2pF(Typ), which is charged by the voltage input from AINn (n=0 to 11). It is possible to charge it by connecting an external capacitor of 0.47uF or more regardless of the input impedance.
Page 479 Chapter 26 Analog Comparator...
Page 480: Overview
ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator 26 Analog Comparator 26.1 Overview An analog comparator compares 2 input voltage and generate an interrupt corresponding to the comparison result. This LSI has two channel analog comparator, can compare the voltages (differential input) supplied to two input pins (CMPnP and CMPnM, n=0, 1).
Page 481: Description Of Registers
ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator 26.2 Description of Registers 26.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) – 0F920 Comparator 0 control register CMP0CON 8/16 0F922 CMP0MODL Comparator 0 mode register CMP0MOD 0F923 CMP0MODH –...
Page 482: Comparator N Control Register (Cmpncon : N=0,1)
ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator 26.2.2 Comparator n Control Register (CMPnCON : n=0,1) Address: 0F920H(CMP0CON), 0F928H(CMP1CON) Access: R/W Access size: 8 bits Initial value: 00H CMPnCON – – – – – CMPnRF CMPnD CMPnEN Initial value CMPnCON is a special function register (SFR) to control the Comparator. Description of Bits •...
Page 483: Comparator N Mode Registers (Cmpnmod : N=0,1)
ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator 26.2.3 Comparator n mode Registers (CMPnMOD : n=0,1) Address: 0F922H(CMP0MODL/CMP0MOD), 0F923H(CMP0MODH), 0F92AH(CMP1MODL/CMP1MOD), 0F92BH(CMP1MODH) Access: R/W Access size: 8/16 bits Initial value: 0000H CMPnMODL – – CMPnMD1 CMPnMD0 – – CMPnE1 CMPnE0 Initial value CMPnMODH –...
Page 484 ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator • CMPnMD1-0 (bit 5 to 4) Set function mode. CMPnMD1 CMPnMD0 Description Single mode After CMPnEN is set and complete the compare, if the interrupt condition is match, generate interrupt and stop automatically. Single monitor mode After CMPnEN is set and complete the compare, generate interrupt and stop automatically.
Page 485: Function Description
ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator 26.3 Function description 26.3.1 Comparator function The Comparator has following 3 modes. Supervisor mode : Suitable for voltage monitor always. Single mode : Suitable for voltage monitor regularly. Generate interrupts par specified. Single monitor mode : Suitable for voltage monitor regularly.
Page 486: Single Mode
ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator The timing chart is as follows. System clock CMPnCLK Sampling clock CMPnEN CMPnOUT  without sampling Trdy CMPnD CMPnRF CMPnIN  with smapling Trdy CMPnD CMPnRF CMPnIN Figure 26-2 Timing in the supervisor mode Time before CMPnD setting becoming valid is depending on operation/sampling clock setting.
Page 487 ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator The timing chart is as follows System clock CMPnCLK Sampling clock CMPnEN CMPnOUT Trdy Tend without sampling CMPnEN CMPnD CMPnRF CMPnINT with sampling Trdy Tend CMPnEN CMPnD CMPnRF CMPnINT Figure 26-3 Timing in the single mode Time before CMPnD setting becoming valid is depending on operation/sampling clock setting.
Page 488: Singlemonitor Mode
ML620Q503/Q504 User’s Manual Chapter 26 Analog Comparator 26.3.4 Single monitor mode This mode activate comparator as specified and generate interrupt after measurment, and deactivate comparator automatically by hardware. Setting instruction: (1)Set operation clock, filtering, and single monitor mode by CMPnMOD register. Interrupt stting is invalid.
Page 489: Flash Memory Control
Chapter 27 Flash Memory Control...
Page 490: General Description
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27 Flash Memory Control 27.1 General Description The flash memory rewriting function includes rewriting function of the data flash using special function registers (SFRs), ISP (In System Programming) function used to rewrite the program memory by software, and remap function of the boot area.
Page 491: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.2 Description of Registers 27.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Word) (Byte) 0F0E0 FLASHAL 8/16 Flash address register FLASHA 0F0E1 FLASHAH 0F0E2 FLASHDL 8/16 Flash data register FLASHD 0F0E3 FLASHDH...
Page 492 ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.2.2 Flash Address Register (FLASHA) Address: 0F0E0H Access: R/W Access size: 8/16 bit Initial value: 0000H FLASHAL Initial value FLASHAH FA15 FA14 FA13 FA12 FA11 FA10 Initial value FLASHA is a special function register (SFR) used to set the flash memory rewrite addresses. Description of Bits •...
Page 493: Flash Data Register (Flashd)
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.2.3 Flash Data Register (FLASHD) Address: 0F0E2H Access: R/W Access size: 8/16 bit Initial value: 0000H FLASHDL Initial value FLASHDH FD15 FD14 FD13 FD12 FD11 FD10 Initial value FLASHD is a special function register (SFR) used to set the flash memory rewrite data. Description of Bits •...
Page 494: Flash Control Register (Flashcon)
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.2.4 Flash Control Register (FLASHCON) Address: 0F0E4H Access: W Access size: 8 bits Initial value: 00H FLASHCON – – – – – – FSERS FERS Initial value FLASHCON is a write-only special function register (SFR) to control the block erase and sector erase for the flash memory rewrite.
Page 495: Flash Acceptor (Flashacp)
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.2.5 Flash Acceptor (FLASHACP) Address: 0F0E6H Access: W Access size: 8 bits Initial value: 00H FLASHACP fac7 fac6 fac5 fac4 fac3 fac2 fac1 fac0 Initial value FLASHACP is a write-only special function register (SFR) to control the block erase for the flash memory rewrite or sector erase or enable/disable the 1-word write operation.
Page 496: Flash Self Register (Flashslf)
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.2.7 Flash Self Register (FLASHSLF) Address: 0F0EAH Access: R/W Access size: 8 bits Initial value: 00H FLASHSLF – – – – – – – FSELF Initial value FLASHSLF is a special function register (SFR) used to control the flash memory self-rewrite function. Description of Bits •...
Page 497: Remap Address Register (Remapadd)
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.2.8 Remap Address Register (REMAPADD) Address: 0F0ECH Access: R/W Access size: 8 bits Initial value: 00H REMAPADD RBTA RES2 RES1 RES0 REA15 REA14 REA13 REA12 Initial value REMAPADD is a special function register (SFR) used to specify the remap area. In REMAPADD, the following two types of remapping can be specified.
Page 498: Description Of Operation
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.3 Description of Operation The following functions are executable by the flash memory control registers. 1) Data flash rewriting 2) Program code rewriting When rewriting program code If use of the self-rewrite function, it is necessary to prepare for the program in advance for self-rewrite on a program code area except the addresses targeted for block/sector erase or 1-word write.
Page 499: Address Setting For Erase
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.3.1 Address Setting for Erase Table 27-1 Address Setting Values for Block Erase Area for block erase FLASHSEG FLASHAH Segment Address 0:0000H 0:1FFFH 0:2000H 0:3FFFH 0:4000H 0:5FFFH Segment 0 0:6000H 0:7FFFH 0:8000H 0:9FFFH 0:A000H 0:BFFFH...
Page 500: Data Flash Rewriting
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.3.2 Data Flash Rewriting The LSI is equipped with a data flash of 2 KB (2 sectors: 1 KB/sector). The rewrite count is 10,000. Figure 27-1 shows the sequence of 1-word write/sector erase/block erase. Writing is performed sequentially from the first sector.
Page 501: Boot Area Remap Function By Software
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.3.4 Boot Area Remap Function by Software This function can remap the area from 0000H to 0FFFH (4 KB) to the area of the same size (4 KB) starting from the address set in the REMAPADD register. The program can start from the remapped area by setting the start address of the area to remap in the REMAPADD register and performing the software reset (* only CPU is reset) by execution of the BRK instruction.
Page 502: Boot Area Remap Function By Hardware
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.3.5 Boot Area Remap Function by Hardware When the power-on reset by power-on or the reset by the RESET_N pin is released under the condition that the external pin (TEST0) is set to High, 512 bytes of ISP boot area and 512 bytes of test area (1 KB in total) are remapped to 0:0000H to 0:03FFH to allow the boot by the program in the ISP boot area.
Page 503: Notes Of The Program After Remapping
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control [Note] Write the boot program in the addresses from FC00H to FDDFH of the ISP boot area (addresses FC00H to FDFFH) in advance by using the on-chip ICE function. Please be sure to write “0FFH” in FDE0-FDFFH. Do not set TEST0 pin to “0”...
Page 504: Sample Program
ML620Q503/Q504 User's Manual Chapter 27 Flash Memory Control 27.3.7 Sample Program This section lists sample programs for block erase/sector erase/1-word write (assuming that the flash segment register is already set). (1) Block erase/sector erase ; EA←FLASHAH address offset FLASHAH #0FAH ;...
Page 505: Voltage Level Supervisor
Chapter 28 Voltage Level Supervisor (VLS)
Page 506: General Description
ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor 28 Voltage Level Supervisor (VLS) 28.1 General Description This LSI has one channel of built-in Voltage Level Supervisor (VLS). This function can be used to judge whether the voltage level of V is lower than the specified threshold voltage.
Page 507: Description Of Registers
ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor 28.2 Description of Registers 28.2.1 List of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F900 VLSCONL 8/16 Voltage level supervisor control VLSCON register 0F901 VLSCONH 0F902 VLSMODL 8/16 Voltage level supervisor mode VLSMOD register 0F903...
Page 508: Voltage Level Supervisor Control Register (Vlscon)
ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor 28.2.2 Voltage level supervisor control register (VLSCON) Address: 0F900H Access: R/W Access size: 8/16 bit Initial value: 0000H VLSCONL – – – – VLSLV3 VLSLV2 VLSLV1 VLSLV0 Initial value* VLSCONH – – –...
Page 509 ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor • ENVLS (bit 8) The ENVLS bit is used to control ON/OFF of the VLS. VLS is turned on when ENVLS is set to "1", and off when “0”. When the VLS reset is issued, the VLS keep the ON state. ENVLS Description VLS: OFF (initial value)
Page 510: Voltage Level Supervisor Mode Register (Vlsmod)
ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor 28.2.3 Voltage level supervisor mode register (VLSMOD) Address: 0F902H Access: R/W Access size: 8/16 bit Initial value: 0000H VLSMODL – – – – – – VLSSEL1 VLSSEL0 Initial value* VLSMODH – – –...
Page 511: Supervisor Mode
ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor • VLSAMD1-0 (bits 10 to 9) The VLSAMD1-0 bits are used to set the VLS running mode. VLSAMD1 VLSAMD0 Description Use prohibit (initial value) Use prohibit Supervisor mode Supervisor mode [Note] VLSAMD1 - 0 bits set to ”2” or ”3”h, before setting ENVLS bit to “1”.Operation is not guaranteed in the case of the other setting.
Page 512 ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor 28.3 Description of Operation The VLS can judge whether V on the CPU is lower or higher than the specified threshold voltage by reading SFR, and also it can issue a VLS interrupt or VLS reset when V becomes lower than the specified threshold voltage.
Page 513 ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor 28.3.1 Supervisor mode When setting ENVLS with VLSAMD1-0 set to ”10” or ”11”, the supervisor mode is activated. The supervisor mode is useful for using the low voltage detection interrupt/reset with always-ON. The detection flag(VLSF)/reset is masked until the ready flag is asserted.
Page 514 ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor Figure 28-3 shows an example of the operation timing diagram when detecting with sampling and setting the VLS reset issue. ⑤ ⑦ ② ③ ④ ⑥ ① ↓ ↓ ↓ ↓ ↓ ↓...
Page 515 ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor Figure 28-4 shows an example of the operation timing diagram when detecting without sampling and setting the VLS interrupt issue. ① ② ③ ④ ⑤ ↓ ↓ ↓ ↓ ↓ ENVLS Ready flag: VLSRF Threshold voltage (rise) VLS+...
Page 516 ML620Q503/Q504 User's Manual Chapter 28 Voltage Level Supervisor Figure 28-5 shows an example of the operation timing diagram when detecting with sampling and setting the VLS interrupt issue. ⑦ ⑤ ⑥ ① ② ③ ④ ↓ ↓ ↓ ↓ ↓ ↓...
Page 517 Chapter 29 LLD circuit...
Page 518: General Description
ML620Q503/Q504 User’s Manual Chapter 29 LDD circuit 29 LLD circuit 29.1 General Description LLD circuit monitors Power supply Voltage level. When Power supply Voltage falls than the thresholdvoltage, LLD reset this LSI. 29.1.1 Features • Judgement Voltage：1.8V±0.2V • generate LSI reset •...
Page 519: On-Chip Debug Function
Chapter 30 On-Chip Debug Function...
Page 520: Overview
ML620Q503/Q504 user’s manual Chapter 30 On-Chip Debug Function 30 On –Chip Debug Function 30.1 Overview This LSI has an on-chip debug function allowing Flash memory rewriting. The on-chip debug emulator (uEASE) is connected to this LSI to perform the on-chip debug function. nanoEASE can be connected to this LSI.
Page 521: Flash Memory Rewrite Function
ML620Q503/Q504 user’s manual Chapter 30 On-Chip Debug Function 30.3 Flash Memory Rewrite Function Flash memory erase/write can be performed with the the memory mounted on board by using the commands from the on-chip debug emulator (uEASE). For more details on the on-chip debug emulator, see “uEASE User’s Manual”.
Page 522: Appendixes
Appendixes...
Page 523: Appendix A Registers
ML620Q503/Q504 User’s Manual Appendix A Registers Appendix A Registers Contents of Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) – 0F000 Data segment register 0F002 FCON0 8/16 Frequency control register 01 FCON01 0F003 FCON1 0F004 FCON2 8/16 Frequency control register 23 FCON23 0F005 FCON3...
Page 524 ML620Q503/Q504 User’s Manual Appendix A Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F02E ILC6L 8/16 Interrupt lever control register 6 ILC6 0F02F ILC6H 0F030 ILC7L 8/16 Interrupt lever control register 7 ILC7 0F031 ILC7H 0F040 EXICON0 8/16 External interrupt control register 01 EXICON01 0F041...
Page 525 ML620Q503/Q504 User’s Manual Appendix A Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) – 0F219 Port 1 direction register P1DIR 0F21A P1CON0 8/16 Port 1 control register P1CON 0F21B P1CON1 – 0F220 Port 2 data register – 0F221 Port 2 direction register P2DIR 0F222...
Page 526 ML620Q503/Q504 User’s Manual Appendix A Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F322 TM2CON 8/16 Timer 23 control register TM23CON 0F323 TM3CON 0F324 TM4CON 8/16 Timer 45 control register TM45CON 0F325 TM5CON 0F326 TM6CON 8/16 Timer 67 control register TM67CON 0F327 TM7CON...
Page 527 ML620Q503/Q504 User’s Manual Appendix A Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F438 FT1INTEL 8/16 FTM1 interrupt enable register FT1INTE 0F439 FT1INTEH 0F43A FT1INTSL 8/16 FTM1 interrupt status register FT1INTS 0F43B FT1INTSH 0F43C FT1INTCL 8/16 FTM1 interrupt clear register FT1INTC 0F43D FT1INTCH...
Page 528 ML620Q503/Q504 User’s Manual Appendix A Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F47A FT3INTSL 8/16 FTM3 interrupt status register FT3INTS 0F47B FT3INTSH 0F47C FT3INTCL 8/16 FTM3 interrupt clear register FT3INTC 0F47D FT3INTCH 0F480 FTO0SL 8/16 FTM output 01 select register FTO01SL 0F481 FTO1SL...
Page 529 ML620Q503/Q504 User’s Manual Appendix A Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) – 0F754 C bus 1 transmit data register I2C1TD 0F756 I2C1CON0 8/16 C bus 1 control register I2C1CON 0F757 I2C1CON1 0F758 I2C1MODL 8/16 C bus 1 mode register I2C1MOD 0F759 I2C1MODH...
Page 530 ML620Q503/Q504 User’s Manual Appendix A Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F809 RADMODH 0F80A RADCONL 8/16 RC-ADC control register RADCON 0F80B RADCONH 0F820 SADR0L 8/16 SA-ADC result register 0 SADR0 0F821 SADR0H 0F822 SADR1L 8/16 SA-ADC result register 1 SADR1 0F823 SADR1H...
Page 531 ML620Q503/Q504 User’s Manual Appendix A Registers Address Symbol Symbol Initial value Name Size (Byte) (Word) 0F922 CMP0MODL 8/16 Comparator 0 mode register CMP0MOD 0F923 CMP0MODH – 0F928 Comparator 1 control register CMP1CON 0F92A CMP1MODL 8/16 Comparator 1 mode register CMP1MOD 0F92B CMP1MODH FEUL620Q504...
Page 532: Appendix B Package Dimensions
The surface mount type packages are very susceptible to heat in reflow and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions(reflow method, temperature and times).
Page 533 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics ●Absolute Maximum Rating （V =0V） Parameter Symbol Condition Rating Unit Power supply voltage 1 -0.3 to +4.6 Ta=25°C Power supply voltage 2 -0.3 to +2.0 Ta=25°C Power supply voltage 3 Ta=25°C -0.3 to +2.0 Input voltage...
Page 534 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●Recommended Operating Conditions （V =0V） Parameter Symbol Condition Range Unit Operating temperature °C -40 to +85 – (Ambience) Operating voltage – 1.8 to 3.6 Reference voltage 1.8 to V – Operating frequency 30k to 16.8 M –...
Page 535 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●Operating Conditions of Flash Memory （V = 0V） Parameter Symbol Condition Range Unit °C Data area : write/erase -40 to +85 Operating temperature (Ambience) °C Program area : write/erase 0 to +40 Write/erase 1.8 to 3.6 Operating voltage Data area (1,024B x 2)
Page 536 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●AC characteristics (Oscillation, reset) =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Max. Min. Typ. Low speed crystal – – – oscillation start time High speed crystal –...
Page 537 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●DC Characteristics (IDD) =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. – 0.25 CPU is Stopped Ta=25°C Power µ IDD1 Low/High-speed oscillation is consumption 1 stopped...
Page 538 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●DC Characteristics (VLS) =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. vlscon = 3H 1.798 1.898 1.998 1.900 2.000 2.100 vlscon = 4H 1.993 2.093...
Page 539 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●DC characteristics (VOHL, IOHL) =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Output voltage 1 ≤ ≤ 1.8V 3.6V P00-P05, VOH1 –...
Page 540 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●DC characteristics (IIHL) =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Input current 1 IIH1 VIH1=V – – (RESET_N, IIL1 VIL1=V -900 -300...
Page 541 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●DC characteristics (VIHL) =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Input voltage 1 VIH1 – – (RESET_N, ×V TEST0, TEST1_N, PXT0-PXT1, P00-P05,...
Page 542 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●Measuring circuit Measuring circuit 1 32.768kHz Crystal Oscillator OSC0 OSC1 16MHz Crystal Oscillator : 1.0µF : 2.2µF : 0.33µF : 12pF : 12pF : 16pF 32.768kHz crystal oscillator : DT-26 (from Daishinku) : 16pF 16MHz crystal oscillator : NX8045GB (from Nihon denpa kogyo) Measuring circuit 2...
Page 543 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics Measuring circuit 3 (*2) (*1) (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. Measuring circuit 4 (*3) (*3) Measured at the specified output pins. FEUL620Q504 C-10...
Page 544 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics Measuring circuit 5 (*1) (*1) Input logic circuit to determine the specified measuring conditions. FEUL620Q504...
Page 545 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●AC characteristics（external interrput） =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, nless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. 2.5 x 3.5 x Interruput enable (MIE=1) External interrupt disable φ –...
Page 546 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●AC charctoristics (synchronous serial port) =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, unless otherwise specified) Rating Parameter Symbol Conditon Unit Min. Typ. Max. High-speed oscillation µs – – SCK input cycle is not active SCYC (slave mode) High-speed oscillation is...
Page 547 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●AC characteristics（I C Bus interface : Standard mode 100kHz） =1.8 to 3.6V, V =0V, Ta=-40 to +85°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency – – SCL hold time µs –...
Page 548 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●AC characteristics (RC-ADC) =1.8~3.6V, V =0V, Ta=-40~+85°C, unless otherwise specified) Rating Parameter Symbol Condition unit Min. Typ. Max. RS0,RS1,RT0 Resister for oscillation – – kΩ ,RT0-1,RT1 Resister for oscillation – – OSC1_0 =1kΩ Oscillation freqency = 3.0V Resister for oscillation...
Page 549 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●Electrical Characteristics of SA-ADC =1.8~3.6V, V =0V, Ta=-40~+85°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Resolution – – – 2.7V ≤ V ≤ 3.6V −4 – 2.2V ≤ V −6 Integral non-linearity <...
Page 550 ML620Q503/Q504 User’s manual Appendix C Electrical Characteristics ●Power-on and shutdown Procedures In case of power-on or shutdown of V , the procedures and constraints are shown as following. 10ms or less 0.9×V 0.1×V 30mV or less = 0) over 2sec FEUL620Q504...
Page 551: Appendix D Application Circuit Example
ML620Q503/Q504 User's Manual Appendix D Application Circuit Example Appendix D Application Circuit Example 3.3V RESET_N RESET_N TEST0 TEST1_N P00/IN0 CVR0 ML620Q503/Q504 P01/CS0 P03/RS0 P04/RT0 P02/RCT0 P05/RCM P10/OSC0 P20/IN1 CVR1 P11/OSC1 P21/CS1 16MHz P22/RS1 Xtal P23/RT1 PXT0/XT0 PXT1/XT1 32.768KHz /MD0 /LED /LED Xtal /SCL...
Page 552: Revision History
Revision History...
Page 553 ML620Q503/Q504 User’s Manual Revision History Revision History Page Document No. Date Description Previous Current Edition Edition PEUL620Q504-01 May. 21, 2014 – – Primary edition 1.0 FEUL620Q504-01 Apr. 16, 2015 – – Final edition 1.0 FEUL620Q504 R – 1...

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Rohm LAPIS SEMICONDUCTOR ML620Q503 User Manual

Chapter 1 Overview

Chapter 2 CPU and Memory Space

Chapter 3 Reset Function

Chapter 4 Power Management

Chapter 5 Interrupts

Chapter 6 General Description

Chapter 7 Overview

Chapter 8 Timers

Chapter 9 Function Timer(FTM)

Chapter 10 Watchdog Timer

Chapter 11 Synchronous Serial Port

Chapter 12 Synchronous Serial Port with FIFO (SSIOF)

Chapter 13 UART

Chapter 14 UART with FIFO (UARTF)

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