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Rohm LAPIS ML610Q411 User Manual

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Dear customer
st
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1
day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. ("LAPIS
Technology") and LAPIS Technology succeeded LAPIS Semiconductor's LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020

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  • Page 1 Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1 day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"...
  • Page 2 FEUL610Q411-05 ML610Q411/Q412 User’s Manual Issue Date: July. 13, 2015...
  • Page 3 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
  • Page 4 ML610Q411/Q412 User’s Manual Cover Preface This manual describes the operation of the hardware of the 8-bit microcontroller ML610Q411/ML610Q412. The following manuals are also available. Read them as necessary. nX-U8/100 Core Instruction Manual Description on the basic architecture and the each instruction of the nX-U8/100 Core MACU8 Assembler Package User’s Manual Description on the method of operating the relocatable assembler, the linker, the...
  • Page 5 ML610Q411/Q412 User’s Manual Cover Notation Classification Notation Description ♦ Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F Indicates a binary number; “b” may be omitted. x: A value 0 or 1 ♦...

  • Page 6: Table Of Contents

    ML610Q411/ML610Q412 User’s Manual Contents Table of Contents Chapter 1 Overview................................. 1-1 Features ............................... 1-1 Configuration of Functional Blocks ......................1-5 1.2.1 Block Diagram of ML610Q411 ......................1-5 1.2.2 Block Diagram of ML610Q412 ......................1-6 Pins ................................1-7 1.3.1 Pin Layout ............................1-7 1.3.1.1 Pin Layout of ML610Q411 LQFP Package..................
  • Page 7 ML610Q411/ML610Q412 User’s Manual Contents 4.2.6 Block Control Register 2 (BLKCON2)....................4-7 4.2.7 Block Control Register 3 (BLKCON3)....................4-8 4.2.8 Block Control Register 4 (BLKCON4)....................4-9 Description of Operation........................... 4-11 4.3.1 Program Run Mode ........................... 4-11 4.3.2 HALT Mode ............................. 4-11 4.3.3 STOP Mode ............................
  • Page 8 ML610Q411/ML610Q412 User’s Manual Contents 6.3.2.2 External Clock Input Mode ......................6-9 6.3.2.3 Operation of High-Speed Clock Generation Circuit ..............6-10 6.3.3 Switching of System Clock ....................... 6-12 Specifying port registers ........................... 6-14 6.4.1 Functioning P21 (OUTCLK) as the high speed clock output ............6-14 6.4.2 Functioning P22 (LSCLK) as the low speed clock output ..............
  • Page 9 ML610Q411/ML610Q412 User’s Manual Contents 10.2.1 List of Registers ..........................10-3 10.2.2 Timer 0 Data Register (TM0D) ......................10-4 10.2.3 Timer 1 Data Register (TM1D) ......................10-5 10.2.4 Timer 2 Data Register (TM2D) ......................10-6 10.2.5 Timer 3 Data Register (TM3D) ......................10-7 10.2.6 Timer 0 Counter Register (TM0C) ....................
  • Page 10 ML610Q411/ML610Q412 User’s Manual Contents 13.1.3 List of Pins ............................13-2 13.2 Description of Registers ..........................13-3 13.2.1 List of Registers ..........................13-3 13.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) ............ 13-4 13.2.3 Serial Port Control Register (SIO0CON) ..................13-5 13.2.4 Serial Port Mode Register 0 (SIO0MOD0) ..................
  • Page 11 ML610Q411/ML610Q412 User’s Manual Contents 15.3.1.1 Start Condition ..........................15-9 15.3.1.2 Restart Condition ........................... 15-9 15.3.1.3 Slave Address Transmit Mode ....................... 15-9 15.3.1.4 Data Transmit Mode ........................15-9 15.3.1.5 Data Receive Mode ........................15-9 15.3.1.6 Control Register Setting Wait State ....................15-9 15.3.1.7 Stop Condition ..........................
  • Page 12 ML610Q411/ML610Q412 User’s Manual Contents Chapter 19 19. Port 2 ................................19-1 19.1 Overview..............................19-1 19.1.1 Features ............................. 19-1 19.1.2 Configuration ............................ 19-1 19.1.3 List of Pins ............................19-1 19.2 Description of Registers ..........................19-2 19.2.1 List of Registers ..........................19-2 19.2.2 Port 2 Data Register (P2D) .......................
  • Page 13 ML610Q411/ML610Q412 User’s Manual Contents 22.2.2 Port A Data Register (PAD)......................22-3 22.2.3 Port A Direction Register (PADIR) ....................22-4 22.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) ............... 22-5 22.3 Description of Operation........................... 22-7 22.3.1 Input/Output Port Functions......................22-7 Chapter 23 23.
  • Page 14 ML610Q411/ML610Q412 User’s Manual Contents 25.2.5 SA-ADC Result Register 1H (SADR1H) ..................25-5 25.2.6 SA-ADC Control Register 0 (SADCON0) ..................25-6 25.2.7 SA-ADC Control Register 1 (SADCON1) ..................25-7 25.2.8 SA-ADC Mode Register 0 (SADMOD0) ..................25-8 25.3 Description of Operation........................... 25-9 25.3.1 Settings of A/D Conversion Channels ....................
  • Page 15 ML610Q411/ML610Q412 User’s Manual Contents Appendixes Appendix A Registers ............................A-1 Appendix B Package Dimensions ........................B-1 Appendix C Electrical Characteristics .........................C-1 Appendix D Application Circuit Example ......................D-1 Appendix E Check List ............................E-1 Revision History Revision History ..............................R-1 FEUL610Q411 Contents – 10...

  • Page 16: Overview

    Chapter 1 Overview...

  • Page 17: Features

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview Overview Features This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I C bus interface (master), buzzer driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit successive approximation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100.
  • Page 18 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview • Capture − Time base capture × 2 channels (4096 Hz to 32 Hz) • PWM − Resolution 16 bits × 1 channel • Synchronous serial port − Master/slave selectable − LSB first/MSB first selectable −...
  • Page 19 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview • LCD driver − The number of segments ML610Q411: 144 dots max. (36 seg × 4 com) ML610Q412: 176 dots max. (44 seg × 4 com) − 1/1 to 1/4 duty − 1/3 bias (built-in bias generation circuit) −...
  • Page 20 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview • Product name －Supported Function The line-up of the ML610Q411 and the ML610Q412 is below. Low-speed oscillation Operating - Chip (Die) - ROM type Product availability stop detect reset temperature ML610Q411-xxxWA Flash ROM -20°C to +70°C ML610Q411P-xxxWA Flash ROM -40°C to +85°C...

  • Page 21: Configuration Of Functional Blocks

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview Configuration of Functional Blocks 1.2.1 Block Diagram of ML610Q411 "*" indicates the secondary or tertiary function of each port. CPU (nX-U8/100) EPSW1～3 ELR1～3 ECSR1～3 GREG 0～15 DSR/CSR Timing Controller Program Memory Controller Instruction Instruction (Flash) On-Chip Decoder...

  • Page 22: Block Diagram Of Ml610Q412

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.2.2 Block Diagram of ML610Q412 "*" indicates the secondary or tertiary function of each port. CPU (nX-U8/100) EPSW1～3 ELR1～3 ECSR1～3 GREG 0～15 DSR/CSR Timing Controller Program Memory Controller Instruction Instruction (Flash) On-Chip Decoder Register 16Kbyte Data-bus SCK0*...

  • Page 23: Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview Pins 1.3.1 Pin Layout 1.3.1.1 Pin Layout of ML610Q411 120pin TQFP Package 90pin 61pin 60pin 91pin SEG21 (NC) SEG22 (NC) SEG23 (NC) SEG24 (NC) SEG25 (NC) SEG26 (NC) SEG27 (NC) SEG28 (NC) (NC) SEG29 (NC) SEG30 (NC)
  • Page 24 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.3.1.2 Pin Layout of ML610Q412 120pin TQFP Package 90pin 61pin 60pin 91pin SEG21 (NC) SEG22 (NC) SEG23 (NC) SEG24 (NC) SEG25 (NC) SEG26 (NC) SEG27 (NC) (NC) SEG28 (NC) SEG29 (NC) SEG30 (NC) SEG31 SEG32 (NC) SEG33...

  • Page 25: Pin Layout Of Ml610Q411 Chip

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.3.1.3 Pin Layout of ML610Q411 Chip SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 47 VSS SEG27 46 VDD SEG28 45 VSS SEG29 44 P03 SEG30 100 43 P02 2.636mm SEG31 101 42 P01 SEG32 102 41 P00 SEG33 103 40 NMI...

  • Page 26: Pin Layout Of Ml610Q412 Chip

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.3.1.4 Pin Layout of ML610Q412 Chip SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 47 VSS SEG27 46 VDD SEG28 45 VSS SEG29 44 P03 SEG30 100 43 P02 2.636mm SEG31 101 42 P01 SEG32 102 41 P00 SEG33 103 40 NMI...

  • Page 27: Pad Coordinates Of Ml610Q411 Chip

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.3.1.5 Pad Coordinates of ML610Q411 Chip Table 1-1 Pad Coordinates of ML610Q411 Chip Center: X=0,Y=0 Name X(µm) Y(µm) Name X(µm) Y(µm) Name X(µm) Y(µm) (NC) SEG31 -1230 -1212 -1312 (NC) SEG32 -1150 -1212 -1312 (NC) SEG33 -1070...

  • Page 28: Pad Coordinates Of Ml610Q412 Chip

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.3.1.6 Pad Coordinates of ML610Q412 Chip Table 1-2 Pad Coordinates of ML610Q412 Chip Center: X=0,Y=0 Name X(µm) Y(µm) Name X(µm) Y(µm) Name X(µm) Y(µm) (NC) SEG31 -1230 -1212 -1312 (NC) SEG32 -1150 -1212 -1312 (NC) SEG33 -1070...

  • Page 29: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.3.2 List of Pins Primary function Secondary function Tertiary function Pin name Function Pin name Function Pin name Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Negative power supply pin 24,45,47 ⎯ ⎯ ⎯ ⎯...
  • Page 30 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview Primary function Secondary function Tertiary function Pin name Function Pin name Function Pin name Function oscillation input pin RC type ADC0 ⎯ ⎯ ⎯ Input/output port reference capacitor connection pin RC type ADC0 resistor/capacitor Input/output port PWM output RCT0...
  • Page 31 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview Primary function Secondary function Tertiary function Pin name Function Pin name Function Pin name Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LCD segment pin SEG3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LCD segment pin SEG4 ⎯...

  • Page 32: Description Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.3.3 Description of Pins Primary/ Secondary/ Pin name Description Logic Tertiary System Reset input pin. When this pin is set to a “L” level, system reset mode is RESET_N — Negative set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts.
  • Page 33 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview Pin name Description Primary/ Logic Secondary/ Tertiary UART UART data output pin. This pin is used as the secondary function of the TXD0 Secondary Positive P43 pin. UART data input pin. This pin is used as the secondary function of the RXD0 Primary/Se Positive...
  • Page 34 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview Primary/ Pin name Description Secondary/ Logic Tertiary RC oscillation type A/D converter Channel 0 oscillation input pin. This pin is used as the secondary function Secondary — of the P30 pin. Channel 0 reference capacitor connection pin. This pin is used as the Secondary —...
  • Page 35 ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview Primary/ Pin name Description Secondary/ Logic Tertiary Power supply pin for programming Flash ROM. A pull-down resistor is — — — internally connected. FEUL610Q411 1 – 19...

  • Page 36: Termination Of Unused Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 1 Overview 1.3.4 Termination of Unused Pins Table 1-3 shows methods of terminating the unused pins. Table 1-3 Termination of Unused Pins Recommended pin termination Open AIN0, AIN1 Open Open C1, C2 Open RESET_N Open TEST Open Open P00 to P03...

  • Page 37: Cpu And Memory Space

    Chapter 2 CPU and Memory Space...

  • Page 38: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 2 CPU and Memory Space CPU and Memory Space Overview This LSI includes LAPIS Semiconductor’s original 8-bit CPU nX-U8/100 and the memory model is “SMALL model” . For details of the CPU nX-U8/100, see “nX-U8/100 Core Instruction Manual”. Program Memory Space The program memory space is used to store program codes, table data (ROM window), or vector tables.

  • Page 39: Data Memory Space

    ML610Q411/ML610Q412 User’s Manual Chapter 2 CPU and Memory Space Data Memory Space The data memory space of this LSI consists of the ROM window area, 1KByte RAM area and SFR area of Segment 0 and the ROM reference areas of the Segment 1 and Segment 8. The data memory stores 8-bit data and is specified by 20 bits consisting of higher 4 bits as DSR and lower 16 bits as addressing specified by each instruction.

  • Page 40: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 2 CPU and Memory Space Description of Registers 2.6.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F000H Data segment register FEUL610Q411 2 – 3...

  • Page 41: Data Segment Register (Dsr)

    ML610Q411/ML610Q412 User’s Manual Chapter 2 CPU and Memory Space 2.6.2 Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8 bits Initial value: 00H     DSR3 DSR2 DSR1 DSR0 Initial value DSR is a special function register (SFR) to retain a data segment. For details of DSR, see “nX-U8/100 Core Instruction Manual”.

  • Page 42: Reset Function

    Chapter 3 Reset Function...

  • Page 43: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 3 Reset Function Reset Function Overview This LSI has the five reset functions shown below. If any of the five reset conditions is satisfied, this LSI enters system reset mode. • Reset by the RESET_N pin •...

  • Page 44: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 3 Reset Function Description of Registers 3.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value   0F001H Reset status register RSTAT 3.2.2 Reset Status Register (RSTAT) Address: 0F001H Access: R/W Access size: 8 bits Initial value: Undefined ―...

  • Page 45: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 3 Reset Function Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all the processings and any other processing being executed up to then is cancelled. The system reset mode is set by any of the following causes. •...

  • Page 46: Mcu Control Function

    Chapter 4 MCU Control Function...

  • Page 47: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function MCU Control Function Overview The operating states of this LSI are classified into the following 4 modes including system reset mode: System reset mode Program run mode HALT mode STOP mode For system reset mode, see Chapter 3, “Reset Function”. This LSI has a block control function, which power downs the circuits of unused peripherals (reset registers and stop clock supplies) to make even more reducing the current consumption.

  • Page 48: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function Description of Registers 4.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value   Stop code acceptor 0F008H STPACP  0F009H Standby control register SBYCON  0F028H Block control register 0 BLKCON0 ...

  • Page 49: Stop Code Acceptor (Stpacp)

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.2.2 Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value:  (Undefined) ― ― ― ― ― ― ― ― STPACP ― ― ― ― ― ― ―...

  • Page 50: Standby Control Register (Sbycon)

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H ― ― ― ― ― ― SBYCON Initial value SBYCON is a special function register (SFR) to control operating mode of MCU. [Description of Bits] •...

  • Page 51: Block Control Register 0(Blkcon0)

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.2.4 Block Control Register 0(BLKCON0) Address: 0F028H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― BLKCON0 DTM3 DTM2 DTM1 DTM0 Initial value BLKCON0 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off.

  • Page 52: Block Control Register 1(Blkcon1)

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.2.5 Block Control Register 1(BLKCON1) Address: 0F029H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― ― BLKCON1 DCAPR DT1K DPW0 Initial value BLKCON1 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off.

  • Page 53: Block Control Register 2(Blkcon2)

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.2.6 Block Control Register 2(BLKCON2) Address: 0F02AH Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― ― BLKCON2 DI2C0 DUA0 DSIO0 Initial value BLKCON2 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off.

  • Page 54: Block Control Register 3(Blkcon3)

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.2.7 Block Control Register 3(BLKCON3) Address: 0F02BH Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― ― ― ― BLKCON3 DMD0 Initial value BLKCON3 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off.

  • Page 55: Block Control Register 4(Blkcon4)

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.2.8 Block Control Register 4(BLKCON4) Address: 0F02CH Access: R/W Access size: 8 bits Initial value: 00H ― ― ― BLKCON4 DLCD DBLD DXTSP DRAD DSAD Initial value BLKCON4 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off.
  • Page 56 ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function • DSAD (bit 0) The DSAD bit is used to control SA type A/D converter operation. When the DSAD bit is set to “1”, the circuits related to SA type A/D converter are reset and turned off. DSAD Description Enable operating SA type A/D converter (initial value)

  • Page 57: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, RESET_N pin reset, low-speed oscillation stop detect reset, or WDT overflow reset, the CPU executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system reset mode is released.

  • Page 58: Stop Mode

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.3.3 STOP Mode The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by writing “5nH”(n: an arbitrary value) and “0AnH”(n: an arbitrary value) to the stop code acceptor (STPACP) sequentially and the STP bit of the standby control register (SBYCON) is set to “1”, the STOP mode is entered.

  • Page 59: Stop Mode When Cpu Operates With High-Speed Clock

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock When the CPU is operating with a high-speed clock and the STP bit of SBYCON is set to “1” with the stop code acceptor enabled, the STOP mode is entered and high-speed oscillation and low-speed oscillation stop.

  • Page 60: Note On Return Operation From Stop/Halt Mode

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.3.3.3 Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.

  • Page 61: Block Control Function

    ML610Q411/ML610Q412 User’s Manual Chapter 4 MCU Control Function 4.3.4 Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop.

  • Page 62: Interrupts (Ints)

    Chapter 5 Interrupts (INTs)

  • Page 63: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) Interrupts (INTs) Overview This LSI has 25 interrupt sources (External interrupts: 5 sources, Internal interrupts: 20 sources) and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 7, “Time Base Counter” Chapter 9, “1 kHz Timer”...

  • Page 64: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) Description of Registers 5.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F011H Interrupt enable register 1  0F012H Interrupt enable register 2  0F013H Interrupt enable register 3 ...

  • Page 65: Interrupt Enable Register 1 (Ie1)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.2 Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8 bits Initial value: 00H     EP03 EP02 EP01 EP00 Initial value IE1 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE1 is not reset.

  • Page 66: Interrupt Enable Register 2 (Ie2)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.3 Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8 bits Initial value: 00H      EI2C0 ESAD ESIO0 Initial value IE2 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE2 is not reset.

  • Page 67: Interrupt Enable Register 3 (Ie3)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.4 Interrupt Enable Register 3 (IE3) Address: 0F013H Access: R/W Access size: 8 bits Initial value: 00H       ETM1 ETM0 Initial value IE3 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE3 is not reset.

  • Page 68: Interrupt Enable Register 4 (Ie4)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.5 Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8 bits Initial value: 00H       ERAD EUA0 Initial value IE4 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE4 is not reset.

  • Page 69: Interrupt Enable Register 5 (Ie5)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.6 Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8 bits Initial value: 00H       ETM3 ETM2 Initial value IE5 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE5 is not reset.

  • Page 70: Interrupt Enable Register 6 (Ie6)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.7 Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8 bits Initial value: 00H     E32H E128H ET1K EPW0 Initial value IE6 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE6 is not reset.

  • Page 71: Interrupt Enable Register 7 (Ie7)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.8 Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8 bits Initial value: 00H       E16H Initial value IE7 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE7 is not reset.

  • Page 72: Interrupt Request Register 0 (Irq0)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.9 Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8 bits Initial value: 00H       IRQ0 QNMI QWDT Initial value IRQ0 is a special function register (SFR) to request an interrupt for each interrupt source. The watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT) are non-maskable interrupts that do not depend on MIE.

  • Page 73: Interrupt Request Register 1 (Irq1)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.10 Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8 bits Initial value: 00H     IRQ1 QP03 QP02 QP01 QP00 Initial value IRQ1 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ1 request flag is set to “1”...

  • Page 74: Interrupt Request Register 2 (Irq2)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.11 Interrupt Request Register 2 (IRQ2) Address: 0F01AH Access: R/W Access size: 8 bits Initial value: 00H      IRQ2 QI2C0 QSAD QSIO0 Initial value IRQ2 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ2 request flag is set to “1”...

  • Page 75: Interrupt Request Register 3 (Irq3)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.12 Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8 bits Initial value: 00H       IRQ3 QTM1 QTM0 Initial value IRQ3 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ3 request flag is set to “1”...

  • Page 76: Interrupt Request Register 4 (Irq4)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.13 Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8 bits Initial value: 00H       IRQ4 QRAD QUA0 Initial value IRQ4 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ4 request flag is set to “1”...

  • Page 77: Interrupt Request Register 5 (Irq5)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.14 Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8 bits Initial value: 00H       IRQ5 QTM3 QTM2 Initial value IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ5 request flag is set to “1”...

  • Page 78: Interrupt Request Register 6 (Irq6)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.15 Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8 bits Initial value: 00H     IRQ6 Q32H Q128H QT1K QPW0 Initial value IRQ6 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ6 request flag is set to “1”...

  • Page 79: Interrupt Request Register 7 (Irq7)

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.2.16 Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8 bits Initial value: 00H       IRQ7 Q16H Initial value IRQ7 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ7 request flag is set to “1”...

  • Page 80: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) Description of Operation With the exception of the watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT), interrupt enable/disable for 19 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE1 to 7).

  • Page 81: Maskable Interrupt Processing

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.3.1 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) Transfer the program counter (PC) to ELR1.

  • Page 82: Notes On Interrupt Routine

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.3.4 Notes on Interrupt Routine Notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable.
  • Page 83 ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution Specify the “PUSH LR” instruction to save the subroutine return address in the stack. •...
  • Page 84 ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) State B: Non-maskable interrupt is being processed B-1: When no instruction is executed in an interrupt routine • Processing immediately after the start of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW.

  • Page 85: Interrupt Disable State

    ML610Q411/ML610Q412 User’s Manual Chapter 5 Interrupts (INTs) 5.3.5 Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state. Interrupt disabled state 1: Between the interrupt shift cycle and the instruction at the beginning of the interrupt routine When the interrupt conditions are satisfied in this section, an interrupt is generated immediately following the...

  • Page 86: Clock Generation Circuit

    Chapter 6 Clock Generation Circuit...

  • Page 87: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit Clock Generation Circuit Overview The clock generation circuit generates and provides a low-speed clock (LSCLK), 2× low-speed clock (LSCLK2), a high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK). LSCLK, LSCLK×2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU, and OUTCLK is a clock that is output from a port.

  • Page 88: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Pin name Description Pin for connecting a crystal for low-speed clock Pin for connecting a crystal for low-speed clock Pin for an external high-speed clock input P10/OSC0 Used for the secondary function of the P10 pin Description of Registers 6.2.1 List of Registers...
  • Page 89 ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.2.2 Frequency Control Register 0 (FCON0) Address: 0F002H Access: R/W Access size: 8/16 bits Initial value: 33H    FCON0 OUTC1 OUTC0 OSCM0 SYSC1 SYSC0 Initial value FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. [Description of Bits] •...
  • Page 90 ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit Note: − To switch the mode of the high-speed clock generation circuit using the OSCM0 bit, stop the high-speed oscillation and set the system clock to the low-speed clock (set the ENOSC bit and SYSCLK of FCON1 to “0”). −...
  • Page 91 ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 1 (FCON1) Address: 0F003H Access: R/W Access size: 8 bits Initial value: 03H      FCON1 ENMLT ENOSC SYSCLK Initial value FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. [Description of Bits] •...

  • Page 92: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Clock Generation Circuit Figure 6-2 shows the configuration of the low-speed clock generation circuit. A low-speed clock generation circuit is provided with an external 32.768 kHz crystal. To match the oscillation frequency by using a trimmer capacitor, connect external capacitors (C and C ) as required.

  • Page 93: Operation Of Low-Speed Clock Generation Circuit

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.3.1.2 Operation of Low-Speed Clock Generation Circuit The low-speed clock generation circuit is activated by the occurrence of power ON reset. A low-speed clock (LSCLK) is supplied to the peripheral circuits after the elapse of the low-speed oscillation start period (T ) and oscillation stabilization period (8192 counts) after powered on.

  • Page 94: High-Speed Clock

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2 High-Speed Clock Setting of the OSCM0 bits of the frequency control register 0 (FCON0) allows selection of the 500 kHz RC oscillation mode or external clock input mode for the high-speed clock generation circuit. 6.3.2.1 500 kHz RC Oscillation In RC oscillation mode (OSCM0 = “0”), supply of OSCLK (high-speed oscillation clock) is started when RC oscillation...

  • Page 95: External Clock Input Mode

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.2 External Clock Input Mode In external clock input mode, external clock is input from the P10/OSC0 pin. Figure 6-5 shows the circuit configuration in external clock input mode. STOP mode ENOSC (Enables oscillation) High-speed oscillation clock External clock input (OSCLK)

  • Page 96: Operation Of High-Speed Clock Generation Circuit

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.3 Operation of High-Speed Clock Generation Circuit The high-speed clock generation circuit is activated in 500Hz RC oscillation mode by power-on reset generation. As a result of the occurrence of power-on reset, the circuit goes into system reset mode and then shifts to program operating mode after the elapse of the high-speed RC oscillation start time (T ) and the oscillation stabilization time (Count: 8192) of the high-speed oscillation clock (OSCLK) and at the same time, a high-speed clock (HSCLK) is...
  • Page 97 ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit Figure 6-7 shows the waveforms of the high-speed clock generation circuit in crystal/ceramic oscillation mode. High-speed oscillation enable ENOSC : 500kHz RC oscillation start time : 500kHz RC oscillation start time High-speed oscillation High-speed oscillation waveform waveform High-speed oscillation waveform...

  • Page 98: Switching Of System Clock

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.3.3 Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-8 shows a flow of system clock switching processing (HSCLK→LSCLK) and Figure 6-11 shows a flow of system clock switching processing (LSCLK→HSCLK).
  • Page 99 ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit Set high-speed oscillation mode before switching the system System clock switching clock. Remain using the low-speed clock (LSCLK). 500 kHz RC ? When using 500kHz RC oscillation mode or Voltage detection by 500kHz external clock mode, check that V 1.3V or higher by using BLD.

  • Page 100: Specifying Port Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit Specifying port registers When you want to make sure clock output functions are working, please check related port registers are specified. See Chapter 20, “Port2” for detail about the port registers. 6.4.1 Functioning P21 (OUTCLK) as the high speed clock output Set P21MD bit (bit1 of P2MOD register) to “1”...

  • Page 101: Functioning P22 (Lsclk) As The Low Speed Clock Output

    ML610Q411/ML610Q412 User’s Manual Chapter 6 Clock Generation Circuit 6.4.2 Functioning P22 (LSCLK) as the low speed clock output Set P22MD bit (bit2 of P2MOD register) to “1” for specifying the low speed clock output as the secondary function of P22. Reg.

  • Page 102: Time Base Counter

    Chapter 7 Time Base Counter...

  • Page 103: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter Time Base Counter Overview This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base clocks for peripheral circuits. By using the time base counter, it is possible to generate events periodically. For input clocks, see Chapter 6, “Clock Generation Circuit”.
  • Page 104 ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter HSCLK HTBDR HTBCLK (500kHz) 1/n-Counter (500kHz to 31kHz) RESET (Internal signal) Data bus HTBDR: High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK changes according to specified data in SYSC1 bit and SYSC0 bit of Frequency control register 0 (FON0) FEUL610Q411 7 –...

  • Page 105: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter Description of Registers 7.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Low-speed time base counter  0F00AH LTBR register High-speed time base counter  0F00BH HTBDR frequency divide register Low-speed time base counter 0F00CH LTBADJL...

  • Page 106: Low-Speed Time Base Counter (Ltbr)

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter (LTBR) Address: 0F00AH Access: R/W Access size: 8 bits Initial value: 00H LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ Initial value LTBR is a special function register (SFR) to read the T128HZ-T1HZ outputs of the low-speed time base counter. The T128HZ-T1HZ outputs are set to “0”...

  • Page 107: High-Speed Time Base Counter Divide Register (Htbdr)

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter 7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) Address: 0F00BH Access: R/W Access size: 8 bits Initial value: 00H     HTBDR HTD3 HTD2 HTD1 HTD0 Initial value HTBDR is a special function register (SFR) to set the divide ratio of the 4-bit, 1/n counter. [Description of Bits] •...

  • Page 108: Low-Speed Time Base Counter Frequency Adjustment Registers L And H (Ltbadjl, Ltbadjh)

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter 7.2.4 Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH) Address: 0F00CH Access: R/W Access size: 8/16 bits Initial value: 00H LTBADJL LADJ7 LADJ6 LADJ5 LADJ4 LADJ3 LADJ2 LADJ1 LADJ0 Initial value Address: 0F00DH...

  • Page 109: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The T128HZ, T32HZ, T16HZ, and T2HZ outputs of LTBC are used as time base interrupts and an interrupt is requested on the falling edge of each output.

  • Page 110: High-Speed Time Base Counter

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter 7.3.2 High-Speed Time Base Counter The high-speed time base counter is configured as a 4-bit 1/n counter (n = 1 to 16). In the 4-bit 1/n counter, the divided clock (1/16×HSCLK to 1/1×HSCLK) selected by the high-speed time base counter divide register (HTBDR) is generated as HTBCLK.

  • Page 111: Low-Speed Time Base Counter Frequency Adjustment Function

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter 7.3.3 Low-Speed Time Base Counter Frequency Adjustment Function Frequency adjustment (Adjustment range: Approx. −488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm) is possible for outputs of T8KHZ to T1HZ of LTBC by using the low-speed time base counter frequency adjust registers (LTBADJH and LTBADJL).

  • Page 112: A Signal Generation For 16Bit Timer 2-3 Frequency Measurement Mode

    ML610Q411/ML610Q412 User’s Manual Chapter 7 Time Base Counter 7.3.4 A signal generation for 16bit timer 2-3 frequency measurement mode A signal (437C) used for 16bit timer 2-3 frequency measurement mode is generated in the time base conter block. See Chapter 10, “Timer” for more detail about the frequency measurement function. 16KHz 8KHz 4KHz...

  • Page 113: Capture

    Chapter 8 Capture...

  • Page 114: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 8 Capture Capture Overview This LSI has two channels of capture circuits that capture the T4KHZ to T32HZ signals of the low-speed base counter (LTBC) to the capture register at the occurrence of P00 and P01 interrupts. The circuits capture timings at which each interrupt occurred, based on the time from the time base counter.

  • Page 115: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 8 Capture Description of Registers 8.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F090H Capture control register CAPCON  0F091H Capture status register CAPSTAT  0F092H Capture data register 0 CAPR0 ...

  • Page 116: Capture Control Register (Capcon)

    ML610Q411/ML610Q412 User’s Manual Chapter 8 Capture 8.2.2 Capture Control Register (CAPCON) Address: 0F090H Access: R/W Access size: 8 bits Initial value: 00H       CAPCON ECAP1 ECAP0 Initial value CAPCON is a special function register (SFR) to control the capture circuit. [Description of Bits] •...

  • Page 117: Capture Status Register (Capstat)

    ML610Q411/ML610Q412 User’s Manual Chapter 8 Capture 8.2.3 Capture Status Register (CAPSTAT) Address: 0F091H Access: R/W Access size: 8 bits Initial value: 00H       CAPSTAT CAPF1 CAPF0 Initial value CAPSTAT is a special function register (SFR) to indicate a state of the capture circuit. [Description of Bits] •...

  • Page 118: Capture Data Register 0 (Capr0)

    ML610Q411/ML610Q412 User’s Manual Chapter 8 Capture 8.2.4 Capture Data Register 0 (CAPR0) Address: 0F092H Access: R/W Access size: 8 bits Initial value: 00H CAPR0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Initial value CAPR0 is a register in which capture data is stored. The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P00 interrupt request is generated with the CAPF0 flag (bit 0 of the CAPSTAT register) set to "0".

  • Page 119: Capture Data Register 1 (Capr1)

    ML610Q411/ML610Q412 User’s Manual Chapter 8 Capture 8.2.5 Capture Data Register 1 (CAPR1) Address: 0F093H Access: R/W Access size: 8 bits Initial value: 00H CAPR1 CP17 CP16 CP15 CP14 CP13 CP12 CP11 CP10 Initial value CAPR1 is a register in which capture data is stored. The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P01 interrupt request is generated with the CAPF1 flag (bit 1 of the CAPSTAT register) set to "0".

  • Page 120: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 8 Capture Description of Operation The capture circuit starts the capture operation by setting the ECAP0 or ECAP1 bit of the capture control register (CAPCON). When the input trigger from the P00 or P01 pin selected by the external interrupt control register 0 or 1 (EXICON0 or EXICON1) is generated and the P00 or P01 interrupt request flag (QP00 or QP01) is set to “1”, the T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured in the capture register 0 or 1 (CAPR0 or CAPR1) on the next low-speed clock (LSCLK) falling edge and the at the same time, the capture flag (CAPF0 or CAPF1) of the...

  • Page 121: Khz Timer (1Khztm)

    Chapter 9 1 kHz Timer (1kHzTM)

  • Page 122: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) 1 kHz Timer (1kHzTM) Overview This LSI includes a 1 kHz timer to measure 1/1000 seconds. The 1 kHz timer counts the 1 kHz(1.024kHz) signal created by dividing the T2KHZ output frequency (2.048kHz) of the low-speed time base counter (LTBC) and generates a 10 Hz or 1 Hz interrupt (1 kHz timer interrupt).

  • Page 123: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) Description of Registers 9.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F080H 1 kHz timer count register L T1KCRL 8/16 T1KCR 0F081H 1 kHz timer count register H T1KCRH ...

  • Page 124: Khz Timer Count Registers (T1Kcrl, T1Kcrh)

    ML610Q411/ML610Q412 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) 9.2.2 1 kHz Timer Count Registers (T1KCRL, T1KCRH) Address: 0F080H Access: R/W Access size: 8/16 bits Initial value: 00H     T1KCRL T1KC3 T1K02 T1KC1 T1KC0 Initial value Address: 0F081H Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 125: Khz Timer Control Register (T1Kcon)

    ML610Q411/ML610Q412 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) 9.2.3 1 kHz Timer Control Register (T1KCON) Address: 0F082H Access: R/W Access size: 8 bits Initial value: 00H       T1KCON T1KSEL T1KRUN Initial value T1KCON is a special function register (SFR) to control the 1 kHz timer. [Description of Bits] •...

  • Page 126: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) Description of Operation By setting the T1KRUN bit of the 1kHz timer control register (T1KCON) to “1”, the 1kHz timer starts counting of the 1kHz timer counter registers L or H (T1KCRL, T1KCRH). By dividing the T2KHz signal frequency (2.048kHz) of the low-speed timer base counter (LTBC) by the binary/ternary counter, the timer generates a 1kHz signal.

  • Page 127: Timers

    Chapter 10 Timers...

  • Page 128: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers Timers 10.1 Overview This LSI includes 4 channels of 8-bit timers. For the input clock, see Chapter 6, “Clock Generation Circuit”. 10.1.1 Features • The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=0 to 3) and timer data register (TMnD) coincide.
  • Page 129 ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers Low-speed Timer Base Counter(LTBC) 16KHz 8KHz Counter 436cycle 4KHz 2KHz 32KHz 1KHz Decoder 512Hz 256Hz 128Hz 64Hz TM3NT Write TM2C Write TM3C 64Hz 437c LSCLK T2CK TM2CON0 HTBCLK TM2C TM3C External clock TM2CON1 P44/T02P0CK P45/T13P1CK Read TM2C TM3C latch...
  • Page 130 ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2 Description of Registers 10.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Timer 0 data register 0F030H TM0D 8/16 0FFH TM0DC Timer 0 counter register 0F031H TM0C Timer 0 control register 0 0F032H TM0CON0 8/16...

  • Page 131: Timer 0 Data Register (Tm0D)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.2 Timer 0 Data Register (TM0D) Address: 0F030H Access: R/W Access size: 8 bits Initial value: 0FFH TM0D T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 Initial value TM0D is a special function register (SFR) to set the value to be compared with the timer 0 counter register (TM0C) value.

  • Page 132: Timer 1 Data Register (Tm1D)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.3 Timer 1 Data Register (TM1D) Address: 0F034H Access: R/W Access size: 8 bits Initial value: 0FFH TM1D T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 Initial value TM1D is a special function register (SFR) to set the value to be compared with the value of the timer 1 counter register (TM1C).

  • Page 133: Timer 2 Data Register (Tm2D)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.4 Timer 2 Data Register (TM2D) Address: 0F038H Access: R/W Access size: 8 bits Initial value: 0FFH TM2D T2D7 T2D6 T2D5 T2D4 T2D3 T2D2 T2D1 T2D0 Initial value TM2D is a special function register (SFR) to set the value to be compared with the value of the timer 2 counter register (TM2C).

  • Page 134: Timer 3 Data Register (Tm3D)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.5 Timer 3 Data Register (TM3D) Address: 0F03CH Access: R/W Access size: 8 bits Initial value: 0FFH TM3D T3D7 T3D6 T3D5 T3D4 T3D3 T3D2 T3D1 T3D0 Initial value TM3D is a special function register (SFR) to set the value to be compared with the value of the timer 3 counter register (TM3C).

  • Page 135: Timer 0 Counter Register (Tm0C)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.6 Timer 0 Counter Register (TM0C) Address: 0F031H Access: R/W Access size: 8 bits Initial value: 00H TM0C T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 Initial value TM0C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM0C is performed, TM0C is set to “00H”.

  • Page 136: Timer 1 Counter Register (Tm1C)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.7 Timer 1 Counter Register (TM1C) Address: 0F035H Access: R/W Access size: 8 bits Initial value: 00H TM1C T1C7 T1C6 T1C5 T1C4 T1C3 T1C2 T1C1 T1C0 Initial value TM1C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM1C is performed, TM1C is set to “00H”.

  • Page 137: Timer 2 Counter Register (Tm2C)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.8 Timer 2 Counter Register (TM2C) Address: 0F039H Access: R/W Access size: 8 bits Initial value: 00H TM2C T2C7 T2C6 T2C5 T2C4 T2C3 T2C2 T2C1 T2C0 Initial value TM2C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM2C is performed, TM2C is set to “00H”.

  • Page 138: Timer 3 Counter Register (Tm3C)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.9 Timer 3 Counter Register (TM3C) Address: 0F03DH Access: R/W Access size: 8 bits Initial value: 00H TM3C T3C7 T3C6 T3C5 T3C4 T3C3 T3C2 T3C1 T3C0 Initial value TM3C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM3C is performed, TM3C is set to “00H”.

  • Page 139: Timer 0 Control Register 0 (Tm0Con0)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.10 Timer 0 Control Register 0 (TM0CON0) Address: 0F032H Access: R/W Access size: 8 bits Initial value: 00H      TM0CON0 T01M16 T0CS1 T0CS0 Initial value TM0CON0 is a special function (SFR) to control a timer 0. Rewrite TM0CON0 while the timer 0 is stopped (T0STAT of the TM0CON1 register is “0”).

  • Page 140: Timer 1 Control Register 0 (Tm1Con0)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.11 Timer 1 Control Register 0 (TM1CON0) Address: 0F036H Access: R/W Access size: 8 bits Initial value: 00H       TM1CON0 T1CS1 T1CS0 Initial value TM1CON0 is a special function (SFR) to control a timer 1. Rewrite TM1CON0 while the timer 1 is stopped (T1STAT of the TM1CON1 register is “0”).

  • Page 141: Timer 2 Control Register 0 (Tm2Con0)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.12 Timer 2 Control Register 0 (TM2CON0) Address: 0F03AH Access: R/W Access size: 8 bits Initial value: 0A0H TM2CON0 T2FMA7 T2FMA6 T2FMA5 T2FMA4 T23MFM T23M16 T2CS1 T2CS0 Initial value TM2CON0 is a special function (SFR) to control a timer 2. Rewrite TM2CON0 while the timer 2 is stopped (T2STAT of the TM2CON1 register is “0”).

  • Page 142: Timer 3 Control Register 0 (Tm3Con0)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.13 Timer 3 Control Register 0 (TM3CON0) Address: 0F03EH Access: R/W Access size: 8 bits Initial value: 00H       TM3CON0 T3CS1 T3CS0 Initial value TM3CON0 is a special function (SFR) to control a timer 3. Rewrite TM3CON0 while the timer 3 is stopped (T3STAT of the TM3CON1 register is “0”).

  • Page 143: Timer 0 Control Register 1 (Tm0Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.14 Timer 0 Control Register 1 (TM0CON1) Address: 0F033 Access: R/W Access size: 8 bits Initial value: 00H       TM0CON1 T0STAT T0RUN Initial value TM0CON1 is a special function register (SFR) to control a timer 0. [Description of Bits] •...

  • Page 144: Timer 1 Control Register 1 (Tm1Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.15 Timer 1 Control Register 1 (TM1CON1) Address: 0F037H Access: R/W Access size: 8 bits Initial value: 00H       TM1CON1 T1STAT T1RUN Initial value TM1CON1 is a special function register (SFR) to control a timer 1. [Description of Bits] •...

  • Page 145: Timer 2 Control Register 1 (Tm2Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.16 Timer 2 Control Register 1 (TM2CON1) Address: 0F03BH Access: R/W Access size: 8 bits Initial value: 00H       TM2CON1 T2STAT T2RUN Initial value TM2CON1 is a special function register (SFR) to control a timer 2. [Description of Bits] •...

  • Page 146: Timer 3 Control Register 1 (Tm3Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.2.17 Timer 3 Control Register 1 (TM3CON1) Address: 0F03FH Access: R/W Access size: 8 bits Initial value: 00H       TM3CON1 T3STAT T3RUN Initial value TM3CON1 is a special function register (SFR) to control a timer 3. [Description of Bits] •...

  • Page 147: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.3 Description of Operation 10.3.1 Timer mode operation The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer clocks (TnCK) that are selected by the Timer 0 to 3 control register 0 (TMnCON0) when the TnRUN bits of timer 0 to 3 control register 1 (TMnCON1) are set to “1”...

  • Page 148: 16-Bit Timer Frequency Measurement Mode Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.3.2 16-bit timer frequency measurement mode operation The frequency measurement mode in 16-bit timer 2&3, is used to count the frequency of 500kHz RC oscillation clock which typically has temperature variation and production tolerance. Using the frequency measurement mode can make better accuracy for uart baud-rate clock or timer function.
  • Page 149 ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers (5) Clear both TM2C register and TM3C register to “00H”. (6) Set T2RUN bit (bit0 of TM2CON1 register) to “1” to start counting the timer. (7) On the condition of (T23MFM bit=="1") & ((TM23M16 bit=="1") & (T2RUN bit=="1"), the count-up starts at rising edge of 64Hz clock signal.

  • Page 150: 16-Bit Timer Frequency Measurement Mode Application For Setting Uart Baud-Rate

    ML610Q411/ML610Q412 User’s Manual Chapter 10 Timers 10.3.3 16-bit timer frequency measurement mode application for setting uart baud-rate For example, when the target baud-rate is 9600bps and the clock is HSCLK(500kHz), the UART0 baud-rate register (UA0BRTH, UA0BRTL) should be set as follows. See Section 14.3.2. in UART chapter. UA0BRTH, UA0BRTL = 500000/9600 - 1 = 51 (decimal) = 33(Hexadecimal) However, actual 500kHz RC oscillation clock has temperature variation and production tolerance, the calculation by using the fixed value of 500kHz can not make accurate baud-rate.

  • Page 151: Pwm

    Chapter 11...

  • Page 152: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.1 Overview This LSI includes one channel of 16-bit PWM (Pulse Width Modulation). The PWM output (PWM0) function is assigned to P43(Port 4) and P34(Port 3) as the tertiary function. For the functions of port 4 and port3, see Chapter 21, “Port 4” and Chapter 20, “Port 3”. 11.1.1 Features •...

  • Page 153: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.1.3 List of Pins Pin name Description PWM0 output pin P43/PWM0 Used for the secondary function of the P43 pin. PWM0 output pin P34/PWM0 Used for the secondary function of the P34 pin. 11.2 Description of Registers 11.2.1 List of Registers Address...

  • Page 154: Pwm0 Period Registers (Pw0Pl, Pw0Ph)

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.2.2 PWM0 Period Registers (PW0PL, PW0PH) Address: 0F0A0H Access: R/W Access size: 8 bits Initial value: 0FFH PW0PL P0P7 P0P6 P0P5 P0P4 P0P3 P0P2 P0P1 P0P0 At reset Address: 0F0A1H Access: R/W Access size: 8 bits Initial value: 0FFH PW0PH P0P15...

  • Page 155: Pwm0 Duty Registers (Pw0Dl, Pw0Dh)

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.2.3 PWM0 Duty Registers (PW0DL, PW0DH) PW0DL P0D7 P0D6 P0D5 P0D4 P0D3 P0D2 P0D1 P0D0 At reset Address: 0F0A2H Access: R/W Access size: 8 bits Initial value: 00H PW0DH P0D15 P0D14 P0D13 P0D12 P0D11 P0D10 P0D9 P0D8...

  • Page 156: Pwm0 Counter Registers (Pw0Ch, Pw0Cl)

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.2.4 PWM0 Counter Registers (PW0CH, PW0CL) PW0CL P0C7 P0C6 P0C5 P0C4 P0C3 P0C2 P0C1 P0C0 At reset Address: 0F0A4H Access: R/W Access size: 8 bits Initial value: 00H PW0DH P0C15 P0C14 P0C13 P0C12 P0C11 P0C10 P0C9 P0C8...

  • Page 157: Pwm0 Control Register 0 (Pw0Con0)

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.2.5 PWM0 Control Register 0 (PW0CON0)    PW0CON0 P0NEG P0IS1 P0IS0 P0CS1 P0CS0 At reset Address: 0F0A6H Access: R/W Access size: 8 bits Initial value: 00H PW0CON0 is a special function register (SFR) to control PWM. [Description of Bits] •...

  • Page 158: Pwm0 Control Register 1 (Pw0Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.2.6 PWM0 Control Register 1 (PW0CON1)      PW0CON1 P0STAT P0FLG P0RUN At reset Address: 0F0A7H Access: R/W Access size: 8 bits Initial value: 40H PW0CON1 is a special function register (SFR) to control PWM0. [Description of Bits] •...

  • Page 159: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.3 Description of Operation The PWM0 counter registers (PW0CH, PW0CL) are set to an operating state (P0STAT is set to “1”) on the first falling edge of the PWM clock (P0CK) that are selected by the PWM0 control register 0 (PW0CON0) when the P0RUN bit of PWM0 control register 1 (PW0CON1) is set to “1”...
  • Page 160 ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM After the P0RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed.

  • Page 161: Specifying Port Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.4 Specifying port registers When you want to make sure the PWM function is working, please check related port registers are specified. See Chapter 22, “Port 4” and Chapter 21, “Port 3” for detail about the port registers. 11.4.1 Functioning P43 (PWM0) as the PWM output Set P43MD1 bit (bit3 of P4MOD1 register) to “1”...

  • Page 162: Functioning P34 (Pwm0) As The Pwm Output

    ML610Q411/ML610Q412 User’s Manual Chapter 11 PWM 11.4.2 Functioning P34 (PWM0) as the PWM output Set P34MD1 bit (bit4 of P3MOD1 register) to “1” and set P34MD0 bit (bit4 of P3MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P34. Reg.

  • Page 163: Watchdog Timer

    Chapter 12 Watchdog Timer...

  • Page 164: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 12 Watchdog Timer Watchdog Timer 12.1 Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period, the watchdog timer requests a WDT interrupt (non-maskable interrupt).

  • Page 165: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 12 Watchdog Timer 12.2 Description of Registers 12.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F00EH Watchdog timer control register WDTCON  0F00FH Watchdog timer mode register WDTMOD FEUL610Q411 12 – 2...

  • Page 166: Watchdog Timer Control Register (Wdtcon)

    ML610Q411/ML610Q412 User’s Manual Chapter 12 Watchdog Timer 12.2.2 Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: R/W Access size: 8 bits Initial value: 00H WDTCON WDP/d0 Initial value WDTCON is a special function register (SFR) to clear the WDT counter. When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0.

  • Page 167: Watchdog Timer Mode Register (Wdtmod)

    ML610Q411/ML610Q412 User’s Manual Chapter 12 Watchdog Timer 12.2.3 Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: R/W Access size: 8 bits Initial value: 02H       WDTMOD WDT1 WDT0 Initial value WDTMOD is a special function register to set the overflow period of the watchdog timer. [Description of Bits] •...

  • Page 168: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 12 Watchdog Timer 12.3 Description of Operation The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" when WDP is "1".
  • Page 169 ML610Q411/ML610Q412 User’s Manual Chapter 12 Watchdog Timer Figure 12-2 shows an example of watchdog timer operation. Program Occurrence of start Low-speed abnormality oscillation start WDTMOD RESET_S WDTMOD setting setting System reset      Data: WDTCON Write WDTP Internal pointer Overflow WDT counter...

  • Page 170: Synchronous Serial Port

    Chapter 13 Synchronous Serial Port...

  • Page 171: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port Synchronous Serial Port 13.1 Overview This LSI includes one channel of the 8/16-bit synchronous serial port (SSIO) and can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable pin. For the input clock, see Chapter 6, “Clock Generation Circuit”.

  • Page 172: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.1.3 List of Pins Pin name Description P40/SIN0 Receive data input. Used for the tertiary function of the P40 and P44 pins. P44/SIN0 P41/SCK0 Synchronous clock input/output. Used for the tertiary function of the P41 and P45 pins. P45/SCK0 P42/SOUT0 Transmit data output.

  • Page 173: List Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.2 Description of Registers 13.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Serial port 0 transmit/receive 0F280H SIO0BUFL 8/16 buffer L SIO0BUF Serial port 0 transmit/receive 0F281H SIO0BUFH buffer H ...

  • Page 174: Serial Port Transmit/Receive Buffers (Sio0Bufl, Sio0Bufh)

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) Address: 0F280H Access: R/W Access size: 8 bits/16 bits Initial value: 00H SIO0BUFL S0B7 S0B6 S0B5 S0B4 S0B3 S0B2 S0B1 S0B0 Initial value Address: 0F281H Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 175: Serial Port Control Register (Sio0Con)

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.2.3 Serial Port Control Register (SIO0CON) Address: 0F282H Access: R/W Access size: 8 bits Initial value: 00H        SIO0CON S0EN Initial value SIO0CON is a special function register (SFR) to control the synchronous serial port. [Description of Bits] •...

  • Page 176: Serial Port Mode Register 0 (Sio0Mod0)

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.2.4 Serial Port Mode Register 0 (SIO0MOD0) Address: 0F284H Access: R/W Access size: 8 bits Initial value: 00H     SIO0MOD0 S0LG S0MD1 S0MD0 S0DIR Initial value SIO0MOD0 is a special function register (SFR) to set mode of the synchronous serial port. [Description of Bits] •...

  • Page 177: Serial Port Mode Register 1 (Sio0Mod1)

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.2.5 Serial Port Mode Register 1 (SIO0MOD1) Address: 0F285H Access: R/W Access size: 8 bits Initial value: 00H     SIO0MOD1 S0CKT S0CK2 S0CK1 S0CK0 Initial value SIO0MOD1 is a special function register (SFR) to set mode of the synchronous serial port. [Description of Bits] •...

  • Page 178: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.3 Description of Operation 13.3.1 Transmit Operation When “1” is written to the S0MD1 bit and “0” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit mode. When transmit data is written to the serial port transmit /receive buffer (SIO0BUFL and H) and the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission starts.

  • Page 179: Receive Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.3.2 Receive Operation When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, reception starts.

  • Page 180: Transmit/Receive Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.3.3 Transmit/Receive Operation When “1” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit/receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission/reception starts.

  • Page 181: Specifying Port Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.4 Specifying port registers When you want to make sure the SSIO function is working, please check related port registers are specified. See Chapter 21, “Port 4” for detail about the port registers. 13.4.1 Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ “Master mode”...

  • Page 182: Functioning P42 (Sout0), P41 (Sck0) And P40 (Sin0) As The Ssio/ "Slave Mode

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.4.2 Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ ”Slave mode” Set P42MD1-P40MD1 bits(bit2-bit0 of P4MOD1 register) to “1” and set P42MD0-P40MD0(bit2-bit0 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P42, P41 and P40. They are the same setting as those in the case of master mode.

  • Page 183: Functioning P46 (Sout0), P45 (Sck0) And P44 (Sin0) As The Ssio/ "Master Mode

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.4.3 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Master mode” Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P46, P45 and P44. Reg.

  • Page 184: Functioning P46 (Sout0), P45 (Sck0) And P44 (Sin0) As The Ssio/ "Slave Mode

    ML610Q411/ML610Q412 User’s Manual Chapter 13 Synchronous Serial Port 13.4.4 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Slave mode” Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P46, P45 and P44. They are the same setting as those in the case of master mode.

  • Page 185: Uart

    Chapter 14 UART...

  • Page 186: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART UART 14.1 Overview This LSI includes 1 channel of UART (Universal Asynchronous Receiver Transmitter) which is an asynchrnous serial interface. For the input clock, see Chapter 6, “Clock Generation Circuit”. The use of UART requires setting of the secondary functions of Port 4. For setting of the secondary functions of Port 4, see Chapter 21, “Port 4”.

  • Page 187: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.2 Description of Registers 14.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F290H UART0 transmit/receive buffer UA0BUF  0F291H UART0 control register UA0CON 0F292H UART0 mode register 0 UA0MOD0 8/16 UA0MOD...

  • Page 188: Uart0 Transmit/Receive Buffer (Ua0Buf)

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.2.2 UART0 Transmit/Receive Buffer (UA0BUF) Address: 0F290H Access: R/W Access size: 8 bits Initial value: 00H UA0BUF U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 Initial value UA0BUF is a special function register (SFR) to store the transmit/receive data of the UART. In transmit mode, write transmission data to UA0BUF.

  • Page 189: Uart0 Control Register (Ua0Con)

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.2.3 UART0 Control Register (UA0CON) Address: 0F291H Access: R/W Access size: 8 bits Initial value: 00H        UA0CON U0EN Initial value UA0CON is a special function register (SFR) to start/stop communication of the UART. [Description of Bits] •...

  • Page 190: Uart0 Mode Register 0 (Ua0Mod0)

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.2.4 UART0 Mode Register 0 (UA0MOD0) Address: 0F292H Access: R/W Access size: 8/16 bits Initial value: 00H UA0MOD0 — — — U0RSEL — U0CK1 U0CK0 U0IO Initial value UA0MOD0 is a special function register (SFR) to set the transfer mode of the UART. [Description of Bits] •...

  • Page 191: Uart0 Mode Register 1 (Ua0Mod1)

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.2.5 UART0 Mode Register 1 (UA0MOD1) Address: 0F293H Access: R/W Access size: 8/16 bits Initial value: 00H UA0MOD1 — U0DIR U0NEG U0STP U0PT1 U0PT0 U0LG1 U0LG0 Initial value UA0MOD1 is a special function register (SFR) to set the transfer mode of the UART. [Description of Bits] •...
  • Page 192 ML610Q411/ML610Q412 User’s Manual Chapter 14 UART • U0DIR (bit 6) The U0DIR bit is used to select LSB first or MSB first in the communication of the UART. U0DIR Description LSB first (initial value) MSB first Note: Always set the UA0MOD1 register while communication is stopped, and do not rewrite it during communication. FEUL610Q411 14 –...

  • Page 193: Uart0 Baud Rate Registers L, H (Ua0Brtl, Ua0Brth)

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.2.6 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) Address: 0F294H Access: R/W Access size: 8/16 bits Initial value: 0FFH UA0BRTL U0BR7 U0BR6 U0BR5 U0BR4 U0BR3 U0BR2 U0BR1 U0BR0 Initial value Address: 0F295H Access: R/W Access size: 8 bits Initial value: 0FH UA0BRTH...

  • Page 194: Uart0 Status Register (Ua0Stat)

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.2.7 UART0 Status Register (UA0STAT) Address: 0F296H Access: R/W Access size: 8 bits Initial value: 00H UA0STAT — — — — U0FUL U0PER U0OER U0FER Initial value UA0STAT is a special function register (SFR) to indicate the state of transmit or receive operation of the UART. When any data is written to UA0STAT, all the flags are initialized to “0”.
  • Page 195 ML610Q411/ML610Q412 User’s Manual Chapter 14 UART • U0FUL (bit 3) The U0FUL bit is used to indicate the state of the transmit/receive buffer of the UART. When transmit data is written in UA0BUF in transmit mode, this bit is set to “1” and when transmit data is transferred to the shift register, this bit is set to “0”.

  • Page 196: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.3 Description of Operation 14.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can be selected as data bit.

  • Page 197: Baud Rate

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.3.2 Baud Rate Baud rates are generated by the baud generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (U0CK1, U0CK0) of the UART0 mode register 0 (UA0MOD0). The count value of the baud rate generator can be set by writing it in the UART0 baud rate register H or L (UA0BRTH, UA0BRTL).

  • Page 198: Transmit Data Direction

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.3.3 Transmit Data Direction Figure 14-4 shows the relationship between the transmit/receive buffer and the transmit/receive data. • Data length: 8 bits LSB reception LSB reception U0B7 U0B6 U0B5 U0B3 U0B2 U0B0 U0B4 U0B1 MSB reception MSB reception •...

  • Page 199: Transmit Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.3.4 Transmit Operation Transmission is started by setting the U0IO bit of the UART0 mode register 0 (UA0MOD0) to “0” to select transmit mode and setting the U0EN bit of the UART0 control register (UA0CON) to “1”. Figure 14-5 shows the operation timing for transmission.
  • Page 200 ML610Q411/ML610Q412 User’s Manual Chapter 14 UART Figure 14-5 Operation Timing in Transmission FEUL610Q411 14 – 15...

  • Page 201: Receive Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.3.5 Receive Operation Reception is started by selecting a receive data input pin using the U0RSEL bit of the UART0 mode register 0 (UA0MOD0), then setting the U0IO bit of UA0MOD0 to “0” to select receive mode, and then setting the U0EN bit of the UART0 control register (UA0CON) to “1”.
  • Page 202 ML610Q411/ML610Q412 User’s Manual Chapter 14 UART Figure 14-6 Operation Timing in Reception FEUL610Q411 14 – 17...

  • Page 203: Specifying Port Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART 14.4 Specifying port registers When you want to make sure the UART function is working, please check related port registers are specified. See Chapter 21, “Port 4” and Chapter 18, “Port 0” for detail about the port registers. 14.4.1 Functioning P43(TXD0) and P42(RXD0) as the UART.

  • Page 204: Functioning P43(Txd0) And P02(Rxd0) As The Uart

    ML610Q411/ML610Q412 User’s Manual Chapter 14 UART Note: The receive pin (RXD) is selected by U0RSEL bit(bit4 of UA0MOD0 register). Reseting the bit to “0” (initial value) selects P02 pin and setting the bit to “1” selects P43 pin. 14.4.2 Functioning P43(TXD0) and P02(RXD0) as the UART. Set P43MD1 bit(bit3 of P4MOD1 register) to “0”...
  • Page 205 ML610Q411/ML610Q412 User’s Manual Chapter 14 UART P02 is an input-only port, so there is no need to specify data direction (i.e. input or output). Data setting to P02C1 bit and P02C0 bit, depend on the application circuit connected to P02. Reg.

  • Page 206: I 2 C Bus Interface

    Chapter 15 C Bus Interface...

  • Page 207: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface C Bus Interface 15.1 Overview This LSI includes 1 channel of I C bus interface (master). The secondary functions of Port 4 are assigned to the I C bus interface data input/output pin and the I C bus interface clock input/output pin.

  • Page 208: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.2 Description of Registers 15.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F2A0H C bus 0 receive register I2C0RD — 0F2A1H C bus 0 slave address register I2C0SA —...

  • Page 209: I 2 C Bus 0 Receive Register (I2C0Rd)

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.2.2 C Bus 0 Receive Register (I2C0RD) Address: 0F2A0H Access: R Access size: 8 bits Initial value: 00H I2C0RD I20R7 I20R6 I20R5 I20R4 I20R3 I20R2 I20R1 I20R0 Initial value I2C0RD is a read-only special function register (SFR) to store receive data. I2C0RD is updataed after completion of each reception.

  • Page 210: I 2 C Bus 0 Slave Address Register (I2C0Sa)

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.2.3 C Bus 0 Slave Address Register (I2C0SA) Address: 0F2A1H Access: R/W Access size: 8 bits Initial value: 00H I2C0SA I20A6 I20A5 I20A4 I20A3 I20A2 I20A1 I20A0 I20RW Initial value I2C0SA is a special function register (SFR) to set the address and the transmit/receive mode of the slave device. [Description of Bits] •...

  • Page 211: I 2 C Bus 0 Transmit Data Register (I2C0Td)

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.2.4 C Bus 0 Transmit Data Register (I2C0TD) Address: 0F2A2H Access: R/W Access size: 8 bits Initial value: 00H I2C0TD I20T7 I20T6 I20T5 I20T4 I20T3 I20T2 I20T1 I20T0 Initial value I2C0TD is a special function register (SFR) to set transmit data. [Description of Bits] •...

  • Page 212: I 2 C Bus 0 Control Register (I2C0Con)

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.2.5 C Bus 0 Control Register (I2C0CON) Address: 0F2A3H Access: R/W Access size: 8 bits Initial value: 00H I2C0CON I20ACT — — — — I20RS I20SP I20ST Initial value I2C0CON is a special function register (SFR) to control transmit and receive operations. [Description of Bits] •...

  • Page 213: I 2 C Bus 0 Mode Register (I2C0Mod)

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.2.6 C Bus 0 Mode Register (I2C0MOD) Address: 0F2A4H Access: R/W Access size: 8 bits Initial value: 00H I2C0MOD — — — I20SYN I20DW1 I20DW0 I20MD I20EN Initial value I2C0MOD is a special function register (SFR) to set operating mode. [Description of Bits] •...

  • Page 214: I 2 C Bus 0 Status Register (I2C0Stat)

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.2.7 C Bus 0 Status Register (I2C0STAT) Address: 0F2A5H Access: R/W Access size: 8 bits Initial value: 00H I2C0STAT — — — — — I20ER I20ACR I20BB Initial value: I2C0STAT is a read-only special function register (SFR) to indicate the state of the I C bus interface.

  • Page 215: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.3 Description of Operation 15.3.1 Communication Operating Mode Communication is started when communication mode is selected by using the I C bus 0 mode register (I2C0MOD), the C function is enabled by using the I20EN bit, a slave address and a data communication direction are set in the I bus 0 slave address register, and “1”...

  • Page 216: Stop Condition

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface When “1” is written to the I20ST bit in the control register setting wait state, the LSI shifts to the data transmit or receive mode. When “1” is written to the I20SP bit, the LSI shifts to the stop condition. When “1” is written to the I20RS bit and I2ST bit, the operation shifts to the repeated start condition.

  • Page 217: Communication Operation Timing

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.3.2 Communication Operation Timing Figures 15-2 to 15-4 show the operation timing and control method for each communication mode. Transmission Reception Start Stop Repeated Start Reception of Transmission of Transmission of condition condition condition...
  • Page 218 ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface Figure 15-5 shows the operation timing and control method when an acknowledgment error occurs. Acknowledgment error Register I2C0SA=”xxxxxxx0B” setting I2C0CON=”01H” I2C0CON=”02H” Value of I2C0SA I2C0INT I20ST I2C0RD Value of I2C0SA I20ACR Figure 15-5 Operation Suspend Timing at Occurrence of Acknowledgment Error When the values of the transmitted bit and the SDA pin do not coincide, the I20ER bit of the I2C bus 0 status register (I2C0STAT) is set to “1”...

  • Page 219: Operation Waveforms

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.3.3 Operation Waveforms Figure 15-7 shows the operation waveforms of the SDA and SCL signals and the I20BB flag. Table 15-1 shows the relationship between communication speeds and HSCLK clock counts. Start condition Repeated condition Stop condition...

  • Page 220: Specifying Port Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 15 I C Bus Interface 15.4 Specifying port registers When you want to make sure the I2C bus interface function is working, please check related port registers are specified. See Chapter 21, “Port 4” for detail about the port registers. 15.4.1 Functioning P41(SCL) and P40(SDA) as the I2C Set P41MD1-P40MD1 bits(bit1-bit0 of P4MOD1 register) to “0”...

  • Page 221: Nmi Pin

    Chapter 16 NMI Pin...

  • Page 222: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 16 NMI Pin NMI Pin 16.1 Overview This LSI includes an input port (NMI) which generates a non-maskable interrupt. For interrupts see Chapter 5, “Interrupts”. 16.1.1 Features • Non-maskable interrupt pin. • Allows selection of an input with a pull-up resistor or a high-impedance input. •...

  • Page 223: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 16 NMI Pin 16.2 Description of Registers 16.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Depends on  0F200H NMI data register NMID pin state  0F201H NMI control register NMICON FEUL610Q411 16 –...

  • Page 224: Nmi Data Register (Nmid)

    ML610Q411/ML610Q412 User’s Manual Chapter 16 NMI Pin 16.2.2 NMI Data Register (NMID) Address: 0F200H Access: R Access size: 8 bits Initial value: Depends on the pin state        NMID Initial value NMID is a read-only special function register (SFR) for reading the NMI pin level. [Description of Bits] •...

  • Page 225: Nmi Control Register (Nmicon)

    ML610Q411/ML610Q412 User’s Manual Chapter 16 NMI Pin 16.2.3 NMI Control Register (NMICON) Address: 0F201H Access: R/W Access size: 8 bits Initial value: 00H        NMICON NMIC Initial value NMICON is a special function register (SFR) to select the input mode of the NMI pin. [Description of Bits] •...

  • Page 226: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 16 NMI Pin 16.3 Description of Operation The non-maskable NMI interrupt (NMIINT) is assigned to the NMI pin. The NMI pin allows selection of an input mode with a pull-up resistor or a high-impedance input mode by using the NMI control register (NMICON).

  • Page 227: Port 0

    Chapter 17 Port 0...

  • Page 228: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 17 Port 0 Port 0 17.1 Overview This LSI includes Port 0 (P00 to P03) which is a 4-bit input port. 17.1.1 Features • All bits support a maskable interrupt function. • Allows selection of interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode, or both-edge interrupt mode for each bit.

  • Page 229: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 17 Port 0 17.2 Description of Registers 17.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Depends  0F204H Port 0 data register on pin status 0F206H Port 0 control register 0 P0CON0 8/16 P0CON...

  • Page 230: Port 0 Data Register (P0D)

    ML610Q411/ML610Q412 User’s Manual Chapter 17 Port 0 17.2.2 Port 0 Data Register (P0D) Address: 0F204H Access: R Access size: 8 bits Initial value: Depends on pin status     P03D P02D P01D P00D Initial value P0D is a special function register (SFR) to only read the pin level of Port 0. [Description of Bits] •...

  • Page 231: Port 0 Control Registers 0, 1 (P0Con0, P0Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 17 Port 0 17.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) Address: 0F206H Access: R/W Access size: 8/16 bits Initial value: 00H     P0CON0 P03C0 P02C0 P01C0 P00C0 Initial value Address: 0F207H Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 232: External Interrupt Control Registers 0, 1 (Exicon0, Exicon1)

    ML610Q411/ML610Q412 User’s Manual Chapter 17 Port 0 17.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1) Address: 0F020H Access: R/W Access size: 8 bits Initial value: 00H     EXICON0 P03E0 P02E0 P01E0 P00E0 Initial value Address: 0F021H Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 233: External Interrupt Control Register 2 (Exicon2)

    ML610Q411/ML610Q412 User’s Manual Chapter 17 Port 0 17.2.5 External Interrupt Control Register 2 (EXICON2) Address: 0F022H Access: R/W Access size: 8 bits Initial value: 00H     EXICON2 P03SM P02SM P01SM P00SM Initial value EXICON2 is a special function register (SFR) to select detection of signal edge for interrupts with or without sampling. [Description of Bits] •...

  • Page 234: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 17 Port 0 17.3 Description of Operation For each pin of Port 0, the setting of the Port 0 control registers 0 and 1 (P0CON0 and P0CON1) allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. High-impedance input mode is selected at system reset.
  • Page 235 ML610Q411/ML610Q412 User’s Manual Chapter 17 Port 0 SYSCLK P0n pin P0nINT Interrupt request QP0n (c) When Both-Edge Interrupt Mode without Sampling is Selected T16KHZ SYSCLK P0n pin P0nINT Interrupt request QP0n n = 0, 1, 2, 3 (d) When Rising-Edge Interrupt Mode with Sampling is Selected Figure 17-2 P00 to P03 Interrupt Generation Timing FEUL610Q411 17 –...
  • Page 236 Chapter 18 Port 1...

  • Page 237: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 18 Port 1 Port 1 18.1 Overview This LSI incorporates a 2-bit input port, Port 1 (P10, P11). Port 1 can have an external clock input pin as a secondary function. For the external clock input, see Chapter 6, “Clock Generation Circuit”. 18.1.1 Features •...

  • Page 238: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 18 Port 1 18.2 Description of Registers 18.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Depends  0F208H Port 1 data register on pin status 0F20AH Port 1 control register 0 P1CON0 8/16 P1CON...

  • Page 239: Port 1 Data Register (P1D)

    ML610Q411/ML610Q412 User’s Manual Chapter 18 Port 1 18.2.2 Port 1 Data Register (P1D) Address: 0F208H Access: R Access size: 8 bits Initial value: Depends on pin status       P11D P10D Initial value P1D is a special function register (SFR) dedicated to read the input level of the Port 1 pin. [Description of Bits] •...

  • Page 240: Port 1 Control Registers 0, 1 (P1Con0, P1Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 18 Port 1 18.2.3 Port 1 Control Registers 0, 1 (P1CON0, P1CON1) Address: 0F20AH Access: R/W Access size: 8/16 bits Initial value: 00H       P1CON0 P11C0 P10C0 Initial value Address: 0F20BH Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 241: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 18 Port 1 18.3 Description of Operation 18.3.1 Input Port Function For each pin of Port 1, one of high-impedance input mode, input mode with a pull-down resistor, and input mode with a pull-up resistor can be selected by setting the Port 1 control registers 0 and 1 (P1CON0 and P1CON1). At system reset, high-impedance input mode is selected as the initial state.
  • Page 242 Chapter 19 Port 2...

  • Page 243: Port2

    ML610Q411/ML610Q412 User’s Manual Chapter 19 Port 2 Port 2 19.1 Overview This LSI includes 3-bit Port 2 (P20 to P22) dedicated to output. Port 2 can output low-speed clock (LSCLK), high-speed output clock (OUTCLK), and melody as a secondary function. For clock output and buzzer 0 (BZ0) output, see Chapter 6, “Clock Generation Circuit”...

  • Page 244: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 19 Port 2 19.2 Description of Registers 19.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Depends  0F210H Port 2 data register on pin status 0F212H Port 2 control register 0 P2CON0 8/16 P2CON...

  • Page 245: Port 2 Data Register (P2D)

    ML610Q411/ML610Q412 User’s Manual Chapter 19 Port 2 19.2.2 Port 2 Data Register (P2D) Address: 0F210H Access: R/W Access size: 8 bits Initial value: 00H      P22D P21D P20D Initial value P2D is a special function register (SFR) to set the output value of Port 2. The value of this register is output to Port 4. The value written to P4D is readable.

  • Page 246: Port 2 Control Registers 0, 1 (P2Con0, P2Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 19 Port 2 19.2.3 Port 2 control registers 0, 1 (P2CON0, P2CON1) Address: 0F212H Access: R/W Access size: 8/16 bits Initial value: 00H      P2CON0 P22C0 P21C0 P20C0 Initial value Address: 0F213H Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 247: Port 2 Mode Register (P2Mod)

    ML610Q411/ML610Q412 User’s Manual Chapter 19 Port 2 19.2.4 Port 2 Mode Register (P2MOD) Address: 0F214H Access: R/W Access size: 8 bits Initial value: 00H      P2MOD P22MD P21MD P20MD Initial value P2MOD is a special function register (SFR) to select the primary function or the secondary function of Port 2 [Description of Bits] •...

  • Page 248: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 19 Port 2 19.3 Description of Operation 19.3.1 Output Port Function For each pin of Port 2, any one of high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, and CMOS output mode can be selected by setting the Port 2 control registers 0 and 1 (P2CON0 and P2CON1).
  • Page 249 Chapter 20 Port 3...

  • Page 250: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 Port 3 20.1 Overview This LSI includes Port 3 (P30 to P35), which is a 6-bit input/output port. This port can also be used as the RC-ADC (channel 0) oscillation pins (IN0, CS0, RS0, RT0, RCT0, RCM) and the PWM output pin in secondary and tertiary modes.

  • Page 251: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 20.1.3 List of Pins Pin name Primary function Secondary function Tertiary function  Oscillation waveform input pin for P30/IN0 Input/output port RC-ADC  Reference capacitor connection P31/CS0 Input/output por pin for RC-ADC Resistor/capacitor sensor P34/RCT0/PWM0 Input/output port connection pin for measurement...

  • Page 252: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 20.2 Description of Registers 20.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F218H Port 3 data register  0F219H Port 3 direction register P3DIR 0F21AH Port 3 control register 0 P3CON0 8/16 P3CON...

  • Page 253: Port 3 Data Register (P3D)

    ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 20.2.2 Port 3 data register (P3D) Address: 0F218H Access: R/W Access size: 8 bits Initial value: 00H   P35D P34D P33D P32D P31D P30D Initial value P3D is a special function register (SFR) to set the value to be output to the Port 3 pin or to read the input level of the Port 3.

  • Page 254: Port 3 Direction Register (P3Dir)

    ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 20.2.3 Port 3 Direction Register (P3DIR) Address: 0F219H Access: R/W Access size: 8 bits Initial value: 00H   P3DIR P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Initial value P3DIR is a special function register (SFR) to select the input/output mode of Port 3. [Description of Bits] •...

  • Page 255: Port 3 Control Registers 0, 1 (P3Con0, P3Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 20.2.4 Port 3 control registers 0, 1 (P3CON0, P3CON1) Address: 0F21AH Access: R/W Access size: 8/16 bits Initial value: 00H   P3CON0 P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Initial value Address: 0F21BH Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 256 ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 When output mode is selected When input mode is selected (P33DIR bit = “0”) (P33DIR bit = “1”) P33C1 P33C0 Description P33 pin: High-impedance output (initial P33 pin: High-impedance input value) P33 pin: P-channel open drain output P33 pin: Input with a pull-down resistor P33 pin: N-channel open drain output P33 pin: Input with a pull-up resistor...

  • Page 257: Port 3 Mode Registers 0, 1 (P3Mod0, P3Mod1)

    ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 20.2.5 Port 3 mode registers 0, 1 (P3MOD0, P3MOD1) Address: 0F21CH Access: R/W Access size: 8/16 bits Initial value: 00H   P3MOD0 P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Initial value Address: 0F21DH Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 258 ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 • P32MD1, P32MD0 (bit 2) The P32MD1 and P32MD0 bits are used to select the primary or secondary function of the P32 pin. P32MD1 P32MD0 Description General-purpose input/output mode (initial value) Reference resistor connection pin for RC-ADC (channel 0) Prohibited Prohibited •...

  • Page 259: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 20 Port 3 20.3 Description of Operation 20.3.1 Input/Output Port Functions For each pin of Port 3, either output or input is selected by setting the Port 3 direction register (P3DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 3 control registers 0 and 1 (P3CON0 and P3CON1).
  • Page 260 Chapter 21 Port 4...

  • Page 261: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 Port 4 21.1 Overview This LSI includes Port 4 (P40 to P47) which is an 8-bit input/output port. This port can have the I2C bus, RC-ADC, synchronous serial port, and PWM output functions as secondary and tertiary functions.

  • Page 262: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 21.1.3 List of Pins Pin name Primary function Secondary function Tertiary function C bus 0 data input/output P40/SDA/SIN0 Input/output port SSIO0 data input pin C bus 0 clock input/output P41/SCL/SCK0 Input/output port SSIO0 clock input/output pin P42/RXD0/SOUT0 Input/output port UART0 data input pin...

  • Page 263: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 21.2 Description of Registers 21.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F220H Port 4 data register  0F221H Port 4 direction register P4DIR 0F222H Port 4 control register 0 P4CON0 8/16 P4CON...
  • Page 264 ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 21.2.2 Port 4 Data Register (P4D) Address: 0F220H Access: R/W Access size: 8 bits Initial value: 00H P47D P46D P45D P44D P43D P42D P41D P40D Initial value P4D is a special function register (SFR) to set the value to be output to the Port 4 pin or to read the input level of the Port 4.
  • Page 265 ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 21.2.3 Port 4 Direction Register (P4DIR) Address: 0F221H Access: R/W Access size: 8 bits Initial value: 00H P4DIR P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Initial value P4DIR is a special function register (SFR) to select the input/output mode of Port 4. [Description of Bits] •...

  • Page 266: Port 4 Control Registers 0, 1 (P4Con0, P4Con1)

    ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 21.2.4 0, 1 (P4CON0, P4CON1) Port 4 Control Registers Address: 0F222H Access: R/W Access size: 8/16 bits Initial value: 00H P4CON0 P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Initial value Address: 0F223H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 267 ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 When output mode is selected When input mode is selected Setting of P44 pin (P44DIR bit = “0”) (P44DIR bit = “1”) P44C1 P44C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...

  • Page 268: Port 4 Mode Registers 0, 1 (P4Mod0, P4Mod1)

    ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 21.2.5 Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1) Address: 0F224H Access: R/W Access size: 8/16 bits Initial value: 00H P4MOD0 P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Initial value Address: 0F225H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 269 ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 • P44MD1, P44MD0 (bit 4) The P44MD1 and P44MD0 bits are used to select the primary, secondary, or tertiary function of the P44 pin. P44MD1 P44MD0 Description General-purpose input/output mode (initial value) RC oscillation waveform input pin for RC-AD (channel 1) SIO0 data input pin Prohibited •...
  • Page 270 ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 When using RC-ADC as the secondary function, specify each pin be “High-impedance input” even the RC oscillation monitor pin. Pull-up or Pull-down input makes drawing the current. FEUL610Q411 21 – 10...

  • Page 271: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 21 Port 4 21.3 Description of Operation 21.3.1 Input/Output Port Functions For each pin of Port 4, either output or input is selected by setting the Port 4 direction register (P4DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 4 control registers 0 and 1 (P4CON0 and P4CON1).

  • Page 272: Port A

    Chapter 22 Port A...

  • Page 273: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 22 Port A Port A 22.1 Overview ML610Q411 include Port A (PA0 to PA7) which is an 8-bit input/output port. This function is not included in the ML610Q412. 22.1.1 Features • Allows selection of high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output for each bit in output mode.

  • Page 274: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 22 Port A 22.2 Description of Registers 22.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F250H Port A data register  0F251H Port A direction register PADIR 0F252H Port A control register 0 PACON0 8/16 PACON...

  • Page 275: Port A Data Register (Pad)

    ML610Q411/ML610Q412 User’s Manual Chapter 22 Port A 22.2.2 Port A Data Register (PAD) Address: 0F250H Access: R/W Access size: 8 bits Initial value: 00H PA7D PA6D PA5D PA4D PA3D PA2D PA1D PA0D Initial value PAD is a special function register (SFR) to set the value to be output to the Port A pin or to read the input level of the Port A.

  • Page 276: Port A Direction Register (Padir)

    ML610Q411/ML610Q412 User’s Manual Chapter 22 Port A 22.2.3 Port A Direction Register (PADIR) Address: 0F251H Access: R/W Access size: 8 bits Initial value: 00H PADIR PA7DIR PA6DIR PA5DIR PA4DIR PA3DIR PA2DIR PA1DIR PA0DIR Initial value PADIR is a special function register (SFR) to select the input/output mode of Port A. [Description of Bits] •...

  • Page 277: Port A Control Registers 0, 1 (Pacon0, Pacon1)

    ML610Q411/ML610Q412 User’s Manual Chapter 22 Port A 22.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) Address: 0F252H Access: R/W Access size: 8/16 bits Initial value: 00H PACON0 PA7C0 PA6C0 PA5C0 PA4C0 PA3C0 PA2C0 PA1C0 PA0C0 Initial value Address: 0F253H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 278 ML610Q411/ML610Q412 User’s Manual Chapter 22 Port A When output mode is selected When input mode is selected Setting of PA4 pin (PA4DIR bit = “0”) (PA4DIR bit = “1”) PA4C1 PA4C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...

  • Page 279: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 22 Port A 22.3 Description of Operation 22.3.1 Input/Output Port Functions For each pin of Port A, either output or input is selected by setting the Port A direction register (PADIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port A control registers 0 and 1 (PACON0 and PACON1).

  • Page 280: Buzzer

    Chapter 23 Buzzer...

  • Page 281: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 23 Buzzer Buzzer 23.1 Overview This LSI includes one channel of the buzzer driver. To use the buzzer driver, the secondary function of port 2 should be set. For the secondary function of port 2, see Chapter 19, "Port 2".

  • Page 282: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 23 Buzzer 23.2 Description of Registers 23.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F2C0H Buzzer 0 control register MD0CON  0F2C1H Buzzer 0 tempo code register MD0TMP  0F2C2H Buzzer 0 scale code register MD0TON ...

  • Page 283: Buzzer 0 Control Register (Md0Con)

    ML610Q411/ML610Q412 User’s Manual Chapter 23 Buzzer 23.2.2 Buzzer 0 Control Register (MD0CON) Address: 0F2C0H Access: R/W Access size: 8 bits Initial value: 00H        MD0CON M0RUN Initial value MD0CON is a special function register (SFR) to control the buzzer. [Description of Bits] •...

  • Page 284: Buzzer 0 Tempo Code Register (Md0Tmp)

    ML610Q411/ML610Q412 User’s Manual Chapter 23 Buzzer 23.2.3 Buzzer 0 Tempo Code Register (MD0TMP) Address: 0F2C1H Access: R/W Access size: 8 bits Initial value: 00H       MD0TMP M0TM1 M0TM0 Initial value MD0TMP is a special function register (SFR) to select the output mode of a buzzer sound waveform. [Description of Bits] •...

  • Page 285: Buzzer 0 Scale Code Register (Md0Ton)

    ML610Q411/ML610Q412 User’s Manual Chapter 23 Buzzer 23.2.4 Buzzer 0 Scale Code Register (MD0TON) Address: 0F2C2H Access: R/W Access size: 8 bits Initial value: 00H      MD0TON M0TN2 M0TN1 M0TN0 Initial value MD0TON is a special function register (SFR) to select a buzzer output frequency. [Description of Bits] •...

  • Page 286: Buzzer 0 Tone Length Code Register (Md0Len)

    ML610Q411/ML610Q412 User’s Manual Chapter 23 Buzzer 23.2.5 Buzzer 0 Tone Length Code Register (MD0LEN) Address: 0F2C3H Access: R/W Access size: 8 bits Initial value: 00H     MD0LEN M0LN3 M0LN2 M0LN1 M0LN0 Initial value MD0LEN is a special function register (SFR) to select a buzzer output duty. [Description of Bits] •...

  • Page 287: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 23 Buzzer 23.3 Description of Operation 23.3.1 Operations of Buzzer Output A buzzer sound is output in the following procedure. (1) Select a buzzer output mode using the buzzer 0 tempo code register (MD0TMP). (2) Select a duty of the High level width of the buzzer output waveform using the buzzer 0 tone length code register (MD0LEN).

  • Page 288: Specifying Port Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 23 Buzzer 23.4 Specifying port registers When you want to make sure the Buzzer function is working, please check related port registers are specified. See Chapter 19, “Port 2” for detail about the port registers. 23.4.1 Functioning P22 (MD0) as the Buzzer output Set P22MD bit (bit0 of P2MOD register) to “1”...

  • Page 289: Rc Oscillation Type A/D Converter

    Chapter 24 RC Oscillation Type A/D Converter...

  • Page 290: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter RC Oscillation Type A/D Converter 24.1 Overview This LSI has a built-in 2-channel RC oscillation type A/D converter (RC-ADC). The RC-ADC converts resistance values or capacitance values to digital values by counting the oscillator clock whose frequency changes according to the resistor or capacitor connected to the RC oscillator circuits.

  • Page 291: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.1.3 List of Pins Pin name Description Channel 0 oscillation input pin. P30/IN0 Used for the secondary function of the P30 pin. Channel 0 reference capacitor connection pin. P31/CS0 Used for the secondary function of the P31 pin. Pin for connection with a resistive/capacitive sensor for measurement on P34/RCT0 Channel 0.

  • Page 292: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2 Description of Registers 24.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value RC-ADC Counter A register 0 0F300H RADCA0 — RC-ADC Counter A register 1 0F301H RADCA1 —...

  • Page 293: Rc-Adc Counter A Registers (Radca0-2)

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.2 RC-ADC Counter A Registers (RADCA0–2) Address: 0F300H Access: R/W Access size: 8 bits Initial value: 00H RADCA0 RAA7 RAA6 RAA5 RAA4 RAA3 RAA2 RAA1 RAA0 Initial value Address: 0F301H Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 294: Rc-Adc Counter B Registers (Radcb0-2)

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.3 RC-ADC Counter B Registers (RADCB0–2) Address:0F304H Access: R/W Access size: 8 bits Initial value: 00H RADCB0 RAB7 RAB6 RAB5 RAB4 RAB3 RAB2 RAB1 RAB0 Initial value Address:0F305H Access: R/W Access size: 8 bits Initial value: 00H RADCB1...

  • Page 295: Rc-Adc Mode Register (Radmod)

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.4 RC-ADC Mode Register (RADMOD) Address: 0F308H Access: R/W Access size: 8 bits Initial value: 00H RADMOD RACK2 RACK1 RACK0 RADI Initial value RADMOD is a special function register (SFR) used to select an A/D conversion mode of the RC-ADC. [Description of Bits] •...

  • Page 296: Rc-Adc Control Register (Radcon)

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.5 RC-ADC Control Register (RADCON) Address: 0F309H Access: R/W Access size: 8 bits Initial value: 00H RADCON — — — — — — — RARUN Initial value RADCON is a special function register (SFR) used to control A/D conversion operation of the RC-ADC. [Description of Bits] •...

  • Page 297: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.3 Description of Operation Counter A (RADCA0–2) is a 24-bit binary counter for counting the base clock (BSCLK), which is used as the standard of time. Counter A can count up to 0FFFFFFH. Counter B (RADCB0–2) is a 24-bit binary counter for counting the oscillator clock (RCCLK) of the RC oscillator circuits.
  • Page 298 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter In Table 24-1, mode No.0 and mode No.7 are modes where external clocks to be input to the IN0 or IN1 pin are used for measurement with the RC oscillator circuit stopped. As shown in Table 24-1, the two oscillator circuits, RCOSC0 and RCOSC1, are so specified that they cannot operate concurrenty in order to prevent interference in oscillation from occurring when they oscillate concurrently.
  • Page 299 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter Figures 24-2 to 24-5 show the oscillator circuit configurations, the modes of oscillation for each configuration, and the OM3–0 bit settings. RCT0 Mode of oscillation Oscillates with the reference resistor RS0 and CS0 Oscillates with the sensor RT0 and CS0 Figure 24-2 When RCOSC0 Is Used for Measurement with One Resistive Sensor...
  • Page 300 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter Mode of oscillation Oscillates with the reference resistor RS1 and CS1 Oscillates with the sensor RT1 and CS1 Figure 24-5 When RCOSC1 Is Used for Measurement with One Resistive Sensor 24.3.2 Counter A/Counter B Reference Modes There are the following two modes of RC-ADC conversion operation:...
  • Page 301 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter Counter A starts counting of the base clock (BSCLK) when RARUN is set to “1” and the RCON signal (signal synchronized with the fall of the base clock) is set to “1”. When Counter A overflows, the RARUN bit is automatically reset to “0”...
  • Page 302 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter (2) Operation in Counter B reference mode Figure 24-7 shows the operation timing in Counter B reference mode. Following is an example of operation procedure in Counter B reference mode: ...

  • Page 303: Counter A/Counter B Reference Modes

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter   RARUN BSCLK BSCLK RCON  Counter A 000000H nA1 – 3 nA1 – 2 nA1 – 1 000001H 000002H 000003H nA1t BSCLK RCCLK RC oscillator circuit Input waveform IN0/IN1 RCCLK ...

  • Page 304: Example Of Use Of Rc Oscillation Type A/D Converter

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.3.3 Example of Use of RC Oscillation Type A/D Converter This section describes the method of performing A/D conversion for sensor values in Counter A and B reference modes by taking temperature measurement by a thermistor as an example. Figure 24-8 shows the configuration of 1-thermistor RC oscillator circuit using RCOSC0.
  • Page 305 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter To convert from an RT0 value to a digital value, the ratio is used between a) the oscillation frequency by the thermistor connected to the RT0 pin and the capacitor connected to the CS0 pin and b) the oscillation frequency by the reference resistor (which ideally should have no temperature characteristics) connected to the RS0 pin and the capacitor connected to the CS0 pin.
  • Page 306 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter Figure 24-14 shows, as an example of method, a timing diagram of one cycle of conversion from analog value RT0 to a digital value, that is, A/D conversion. Basically, one A/D conversion cycle must consist of two steps, as shown in Figure 24-14. The reason for requiring two steps is that the reference resistor and the thermistor must first be oscillated separately and then the ratio between the oscillation frequencies of them is used, as described above.
  • Page 307 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter A/D conversion procedure is explained below by taking Figure 24-14 as an example. <First Step> <Second Step>  Base clock 32.768 kHz BSCLK   RADMOD (bits 4–0)   RADCON 01H (ERAD=1) 01H (ERAD=1)
  • Page 308 ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter <First Step>  Set the base clock to 32.768 kHz. (Write “00H” in FCON0.)  Preset “1000000H – nA0” in Counter A.  Preset “000000H” in Counter B.  Write “01H” in RADMOD to select Counter A reference mode and the oscillation mode that uses reference resistance RS0.

  • Page 309: Monitoring Rc Oscillation

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter where t (RS0) is the oscillator clock period by reference resistor RS0 and t (RT0) the oscillator clock period RCCLK RCCLK by thermistor RT0. RC”, t Since the oscillation period is expressed by “t (RS0) and t (RT0) are expressed by the RCCLK...

  • Page 310: Specifying Port Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.4 Specifying port registers When you want to make sure the RC-ADC function is working, please check related port registers are specified. See Chapter 20, “Port 3” and Chapter 21, “Port 4” for detail about the port registers. 24.4.1 Functioning P35(RCM), P34(RCT0), P33(RT0), P32(RS0), P31(CS0) and P30(IN0) as the RC-ADC(Ch0)

  • Page 311: Functioning P47(Rt1), P46(Rs1), P45(Cs1) And P44(In1) As The Rc-Adc(Ch1)

    ML610Q411/ML610Q412 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.4.2 Functioning P47(RT1), P46(RS1), P45(CS1) and P44(IN1) as the RC-ADC(Ch1) Set P47MD1-P44MD1 bits(bit7-bit4 of P4MOD1 register) to “0” and set P47MD0-P44MD0(bit7-bit4 of P4MOD0 register) to “1”, for specifying the RC-ADC as the secondary function of P47, P46, P45 and P44. Reg.

  • Page 312: Successive Approximation Type A/D Converter

    Chapter 25 Successive Approximation Type A/D Converter...

  • Page 313: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter Successive Approximation Type A/D Converter 25.1 Overview This LSI has a built-in 2-channel successive approximation type A/D converter (SA-ADC). 25.1.1 Features • Built-in sample/hold 12-bit successive approximation type A-D converter, which enables channel selection from 2 channels 25.1.2 Configuration...

  • Page 314: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.1.3 List of Pins Pin name Description Positive power supply pin for the successive approximation type  A/D converter Reference power supply pin for the successive approximation type  A/D converter Negative power supply pin for the successive approximation type ...

  • Page 315: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2 Description of Registers 25.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F2D0H SA-ADC result register 0L SADR0L 8/16 SADR0 0F2D1H SA-ADC result register 0H SADR0H 0F2D2H SA-ADC result register 1L...

  • Page 316: Sa-Adc Result Register 0L (Sadr0L)

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.2 SA-ADC Result Register 0L (SADR0L) Address: 0F2D0H Access: R Access size: 8/16 bits Initial value: 00H     SADR0L SAR03 SAR02 SAR01 SAR00 Initial value SADR0L is a special function register (SFR) used to store SA-ADC conversion results on channel 0. SADR0L is updated after A/D conversion.

  • Page 317: Sa-Adc Result Register 1L (Sadr1L)

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.4 SA-ADC Result Register 1L (SADR1L) Address: 0F2D2H Access: R Access size: 8/16 bits Initial value: 00H     SADR1L SAR13 SAR12 SAR11 SAR10 Initial value SADR1L is a special function register (SFR) used to store SA-ADC conversion results on channel 1. SADR1L is updated after A/D conversion.

  • Page 318: Sa-Adc Control Register 0 (Sadcon0)

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.6 SA-ADC Control Register 0 (SADCON0) Address: 0F2F0H Access: R/W Access size: 8/16 bits Initial value: 02H        SADCON0 SALP Initial value SADCON0 is a special function register (SFR) used to control the operation of the SA-ADC. [Description of Bits] •...

  • Page 319: Sa-Adc Control Register 1 (Sadcon1)

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.7 SA-ADC Control Register 1 (SADCON1) Address: 0F2F1H Access: R/W Access size: 8 bits Initial value: 00H        SADCON1 SARUN Initial value SADCON1 is a special function register (SFR) used to control the operation of the SA-ADC. [Description of Bits] •...

  • Page 320: Sa-Adc Mode Register 0 (Sadmod0)

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.8 SA-ADC Mode Register 0 (SADMOD0) Address: 0F2F2H Access: R/W Access size: 8 bits Initial value: 00H       SADMOD0 SACH1 SACH0 Initial value SADMOD0 is a special function register (SFR) used to choose A/D conversion channel(s). [Description of Bits] •...

  • Page 321: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.3 Description of Operation 25.3.1 Settings of A/D Conversion Channels According to the setting of SA-ADC mode register 0 (SADMOD0), A/D conversion is performed as shown below and A/D conversion results are stored in the SA-ADC result register. SA-ADC mode register 0 SA-ADC result register...

  • Page 322: Operation Of The Successive Approximation A/D Converter

    ML610Q411/ML610Q412 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.3.2 Operation of the Successive Approximation A/D Converter 1. Before starting SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillator settles. 2. Set the SA-ADC mode register 0 (SADMOD0). 3.

  • Page 323: Lcd Drivers

    Chapter 26 LCD Drivers...

  • Page 324: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers LCD Drivers 26.1 Overview This LSI includes LCD drivers that display the contents that are set in the display register. The LCD drivers handle the LCD display functions with three blocks. 1. Display registers 2.

  • Page 325: Configuration Of The Lcd Drivers

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.1.2 Configuration of the LCD Drivers Figure 26-2 shows the configuration of the LCD drivers and the bias generation circuit. (*1) SEG0 SEG35 COM0 COM4 Common Segment Bias generation circuit drivers drivers Regulated power supply circuit Voltage...

  • Page 326: Configuration Of The Bias Generation Circuit

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.1.3 Configuration of the Bias Generation Circuit The bias generation circuit generates LCD drive voltages (V to V by multiplying the voltage (V ) generated by the voltage regulator with the capacitors (C When the BSON bit of the bias circuit control register (BIASCON) is set to “1”, the bias generation circuit starts operation.

  • Page 327: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.1.4 List of Pins Pin name Description  Power supply pin for LCD bias (internally generated)  Power supply pin for LCD bias (internally generated)  Power supply pin for LCD bias (internally generated) ...
  • Page 328 ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers Pin name Description SEG36 LCD segment pin SEG37 LCD segment pin SEG38 LCD segment pin SEG39 LCD segment pin SEG40 LCD segment pin SEG41 LCD segment pin SEG42 LCD segment pin SEG43 LCD segment pin SEG44 LCD segment pin FEUL610Q411...

  • Page 329: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.2 Description of Registers 26.2.1 List of Registers Symbol Address Name Symbol (Byte) Size Initial value (Word)  0F0F0H Bias circuit control register BIASCON  0F0F1H Display contrast register DSPCNT  0F0F2H Display mode register 0 DSPMOD0 8/16 ...

  • Page 330: Bias Circuit Control Register 0 (Biascon)

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.2.2 Bias Circuit Control Register 0 (BIASCON) Address: 0F0F0H Access: R/W Access size: 8 bits Initial value: 08H     BIASCON BSN2 BSN1 BSN0 BSON Initial value BIASCON is a special function register (SFR) to control the bias generation circuit. [Description of Bits] •...

  • Page 331: Display Control Register (Dspcnt)

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.2.3 Display Control Register (DSPCNT) Address: 0F0F1H Access: R/W Access size: 8 bits Initial value: 00H    DSPCNT LCN4 LCN3 LCN2 LCN1 LCN0 Initial value DSPCNT is a special function register (SFR) to adjust the contrast of display (32 steps). For the setting value of DSPCNT and the LCD drive voltages (V ), see Appendix C, “Electrical Characteristics”.

  • Page 332: Display Mode Register 0 (Dspmod0)

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.2.4 Display Mode Register 0 (DSPMOD0) Address: 0F0F2H Access: R/W Access size: 8/16 bits Initial value: 00H     DSPMOD0 FRM1 FRM0 DUTY1 DUTY0 Initial value DSPMOD0 is a special function register (SFR) to control the display mode of the LCD drivers. [Description of Bits] •...

  • Page 333: Display Control Register (Dspcon)

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.2.5 Display Control Register (DSPCON) Address: 0F0F4H Access: R/W Access size: 8 bits Initial value: 00H       DSPCON LMD1 LMD0 Initial value DSPCON is a special function register (SFR) to control the LCD drivers. [Description of Bits] •...

  • Page 334: Display Registers (Dspr00 To Dspr23 Or Dspr00 To Dspr2B)

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.2.6 Display Registers (DSPR00 to DSPR23 or DSPR00 to DSPR2B) Address: 0F100H to 0F123H (ML610Q411) : 0F100H to 0F12BH (ML610Q412) Access: R/W Access size: 8 bits Initial value: Undefined     DSPRxx Initial value DSPRxx (xx = 00 to 2B) are special function registers (SFRs) to store display data.
  • Page 335 ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers Table 26-4 Display Registers Symbol Address Segment bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DSPR00 0F100H SEG0 DSPR01 0F101H SEG1 DSPR02 0F102H SEG2 DSPR03 0F103H SEG3 DSPR04 0F104H SEG4 DSPR05 0F105H SEG5 DSPR06 0F106H SEG6...

  • Page 336: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.3 Description of Operation 26.3.1 Operation of LCD Drivers and Bias Generation Circuit Figure 26-4 shows the operation of the LCD drivers and the bias generation circuit. Reset RESET_N BIASCON.BSON LCD bias voltage Generation of LCD bias voltage to V BIAS activation time (T...
  • Page 337 ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.3.2 Display Registers Segment Map Figure 26-5 shows the display registers segment map. DSPR23[3] DSPR22[3] DSPR01[3] DSPR00[3] COM3 DSPR23[2] DSPR22[2] COM2 DSPR01[2] DSPR00[2] DSPR23[1] DSPR22[1] DSPR01[1] DSPR00[1] COM1 DSPR23[0] DSPR22[0] DSPR01[0] DSPR00[0] COM0 ML610Q411 DSPR2B[3] DSPR2A[3]...

  • Page 338: Common Output Waveforms

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.3.3 Common Output Waveforms Figure 26-6 shows the common output waveforms for 1/4 duty and 1/3 bias. Frame Frequency 64Hz/73Hz/85Hz/102Hz COM0 COM1 COM2 COM3 Figure 26-6 Common Output Waveforms for 1/4 Duty and 1/3 Bias FEUL610Q411 26 –...

  • Page 339: Segment Output Waveform

    ML610Q411/ML610Q412 User’s Manual Chapter 26 LCD Drivers 26.3.4 Segment Output Waveform Figure 26-7 shows the segment output waveforms for 1/4 duty and 1/3 bias. Frame Frequency 64Hz/73Hz/85Hz/102Hz Data SEGn Data SEGn Data SEGn Data SEGn ・ ・ ・ ・ ・ ・...

  • Page 340: Battery Level Detector

    Chapter 27 Battery Level Detector...

  • Page 341: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 27 Battery Level Detector Battery Level Detector 27.1 Overview This LSI includes a Battery Level Detector (BLD). 16 levels of threshold voltages can be selected by setting Battery Level Detector control register 0 (BLDCON0). 27.1.1 Features •...

  • Page 342: Description Of Registers

    ML610Q411/ML610Q412 User’s Manual Chapter 27 Battery Level Detector 27.2 Description of Registers 27.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Battery Level Detector control register 0F0D0H BLDCON0 8/16 BLDCON Battery Level Detector control register 0F0D1H BLDCON1 FEUL610Q411 27 –...

  • Page 343: Battery Level Detector Control Register 0 (Bldcon0)

    ML610Q411/ML610Q412 User’s Manual Chapter 27 Battery Level Detector 27.2.2 Battery Level Detector Control Register 0 (BLDCON0) Address: 0F0D0H Access: R/W Access size: 8 bits Initial value: 00H     BLDCON0 Initial value BLDCON0 is a special function register (SFR) to control the Battery Level Detector [Description of Bits] •...

  • Page 344: Battery Level Detector Control Register 1 (Bldcon1)

    ML610Q411/ML610Q412 User’s Manual Chapter 27 Battery Level Detector 27.2.3 Battery Level Detector Control Register 1 (BLDCON1) Address: 0F0D1H Access: R/W Access size: 8 bits Initial value: 00H       BLDCON1 BLDF ENBL Initial value BLDCON1 is a special function register (SFR) to control the Battery Level Detector. [Description of Bits] •...

  • Page 345: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 27 Battery Level Detector 27.3 Description of Operation 27.3.1 Threshold Voltage The threshold voltage (VCMP) is selected by setting the bits of BLDCON0. Table 27-1 shows the threshold voltages and the accuracy. Table 27-1 Threshold Voltages and Accuracy BLDCON0 Threshold voltage Accuracy...

  • Page 346: Operation Of Battery Level Detector

    ML610Q411/ML610Q412 User’s Manual Chapter 27 Battery Level Detector 27.3.2 Operation of Battery Level Detector Activation (ON) and deactivation (OFF) of the Battery Level Detector are controlled by setting the ENBL bit of the Battery Level Detector control register (BLDCON1), and the result of the comparison of the power supply voltage (VDD) to the threshold voltage is output to the BLDF bit of BLDCON1.

  • Page 347: Power Supply Circuit

    Chapter 28 Power Supply Circuit...

  • Page 348: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 28 Power Supply Circuit Power Supply Circuit 28.1 Overview This LSI includes a regulated power supply for the internal logic (VRL) and a regulated power supply for low-speed oscillation (VRX). The VRL outputs the operating voltage, V , of the internal logic, program memory, RAM, etc.

  • Page 349: List Of Pins

    ML610Q411/ML610Q412 User’s Manual Chapter 28 Power Supply Circuit 28.1.3 List of Pins Pin name Description  Positive power supply pin for the internal logic circuits  Positive power supply pin for low-speed oscillation FEUL610Q411 28 – 2...

  • Page 350: Description Of Operation

    ML610Q411/ML610Q412 User’s Manual Chapter 28 Power Supply Circuit 28.2 Description of Operation and V become approx. 1.2 V at a system reset. becomes approx. 0.6 V (Typ.) after 4096 low-speed oscillation clock (XTCLK) pulses are counted after the system reset is released. As a result of release of STOP mode (generation of external interrupt), V becomes approx.

  • Page 351: On-Chip Debug Function

    Chapter 29 On-Chip Debug Function...

  • Page 352: Overview

    ML610Q411/ML610Q412 User’s Manual Chapter 29 On-Chip Debug Function On-Chip Debug Function 29.1 Overview This LSI has an on-chip debug function allowing Flash memory rewriting. The on-chip debug emulator (uEASE) is connected to this LSI to perform the on-chip debug function. 29.2 Method of Connecting to On-Chip Debug Emulator Figure 29-1 shows connection to the on-chip debug emulator (uEASE).

  • Page 353: Flash Memory Rewrite Function

    ML610Q411/ML610Q412 User’s Manual Chapter 29 On-Chip Debug Function 29.3 Flash Memory Rewrite Function Flash memory erase/write can be performed with the the memory mounted on board by using the commands from the on-chip debug emulator (uEASE). For more details on the on-chip debug emulator, see “uEASE User’s Manual”. Table 29-2 shows the Flash memory rewrite functions.

  • Page 354: Appendixes

    Appendixes...

  • Page 355: Appendix A Registers

    ML610Q411/ML610Q412 User’s Manual Appendix A Registers Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value  0F000H Data segment register  0F001H Reset status register RSTAT Undefined 0F002H Frequency control register 0 FCON0 8/16 FCON 0F003H Frequency control register 1 FCON1 ...
  • Page 356 ML610Q411/ML610Q412 User’s Manual Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value 0F03AH Timer control register 0 TM2CON0 8/16 TM2CON 0F03BH Timer 2 control register 1 TM2CON1 0F03CH Timer 3 data register TM3D 8/16 0FFH TM3DC 0F03DH Timer 3 counter register TM3C 0F03EH...
  • Page 357 ML610Q411/ML610Q412 User’s Manual Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value  0F117H Display register 17 DSPR17  0F118H Display register 18 DSPR18  0F119H Display register 19 DSPR19  0F11AH Display register 1A DSPR1A  0F11BH Display register 1B DSPR1B...
  • Page 358 ML610Q411/ML610Q412 User’s Manual Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value 0F281H Serial port 0 transmit/receive buffer H SIO0BUFH  0F282H Serial port 0 control register SIO0CON 0F284H Serial port 0 mode register 0 SIO0MOD0 8/16 SIO0MOD 0F285H Serial port 0 mode register 1...

  • Page 359: Appendix B Package Dimensions

    The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
  • Page 360 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics ABSOLUTE MAXIMUM RATINGS = AV = 0V) Parameter Symbol Condition Rating Unit −0.3 to +4.6 Power supply voltage 1 Ta = 25°C −0.3 to +4.6 Power supply voltage 2 Ta = 25°C −0.3 to +9.5 Power supply voltage 3...

  • Page 361: Appendix C Electrical Characteristics

    ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics CLOCK GENERATION CIRCUIT OPERATING CONDITIONS = 0V) Rating Parameter Symbol Condition Unit Min. Typ. Max. Low-speed crystal oscillation    32.768k frequency Recommended equivalent series    Ω resistance value of low-speed crystal oscillation =6pF of ...
  • Page 362 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics DC CHARACTERISTICS (1/5) = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, = 1.1 to 3.6V, AV = 2.2 to 3.6V, V = AV unless otherwise specified) (1/5) Rating Measuring Parameter...
  • Page 363 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics DC CHARACTERISTICS (2/5) = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, = 1.1 to 3.6V, AV = 2.2 to 3.6V, V = AV unless otherwise specified) (2/5) Rating Measuring Parameter...
  • Page 364 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics DC CHARACTERISTICS (3/5) = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, = 1.1 to 3.6V, AV = 2.2 to 3.6V, V = AV unless otherwise specified) (3/5) Rating Measuring Parameter...
  • Page 365 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics CPU: In RC 500kHz operating state.*  Ta= 25°C 0.５ LCD and BIAS circuits: Supply current 6 IDD6 Operating. * A/D: In operating state.   0.６ = AV = 3.0V : When the CPU operating rate is 100% (No HALT state). : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx.
  • Page 366 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics  IIH1 VIH1 = V Input current 1 −600 −300 = 1.3 to 3.6V (RESET_N) IIL1 VIL1 = V −600 −300 = 1.1 to 3.6V = 1.3 to 3.6V Input current 1 IIH1 VIH1 = V = 1.1 to 3.6V (TEST)
  • Page 367 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics Input pin capacitance (NMI) f = 10kHz (P00–P03)    = 50mV (P10–P11) Ta = 25°C (P30–P35) (P40–P47) (PA0–PA7) *1: ML610Q411 HYSTERESIS WIDTH ∆V Input signal Internal signal FEUL610Q411 C – 8...
  • Page 368 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics MEASURING CIRCUITS MEASURING CIRCUIT 1 32.768kHz crystal P10/OSC0 1µF 1µF 0.1µF 0.1µF 1µF 1µF 32.768kHz crystal: C-001R (Epson Toyocom) MEASURING CIRCUIT 2 (*2) (*1) (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins.
  • Page 369 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics MEASURING CIRCUIT 4 (*3) *3: Measured at the specified output pins. MEASURING CIRCUIT 5 (*1) *1: Input logic circuit to determine the specified measuring conditions. FEUL610Q411 C – 10...
  • Page 370 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics AC CHARACTERISTICS (External Interrupt) = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, = 1.1 to 3.6V, AV = 2.2 to 3.6V, V = AV unless otherwise specified) Rating Parameter Symbol...
  • Page 371 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics AC CHARACTERISTICS (Synchronous Serial Port) = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, = 1.3 to 3.6V, AV = 2.2 to 3.6V, V = AV unless otherwise specified) Rating Parameter Symbol...
  • Page 372 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics AC CHARACTERISTICS (I C Bus Interface: Standard Mode) = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, = 1.8 to 3.6V, AV = 2.2 to 3.6V, V = AV unless otherwise specified) Rating...
  • Page 373 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics AC CHARACTERISTICS (RC Oscillation A/D Converter) = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, = 1.3 to 3.6V, AV = 2.2 to 3.6V, V = AV unless otherwise specified) Rating Parameter...
  • Page 374 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. - When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal.
  • Page 375 ML610Q411/ML610Q412 User’s Manual Appendix C Electrical Characteristics coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. - When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal.

  • Page 376: Appendix D Application Circuit Example

    ML610Q411/ML610Q412 User’s Manual Appendix D Application Circuit Example Appendix D Application Circuit Example 3.0V uEASE COM0-3 SEG0~35(ML610Q411) UVDD_O SEG0~43(ML610Q412) RESET_N P00/CAP0 RESET_N P01/CAP1 TEST TEST P30/IN0 CVR0 ML610Q411 P31/CS0 P32/RS0 P33/RT0 P34/RCT0 ML610Q412 P35/RCM P44/IN1 CVR1 P45/CS1 P46/RS1 P47/RT1 P42 (Output) EN VDD ML8511 AIN0...

  • Page 377: Appendix E Check List

    ML610Q411/ML610Q412 User’s Manual Appendix E Check List Appendix E Check List This Check List has notes to prevent commonly-made programming mistakes and frequently overlooked or misunderstood hardware features of the MCU. Check each note listed up chapter by chapter while coding the program or evaluating it using the MCU.
  • Page 378 ML610Q411/ML610Q412 User’s Manual Appendix E Check List Chapter 5 Interrupt • Unused interrupt vector table [ ] Please define all unused interrupt vector tables for fail safe. • Non-maskable interrupt [ ] The watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT) are non-maskable interrupts that do not depend on MIE flag(Refer to Section 5.2.9.
  • Page 379 ML610Q411/ML610Q412 User’s Manual Appendix E Check List Chapter 13 SSIO • Used pin [ ] P40(SIN0), P41(SCK0) and P42(SOUT0) are used, or P44(SIN0), P45(SCK0) and P46(SOUT0) are used. • Port 2 Function [ ] Specify the 2 Function for the port (Refer to Section 13.4. in the user’s manual) Chapter 14 UART •...
  • Page 380 ML610Q411/ML610Q412 User’s Manual Appendix E Check List Chapter 25 Successive Approximation type A/D converter • Operating conditions [ ] Please confirm the operating voltage and the clock frequency. =1.3V~3.6V (HSCLK=375KHz~625KHz）, AV =2.2V~3.6V • Others [ ] Use the A/D converter when the HSCLK is oscillating. [ ] Do not set SARUN bit of SADCON1 register to “1”...

  • Page 381: Revision History

    Revision History...
  • Page 382 ML610Q411/ML610Q412 User’s Manual Revision History Revision History Page Document No. Date Description Previous Current Edition Edition FEUL610Q411-01 May 1, 2010 – – Formaly edition 1.0 1-3, 1-4, 1-3, 1-4, 3-1, 3-2, 3-1, 3-2, Add the explanation of ML610Q411PC. 3-3, 4-9, 3-3, 4-9, FEUL610Q411-02 Mar.
  • Page 383 ML610Q411/ML610Q412 User’s Manual Revision History Change from "Shipment" to "Product name － Supported Function" Add the internal loading capacitance of the low-speed clock generation circuit. FEUL610Q411-04 Apr.15,2015 Add notes of the case that RC-ADC is stopped by 24-7 software during A / D conversion. Add Clock Generation Circuit Operating Conditions.

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