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Rohm LAPIS ML620Q150A Series User Manual

16-bit microcontroller
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Table of Contents

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FEUL620Q150A-02
ML620Q150A Series
User's Manual
16-bit Microcontroller
Rev.2
Issue Date: May.25, 2015

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Summary of Contents for Rohm LAPIS ML620Q150A Series

  • Page 1 FEUL620Q150A-02 ML620Q150A Series User’s Manual 16-bit Microcontroller Rev.2 Issue Date: May.25, 2015...
  • Page 2 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
  • Page 3 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual  Preface This manual describes the operation of the hardware of the 16-bit microcontroller ML620Q150A Series. The following manuals are also available. Read them as necessary. nX-U16/100 Core Instruction Manual Description on the basic architecture and the each instruction of the nX-U16/100 Core MACU8 Assembler Package User’s Manual Description on the method of operating the relocatable assembler, the linker, the librarian,...
  • Page 4 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual  Notation Classification Notation Description ♦ Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F Indicates a binary number; “b” may be omitted. x: A value 0 or 1 ♦...

  • Page 5: Table Of Contents

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents Contents Chapter 1 Overview .................................1-1 Features ...............................1-1 Configuration of Functional Blocks ......................1-4 1.2.1 Block Diagram of ML620Q151A/ML620Q152A/ML620Q153A(TQFP48)........1-4 1.2.2 Block Diagram of ML620Q154A/ML620Q155A/ML620Q156A(TQFP52)........1-5 1.2.3 Block Diagram of ML620Q157A/ML620Q158A/ML620Q159A(QFP64) ..........1-6 Pins ................................1-7 1.3.1 Pin Layout..............................1-8 1.3.2 List of Pins............................1-10 1.3.3 Pin Description ............................1-14 1.3.4...
  • Page 6   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents 4.3.3 STOP Mode ............................4-12 4.3.3.1 STOP Mode When the CPU runs with Low-Speed Clock.............4-12 4.3.3.2 STOP Mode When the CPU runs with High-Speed Clock............4-13 4.3.3.3 Note on Return Operation from STOP/HALT Mode..............4-14 4.3.4 Block control function .........................4-15 Chapter 5 Interrupts (INTs) .............................5-1 Genral Description ............................5-1...
  • Page 7   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents Description of Registers ..........................6-4 6.2.1 List of Registers.............................6-4 6.2.2 Frequency Control Register 0(FCON0)....................6-5 6.2.3 Frequency Control Register 1 (FCON1)....................6-7 6.2.4 Frequency Control Register 3 (FCON3)....................6-8 6.2.5 Frequency Status Register (FSTAT) ....................6-10 Description of Operation ...........................6-11 6.3.1 Low-Speed Clock ..........................6-11 6.3.1.1...
  • Page 8   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents Chapter 9 16bit Timer..............................9-1 Genral Description ............................9-1 9.1.1 Features..............................9-1 9.1.2 Configuration............................9-1 Description of Registers ..........................9-2 9.2.1 List of Registers.............................9-2 9.2.2 16bit timer 8 data register L,H (TMH8DL,H) ..................9-3 9.2.3 16bit timer 9 data register L,H (TMH9DL,H) ..................9-4 9.2.4 16bit timer A data register L,H (TMHADL,H) ..................9-5 9.2.5...
  • Page 9   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents 11.2.17 PWM5 control register 2 (PW5CON2) .....................11-27 11.2.18 PWM5 control register 4 (PW5CON4) .....................11-29 11.2.19 PWM5 control register 5 (PW5CON5) .....................11-30 11.2.20 PWM5 control register 6 (PW5CON6) .....................11-31 11.2.21 PWM6 period registers (PW6PL, PW6PH)..................11-32 11.2.22 PWM6 duty registers (PW6DL, PW6DH) ..................11-33 11.2.23 PWM6 counter registers (PW6CL, PW6CH) ..................11-34 11.2.24 PWM6 control register 0 (PW6CON0) .....................11-35 11.2.25 PWM6 control register 1 (PW6CON1) .....................11-37...
  • Page 10   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents Chapter 12 12. Synchronous Serial Port (SSIO)........................12-1 12.1 Genral Description ............................12-1 12.1.1 Features..............................12-1 12.1.2 Configuration............................12-1 12.1.3 List of Pins............................12-2 12.2 Description of Registers ..........................12-3 12.2.1 List of Registers...........................12-3 12.2.2 Serial Port 0 Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH)............12-4 12.2.3 Serial Port 0 Control Register (SIO0CON) ..................12-5 12.2.4 Serial Port 0 Mode Register 0 (SIO0MOD0) ..................12-6 12.2.5 Serial Port 0 Mode Register 1 (SIO0MOD1) ..................12-7...
  • Page 11   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents Chapter 14 14. I C Bus Interface ............................14-1 14.1 Genral Description ............................14-1 14.1.1 Features..............................14-1 14.1.2 Configuration............................14-1 14.1.3 List of Pins............................14-2 14.2 Description of Registers ..........................14-3 14.2.1 List of Registers...........................14-3 14.2.2 I C Bus 0 Receive Register (I2C0RD) ....................14-4 14.2.3 I C Bus 0 Slave Address Register (I2C0SA)..................14-5 14.2.4 I...
  • Page 12   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents Chapter 17 17. Port 2 ................................17-1 17.1 Genral Description ............................17-1 17.1.1 Features..............................17-1 17.1.2 Configuration............................17-1 17.1.3 List of Pins............................17-1 17.2 Description of Registers ..........................17-2 17.2.1 List of Registers...........................17-2 17.2.2 Port 2 Data Register (P2D) ........................17-3 17.2.3 Port 2 control registers 0, 1 (P2CON0, P2CON1)................17-4 17.2.4 Port 2 Mode Register (P2MOD)......................17-6 17.3 Description of Operation ...........................17-8 17.3.1 Output Port Function ...........................17-8...
  • Page 13   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents 20.2.3 Port 5 Direction Register (P5DIR) ......................20-6 20.2.4 Port 5 Control Registers 0, 1 (P5CON0, P5CON1)................20-7 20.2.5 Port 5 Mode Registers 0, 1 (P5MOD0, P5MOD1)................20-9 20.3 Description of Operation .........................20-12 20.3.1 Input/Output Port Functions ......................20-12 20.3.2 Secondary, Tertiary, and Quartic Functions ..................20-12 Chapter 21 21.
  • Page 14   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents 24.1.1 Features..............................24-1 24.1.2 Configuration............................24-1 24.1.3 List of Pins............................24-2 24.2 Description of Registers ..........................24-3 24.2.1 List of Registers...........................24-3 24.2.2 SA-ADC Result Register 0L (SADR0L).....................24-4 24.2.3 SA-ADC Result Register 0H (SADR0H)....................24-4 24.2.4 SA-ADC Result Register 1L (SADR1L).....................24-5 24.2.5 SA-ADC Result Register 1H (SADR1H)....................24-5 24.2.6 SA-ADC Result Register 2L (SADR2L).....................24-6 24.2.7 SA-ADC Result Register 2H (SADR2H)....................24-6...
  • Page 15   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents 26.2.2 LLD Circuit Control Register 1 (LLDCON1) ..................26-3 26.3 Description of Operation ...........................26-4 26.3.1 Threshold Voltage ..........................26-4 26.3.2 Operation of LLD Circuit ........................26-5 Chapter 27 27. Power Supply Circuit ............................27-1 27.1 Genral Description ............................27-1 27.1.1 Features..............................27-1 27.1.2 Configuration............................27-1 27.1.3 List of Pins............................27-1 27.2 Description of Registers ..........................27-2...
  • Page 16   ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Contents Appendix D Application Circuit Example ......................D-1 Appendix E Check List ............................E-1 Revision History Revision History..............................R-1 FEUL620Q150A Contents-12...

  • Page 17: Overview

    Chapter 1 Overview...

  • Page 18: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1. Overview 1.1 Features This LSI is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit A/D converter, timer, PWM, synchronous serial port, UART, I2C bus interface (master), Low level detect circuit, are incorporated around 16-bit CPU nX-U16/100.
  • Page 19 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview - 16 bits x 4ch - The auto reload timer mode / PWM mode - Timer start-stop function by the software and an external trigger. - A pulse width can be measured using an external-trigger input. - An external event can be selected as the counter clock.
  • Page 20 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview Clock - Low-speed clock (This LSI can not guarantee the operation without low-speed clock) - Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.768kHz) - Crystal oscillation or Built-in RC oscillation is selectable as Code-Option. - High-speed clock - Built-in RC oscillation (2.097MHz) or Built-in PLL oscillation (8.192MHz) Power management...

  • Page 21: Configuration Of Functional Blocks

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.2 Configuration of Functional Blocks 1.2.1 Block Diagram of ML620Q151A/ML620Q152A/ML620Q153A(TQFP48) CPU (nX-U16/100) EPSW1～3 ELR1～3 ECSR1～3 GREG 0～15 DSR/CSR Program Timing Memory Controller (FLASH) Instruction Instruction 32/48/64Kbyte Controller On-Chip Decoder Register Data-bus SSIOx1 SCK0* SIN0* SOUT0* 2Kbyte RXD0*...

  • Page 22: Block Diagram Of Ml620Q154A/Ml620Q155A/Ml620Q156A(Tqfp52)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.2.2 Block Diagram of ML620Q154A/ML620Q155A/ML620Q156A(TQFP52) CPU (nX-U16/100) EPSW1～3 ELR1～3 ECSR1～3 GREG 0～15 DSR/CSR Program Timing Memory Controller (FLASH) Instruction Instruction 32/48/64Kbyte Controller On-Chip Decoder Register Data-bus SSIOx1 SCK0* SIN0* SOUT0* 2Kbyte RXD0* UARTx1 Power TXD0* (*1) RXD1*...

  • Page 23: Block Diagram Of Ml620Q157A/Ml620Q158A/Ml620Q159A(Qfp64)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.2.3 Block Diagram of ML620Q157A/ML620Q158A/ML620Q159A(QFP64) CPU (nX-U16/100) EPSW1～3 ELR1～3 ECSR1～3 GREG 0～15 DSR/CSR Program Timing Memory Controller (FLASH) Instruction Instruction 32/48/64Kbyte Controller On-Chip Decoder Register Data-bus SSIOx1 SCK0* SIN0* SOUT0* 2Kbyte RXD0* UARTx1 Power TXD0* (*1) RXD1*...

  • Page 24: Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.3 Pins 1.3.1 Pin Layout 1.3.1.1 Pin Layout of ML620Q151A/ML620Q152A/ML620Q153A TQFP48 package product P00/EXI0/PW45EV0 P57/SOUT0/PWM7 P01/EXI1/PW67EV0 P56/SCK0 P02/EXI2/RXD0 P55/TXD0/SIN0/TXD1 P03/EXI3/RXD1 P54/RXD0 P04/EXI4 P47/AIN11/T16CK1/PWM5 (TOP VIEW) P20/LED0/LSCLK/PWM4 P46/AIN10/T16CK0/SOUT0 TQFP48 P21/LED1/OUTCLK/PWM5 P45/AIN9/T1P5CK/SCK0 P22/LED2/TMHAOUT/PWM6 P44/AIN8/T0P4CK/SIN0 P23/LED3/TMHBOUT/PWM7 P43/AIN7/TXD0/PWM4/TXD1 P42/AIN6/RXD0/SOUT0 P14/TEST0 P41/SCL/SCK0/CMP0P...
  • Page 25 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.3.1.2 Pin Layout of ML620Q154A/ML620Q155A/ML620Q156A TQFP52 package product P00/EXI0/PW45EV0 P57/SOUT0/PWM7 P56/SCK0 P01/EXI1/PW67EV0 P55/TXD0/SIN0/TXD1 P02/EXI2/RXD0 P03/EXI3/RXD1 P54/RXD0 P53/TXD1/PWM6 P04/EXI4 P47/AIN11/T16CK1/PWM5 P05/EXI5 (TOP VIEW) P46/AIN10/T16CK0/SOUT0 P20/LED0/LSCLK/PWM4 TQFP52 P21/LED1/OUTCLK/PWM5 P45/AIN9/T1P5CK/SCK0 P44/AIN8/T0P4CK/SIN0 P22/LED2/TMHAOUT/PWM6 P43/AIN7/TXD0/PWM4/TXD1 P23/LED3/TMHBOUT/PWM7 P42/AIN6/RXD0/SOUT0 P14/TEST0 P41/SCL/SCK0/CMP0P RESET_N P40/SDA/SIN0/CMP0M TEST1_N...
  • Page 26 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.3.1.3 Pin Layout of ML620Q157A/ML620Q158A/ML620Q159A QFP64 package product P00/EXI0/PW45EV0 P57/SOUT0/PWM7 P01/EXI1/PW67EV0 P56/SCK0 P02/EXI2/RXD0 P55/TXD0/SIN0/TXD1 P03/EXI3/RXD1 P54/RXD0 P04/EXI4 P53/TXD1/PWM6 P52/RXD1/SOUT0 P05/EXI5 P20/LED0/LSCLK/PWM4 P51/SCL/SCK0 P21/LED1/OUTCLK/PWM5 P50/SDA/SIN0 P22/LED2/TMHAOUT/PWM6 P47/AIN11/T16CK1/PWM5 (TOP VIEW) P46/AIN10/T16CK0/SOUT0 QFP64 P72/RXD1/SIN0 P45/AIN9/T1P5CK/SCK0 P73/TXD1/SCK0/TXD0 P44/AIN8/T0P4CK/SIN0 P74/SOUT0 P43/AIN7/TXD0/PWM4/TXD1 P14/TEST0...

  • Page 27: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.3.2 List of Pins Primary function Secondary function Tertiary function Quaternary function Description name name scription name scription name scription Negative power ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ supply pin Positive power ⎯...
  • Page 28 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview Primary function Secondary function Tertiary function Quaternary function Description name name scription name scription name scription Input/output port / P34/ Successive PWM4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PWM4 AIN4/ approximation type output ADC input Input/output port / P35/ Successive...
  • Page 29 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview Primary function Secondary function Tertiary function Quaternary function Description name name scription name scription name scription UART0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Input/output port RXD0 data input UART0 SSIO0 UART1 Input/output port TXD0 data SIN0 data...
  • Page 30 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview Primary function Secondary function Tertiary function Quaternary function Description name name scription name scription name scription UART0 SSIO0 ⎯ ⎯ ⎯ data Input/output port RXD0 data SOUT0 output input UART0 PWM4 ⎯ ⎯ ⎯ Input/output port TXD0 data...

  • Page 31: Pin Description

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.3.3 Pin Descriptions Table 1-2 Pin Descriptions (1/3) Primary/ Secondary/ Pin name Description Logic Tertiary/ Quaternary Power supply — Negative power supply pin — — — Positive power supply pin — — — Positive power supply pin for internal logic (internally generated). Connect —...
  • Page 32 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview Table 1-2 Pin Descriptions (2/3) Primary/ Secondary/ Pin name Description Logic Tertiary/ Quaternary UART TXD0* Secondary UART0 data output pin. Allocated to the secondary function of the P43, Positive P55 , P87 and the fourthly function of the P73. Quaternary UART0 data input pin.
  • Page 33 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview Table 1-2 Pin Descriptions (3/3) Primary/ Pin name Description Logic Secondary External interrupt External maskable interrupt input pins. The interrupt is enabled and EXI0～7* Positive/ interrupt edge is selectable by the software for each bit. Allocated to the Primary Negative primary function of the P00 to P05 and P30 to P31.

  • Page 34: Handling Of Unused Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 1 Overview 1.3.4 Handling of Unused Pins Table 1-3 shows methods of terminating the unused pins. Table 1-3 Termination of Unused Pins Recommended pin termination RESET_N open P14/TEST0 open TEST1_N open Connect to V P00 to P05* Connect V or V Connect V...

  • Page 35: Cpu And Memory Space

    Chapter 2 CPU and Memory Space...

  • Page 36: Genral Description

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space CPU and Memory Space 2.1 General Description This LSI includes 16-bit CPU nX-U16/100 and the memory model is SMALL model. For details of the CPU nX-U16/100, see “nX-U16/100 Core Instruction Manual”. 2.2 Program Memory Space The program memory space is used to store program codes, table data (ROM window), or vector tables.
  • Page 37 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space Segment 0 CSR:PC 0:0000H ~ 0BFFFH 0:0BFFFH Test data area 0:0BC00H 0:0BBFFH Program code ROM window area 0:0100H 0:00FFH Vector table area Program code ROM window area 0:0000H 8bit Figure 2-2 Configuration of ML620Q152A/ML620Q155A/ML620Q158A Program Memory Space (48-Kbyte) Note: ・...
  • Page 38 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space Segment 0 CSR:PC 0:0000H ~ 0FFFFH 0:0FFFFH Test data area 0:0FC00H 0:0FBFFH Program code ROM window area 0:0100H 0:00FFH Vector table area Program code ROM window area 0:0000H 8bit Figure 2-3 Configuration of ML620Q153A/ML620Q156A/ML620Q159A Program Memory Space (64-Kbyte) Note: ・...

  • Page 39: Data Memory Space

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space 2.3 Data Memory Space The data memory space of this LSI consists of the ROM window area of Segment 0, 2KByte RAM area, SFR area, and ROM reference area of segment 8. The data memory has the 8-bit length and is specified by a 4-bit Data Segment Register (DSR) and 16-bit addressing instructions.
  • Page 40 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space DSR: Data address Segment 0 Segment 7 0:0FFFFH SFR are 0:0F000H Unused area 0:0E7FFH RAM area 2K Byte 0:0E000H Unused area 0:0DFFFH Unused area 0:0C000H 0:0BFFFH Test data area 0:0BC00H 7:07FFH ROM Window Data Flash area area...
  • Page 41 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space DSR: Data address Segment 0 Segment 7 0:0FFFFH SFR area 0:0F000H Unused area 0:0E7FFH RAM area 2K Byte Unused area 0:0E000H ROM Window area 7:07FFH Data Flash area 2K Byte 0:0000H 7:0000H 8bit 8bit...

  • Page 42: Instruction Length

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space 2.4 Instruction Length The length of an instruction is 16 bits. 2.5 Data Type The data types supported include byte (8 bits) and word (16 bits). FEUL620Q150A...

  • Page 43: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space 2.6 Description of Registers 2.6.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F000H Data segment register — FEUL620Q150A...

  • Page 44: Data Segment Register (Dsr)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 2 CPU and Memory Space 2.6.2 Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8-bit Initial value: 00H — — — — DSR3 DSR2 DSR1 DSR0 Initial value DSR is a special function register (SFR) to retain a data segment. For details of DSR, see “nX-U16/100 Core Instruction Manual”.

  • Page 45: Reset Function

    Chapter 3 Reset Function...

  • Page 46: General Description

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 3 Reset Function Reset Function 3.1 General Description This LSI has the five reset functions. If any of the four reset conditions is satisfied, this LSI enters system reset mode. • Reset by the RESET_N pin •...

  • Page 47: Reset Status Register (Rstat)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 3 Reset Function 3.2.2 Reset Status Register (RSTAT) Address: 0F00CH Access: R/W Access size: 8 bits Initial value: Undefined ― ― ― ― RSTAT RSTR LLDR WDTR Initial value *)The initial value depends on the reset factor RSTAT is a special function register (SFR) that indicates the causes set to the system reset mode.

  • Page 48: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 3 Reset Function 3.3 Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all processings and any other processing will be cancelled. The system reset mode is set by any of the following causes. •...

  • Page 49: Mcu Control Function

    Chapter 4 MCU Control Function...

  • Page 50: General Description

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function MCU Control Function 4.1 General Description The operating states of this LSI are classified into the following 4 modes including system reset mode: (1) System reset mode (2) Program run mode (3) HALT mode (4) STOP mode For the System reset mode, see Chapter 3, "Reset Function".

  • Page 51: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2 Description of Registers 4.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value 0F008H Stop code acceptor STPACP 0F009H Standby control register SBYCON 0F068H Block control register 0 BLKCON0 0F06AH Block control register 2...

  • Page 52: Stop Code Acceptor (Stpacp)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2.2 Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value: -(Undefined) STPACP Initial value STPACP is a write-only special function register (SFR) that is used for setting a STOP mode. When STPACP is read, “00H”...

  • Page 53: Standby Control Register (Sbycon)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H SBYCON HLTH DHLT Initial value SBYCON is a special function register (SFR) to control the operation mode of MCU. Description of Bits •...

  • Page 54: Block Control Register 0 (Blkcon0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2.4 Block Control Register 0 (BLKCON0) Address: 0F068H Access: R/W Access size: 8 bit Initial value: 00H BLKCON0 DTM1 DTM0 Initial value BLKCON0 is a special function register (SFR) to control each block operation. Description of Bits •...

  • Page 55: Block Control Register 2 (Blkcon2)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2.5 Block Control Register 2 (BLKCON2) Address: 0F06AH Access: R/W Access size: 8 bit Initial value: 00H BLKCON2 DI2C0 DUA1 DUA0 DSIO0 Initial value BLKCON2 is a special function register (SFR) to control each block operation. Description of Bits •...

  • Page 56: Block Control Register 3 (Blkcon3)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2.6 Block Control Register 3 (BLKCON3) Address: 0F06BH(BLKCON3) Access: R/W Access size: 8 bit Initial value: 00H BLKCON3 DCMP Initial value BLKCON3 is a special function register (SFR) to control each block operation. Description of Bits •...

  • Page 57: Block Control Register 4 (Blkcon4)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2.7 Block Control Register 4 (BLKCON4) Address: 0F06CH(BLKCON4) Access: R/W Access size: 8 bit Initial value: 00H BLKCON4 DSAD Initial value BLKCON4 is a special function register (SFR) to control each block operation. Description of Bits •...

  • Page 58: Block Control Register 6 (Blkcon6)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2.8 Block Control Register 6 (BLKCON6) Address: 0F06EH(BLKCON6) Access: R/W Access size: 8 bit Initial value: 00H BLKCON6 DTMB DTMA DTM9 DTM8 Initial value BLKCON6 is a special function register (SFR) to control each block operation. Description of Bits •...

  • Page 59: Block Control Register 7 (Blkcon7)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.2.9 Block Control Register 7 (BLKCON7) Address: 0F06FH(BLKCON7) Access: R/W Access size: 8 bit Initial value: 00H BLKCON7 DPW7 DPW6 DPW5 DPW4 Initial value BLKCON7 is a special function register (SFR) to control each block operation. Description of Bits •...

  • Page 60: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.3 Description of Operation 4.3.1 Program Operating Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, low-speed oscillation stop detect reset, WDT overflow reset, or RESET_N pin reset, the CPU executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system reset mode is released.

  • Page 61: Stop Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.3.3 STOP Mode During the STOP mode, the low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by successively writing “5nH” and “0AnH” (where n is 0 to 0FH) to the stop code acceptor (STPACP) and the STP bit of the standby control register (SBYCON) is set to “1”, the STOP mode is entered.

  • Page 62: Stop Mode When The Cpu Runs With High-Speed Clock

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.3.3.2 Stop mode when the CPU runs with high-speed clock When the STP bit of SBYCON is set to “1” with the stop code acceptor enabled while the high-speed clock is operating, the mode changes to the STOP mode and the high-speed oscillation and low-speed oscillation stop.

  • Page 63: Note On Return Operation From Stop/Halt Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.3.3.3 Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP or HALT mode depends on the condition of interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.

  • Page 64: Block Control Function

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 4 MCU Control Function 4.3.4 Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. For each block control register, the initial value of each flag is “0”, meaning the operation of each block is enabled. When any flag is set to “1”...

  • Page 65: Interrupts (Ints)

    Chapter 5 Interrupts...

  • Page 66: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5 Interrupt 5.1 General Description This LSI has external interrupts, internal interrupts, and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 7, "Time Base Counter" Chapter 8, "8-bit Timer" Chapter 9, "16-bit Timer"...

  • Page 67: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2 Description of Registers 5.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F010H Interrupt enable register 0 0F011H Interrupt enable register 1 0F012H Interrupt enable register 2 0F013H Interrupt enable register 3 0F014H Interrupt enable register 4 0F015H...

  • Page 68: Interrupt Enable Register 0 (Ie0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.2 Interrupt Enable Register 0 (IE0) Address: 0F010H Access: R/W Access size: 8 bits Initial value: 00H ELLD Initial value IE0 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE0 is not reset.

  • Page 69: Interrupt Enable Register 1 (Ie1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.3 Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8 bits Initial value: 00H EP31 EP30 EP05 EP04 EP03 EP02 EP01 EP00 Initial value IE1 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE1 is not reset.
  • Page 70 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts • EP02 (bit 2) EP02 is the enable flag for the input port P02 pin interrupt (P02INT). EP02 Description Disabled (initial value) Enabled • EP01 (bit 1) EP01 is the enable flag for the input port P01 pin interrupt (P01INT). EP01 Description Disabled (initial value)

  • Page 71: Interrupt Enable Register 2 (Ie2)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.4 Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8 bits Initial value: 00H EI2C0 ESAD ESIO0 Initial value IE2 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE2 is not reset.

  • Page 72: Interrupt Enable Register 3 (Ie3)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.5 Interrupt Enable Register 3 (IE3) Address: 0F013H Access: R/W Access size: 8 bits Initial value: 00H ECMP0 ETM9 ETM8 ETM1 ETM0 Initial value IE3 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE3 is not reset.

  • Page 73: Interrupt Enable Register 4 (Ie4)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.6 Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8 bits Initial value: 00H EUA1 EUA0 Initial value IE4 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE4 is not reset.

  • Page 74: Interrupt Enable Register 5 (Ie5)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.7 Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8 bits Initial value: 00H ETMB ETMA Initial value IE5 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE5 is not reset.

  • Page 75: Interrupt Enable Register 6 (Ie6)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.8 Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8 bits Initial value: 00H ELTBC1 ELTBC0 EPW7 EPW6 EPW5 EPW4 Initial value IE6 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE6 is not reset.
  • Page 76 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts • EPW5 (bit 1) EPW5 is the enable flag for the PWM5 interrupt (PW5INT). EPW5 Description Disabled (initial value) Enabled • EPW4 (bit 0) EPW4 is the enable flag for the PWM4 interrupt (PW4INT). EPW4 Description Disabled (initial value)

  • Page 77: Interrupt Enable Register 7 (Ie7)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.9 Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8 bits Initial value: 00H ELTBC2 Initial value IE7 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE7 is not reset.

  • Page 78: Interrupt Request Register 0 (Irq0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.10 Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8 bits Initial value: 00H IRQ0 QLLD QCKC QWDT Initial value IRQ0 is a special function register (SFR) used to request an interrupt for each interrupt source. The watchdog timer interrupt (WDTINT) and the clock backup interrupt (CKCINT) are non-maskable interrupts that do not depend on MIE.

  • Page 79: Interrupt Request Register 1 (Irq1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.11 Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8 bits Initial value: 00H IRQ1 QP31 QP30 QP05 QP04 QP03 QP02 QP01 QP00 Initial value IRQ1 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ1 request flag is set to "1"...
  • Page 80 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts • QP02 (bit 2) QP02 is the request flag for the input port P02 pin interrupt (P02INT). QP02 Description No request (initial value) Request • QP01 (bit 1) QP01 is the request flag for the input port P01 pin interrupt (P01INT). QP01 Description No request (initial value)

  • Page 81: Interrupt Request Register 2 (Irq2)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.12 Interrupt Request Register 2 (IRQ2) Address: 0F01AH Access: R/W Access size: 8 bits Initial value: 00H IRQ2 QI2C0 QSAD QSIO0 Initial value IRQ2 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ2 request flag is set to "1"...

  • Page 82: Interrupt Request Register 3 (Irq3)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.13 Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8 bits Initial value: 00H IRQ3 QCMP0 QTM9 QTM8 QTM1 QTM0 Initial value IRQ3 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ3 request flag is set to "1"...
  • Page 83 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts [Note] When an interrupt is generated by the write instruction to the interrupt request register (IRQ3) or to the interrupt enable register (IE3), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL620Q150A 5-18...

  • Page 84: Interrupt Request Register 4 (Irq4)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.14 Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8 bits Initial value: 00H IRQ4 QUA1 QUA0 Initial value IRQ4 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ4 request flag is set to "1"...

  • Page 85: Interrupt Request Register 5 (Irq5)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.15 Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8 bits Initial value: 00H IRQ5 QTMB QTMA Initial value IRQ5 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ5 request flag is set to "1"...

  • Page 86: Interrupt Request Register 6 (Irq6)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.16 Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8 bits Initial value: 00H IRQ6 QLTBC1 QLTBC0 QPW7 QPW6 QPW5 QPW4 Initial value IRQ6 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ6 request flag is set to "1"...
  • Page 87 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts [Note] When an interrupt is generated by the write instruction to the interrupt request register (IRQ6) or to the interrupt enable register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL620Q150A 5-22...

  • Page 88: Interrupt Request Register 7 (Irq7)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.17 Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8 bits Initial value: 00H IRQ7 QLTBC2 Initial value IRQ7 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ7 request flag is set to "1"...

  • Page 89: Interrupt Level Control Enable Register (Ilenl)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.18 Interrupt Level Control Enable Register (ILENL) Address: 0F020H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― ― ― ― ILENL Initial value The interrupt level control enable register (ILENL) is a special function register (SFR) used to control enable/disable for the interrupt level control.

  • Page 90: Current Interrupt Request Level Register (Cill)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.19 Current Interrupt Request Level Register (CILL) Address: 0F022H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― CILL CILN CILM[3:0] Initial value The current interrupt request level register (CILL) indicates the interrupt level of the interrupt currently being processed by the processor.

  • Page 91: Interrupt Level Control Register 01 (Ilc01)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.20 Interrupt Level Control Register 01 (ILC01) Address: 0F025H Access: R/W Access size: 8 bits Initial value: 00H ILC01 ILC01[5:4] Initial value The interrupt level control register 01 (ILC01) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 92: Interrupt Level Control Register 10 (Ilc10)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.21 Interrupt Level Control Register 10 (ILC10) Address: 0F026H Access: R/W Access size: 8 bits Initial value: 00H ILC10 ILC10[7:6] ILC10[5:4] ILC10[3:2] ILC10[1:0] Initial value The interrupt level control register 10 (ILC10) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 93: Interrupt Level Control Register 11 (Ilc11)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.22 Interrupt Level Control Register 11 (ILC11) Address: 0F027H Access: R/W Access size: 8 bits Initial value: 00H ILC11 ILC11[7:6] ILC11[5:4] ILC11[3:2] ILC11[1:0] Initial value The interrupt level control register 11 (ILC11) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 94: Interrupt Level Control Register 20 (Ilc20)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.23 Interrupt Level Control Register 20 (ILC20) Address: 0F028H Access: R/W Access size: 8 bits Initial value: 00H ILC20 ILC20[5:4] ILC20[1:0] Initial value The interrupt level control register 20 (ILC20) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 95: Interrupt Level Control Register 21 (Ilc21)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.24 Interrupt Level Control Register 21 (ILC21) Address: 0F029H Access: R/W Access size: 8 bits Initial value: 00H ILC21 ILC21[7:6] Initial value The interrupt level control register 21 (ILC21) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 96: Interrupt Level Control Register 30 (Ilc30)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.25 Interrupt Level Control Register 30 (ILC30) Address: 0F02AH Access: R/W Access size: 8 bits Initial value: 00H ILC30 ILC30[7:6] ILC30[5:4] ILC30[3:2] ILC30[1:0] Initial value The interrupt level control register 30 (ILC05) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 97: Interrupt Level Control Register 31 (Ilc31)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.26 Interrupt Level Control Register 31 (ILC31) Address: 0F02BH Access: R/W Access size: 8 bits Initial value: 00H ILC31 ILC31[5:4] Initial value The interrupt level control register 31 (ILC31) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 98: Interrupt Level Control Register 40 (Ilc40)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.27 Interrupt Level Control Register 40 (ILC40) Address: 0F02CH Access: R/W Access size: 8 bits Initial value: 00H ILC40 ILC40[3:2] ILC40[1:0] Initial value The interrupt level control register 40 (ILC40) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 99: Interrupt Level Control Register 51 (Ilc51)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.28 Interrupt Level Control Register 51 (ILC51) Address: 0F02FH Access: R/W Access size: 8 bits Initial value: 00H ILC51 ILC51[3:2] ILC51[1:0] Initial value The interrupt level control register 51 (ILC51) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 100: Interrupt Level Control Register 60 (Ilc60)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.29 Interrupt Level Control Register 60 (ILC60) Address: 0F030H Access: R/W Access size: 8 bits Initial value: 00H ILC60 ILC60[7:6] ILC60[5:4] ILC60[3:2] ILC60[1:0] Initial value The interrupt level control register 60 (ILC60) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 101: Interrupt Level Control Register 61 (Ilc61)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.30 Interrupt Level Control Register 61 (ILC61) Address: 0F031H Access: R/W Access size: 8 bits Initial value: 00H ILC61 ILC61[7:6] ILC61[3:2] Initial value The interrupt level control register 61 (ILC61) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 102: Interrupt Level Control Register 70 (Ilc70)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.2.31 Interrupt Level Control Register 70 (ILC70) Address: 0F032H Access: R/W Access size: 8 bits Initial value: 00H ILC70 ILC70[7:6] Initial value The interrupt level control register 70 (ILC70) sets the interrupt level for the specific maskable interrupt source. Access to this register is possible only when the interrupt level control is enabled by the ILENL register.

  • Page 103: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.3 Description of Operation With the exceptions of the watchdog timer interrupt (WDTINT) and clock backup interrupt (CKCINT), interrupt enable/disable for 28 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE1 to 7).

  • Page 104: Maskable Interrupt Processing

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.3.1 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to "1", the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) Transfer the program counter (PC) to ELR1 (2) Transfer PSW to EPSW1 (3) Set the MIE flag to "0"...

  • Page 105: Notes On Interrupt Routine (When Interrupt Level Control Disabled)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.3.4 Notes on Interrupt Routine (When Interrupt Level Control Disabled) If ILE of the interrupt level control enable register (ILENL) is set to disable the interrupt level control, notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable.
  • Page 106 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution Specify the "PUSH LR" instruction to save the subroutine return address in the stack. •...
  • Page 107 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts Status B: Non-maskable interrupt is being processed B-1: When a subroutine is not called • Processing immediately after the start of interrupt routine execution No specific notes. • Processing at the end of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW.

  • Page 108: Interrupt Processing When Interrupt Level Control Enabled

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.3.5 Interrupt Processing When Interrupt Level Control Enabled Interrupt processing The interrupt handler carries out the following processing. i. The following processing is made when multiple interrupts are enabled. When a higher level interrupt request occurs, that request should be processed with priority. For this reason, the general-purpose registers are saved to memory and the EPW and EPSW registers are pushed in order to retain the processor state at return.

  • Page 109: Flow Chart When Interrupt Level Control Enabled

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.3.6 Flow Chart When Interrupt Level Control Enabled The figure below shows the flow chart of the software processing of a maskable interrupt when the interrupt level control is enabled. The EI and DI instructions allow the execution of multiple interrupts by a higher-level maskable interrupt request during the "execution of the desired processing".
  • Page 110 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts Non-maskable interrupt Save general-purpose registers to memory Execute desired processing Write access to current interrupt level register (CILL) Restore general-purpose registers from memory RTI instruction Interrupt processing FEUL620Q150A 5-45...

  • Page 111: How To Write Interrupt Processing When Interrupt Level Control Enabled

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts 5.3.7 How To Write Interrupt Processing When Interrupt Level Control Enabled When ILE of the interrupt level control enable register (ILENL) is set to enable the interrupt level control, the interrupt function should be written as below. For more details and notes on how to write the interrupt processing, refer to "CCU8 Programming Guide".
  • Page 112 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts push push func(); _func CILL = 0; #00h 0f022h When calling other functions from an interrupt function, the output code becomes more redundant, which results in a longer interrupt processing time. This is because CCU8 does not know which register is used by func and thus saves all possible registers that may be changed by calling the func function in the stack.

  • Page 113: Interrupt Disable State

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 5 Interrupts CILL = 0; #00h 0f022h psw, pc An interrupt function enabling multiple interrupts should save ELR and EPSW in the stack so that ELR and EPSW are not destroyed by multiple interrupts. This is different from the case for interrupt functions disabling multiple interrupts.

  • Page 114: Clock Generation Circuit

    Chapter 6 Clock Generation Circuit ...

  • Page 115: General Description

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6 Clock Generation Circuit 6.1 General Description The clock generation circuit generates and provides the low-speed clock (LSCLK), the high-speed clock (HSCLK), the system clock (SYSCLK), and the high-speed output clock (OUTCLK). LSCLK and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU, and OUTCLK is a clock that is output from a port.
  • Page 116 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit [Note] After power-on or system reset, the operation starts by the clock supplied from the built-in high-speed clock generation circuit with the frequency divided by 8. Change it as needed by setting the FCON0, FCON1 and FCON2 register. FEUL620Q150A...

  • Page 117: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Pin Name Function P12/XT0 Pin for connecting a crystal for low-speed clock. P13/XT1 Pin for connecting a crystal for low-speed clock. 6.1.4 Clock Configuration Diagram Figure 6-2 shows the clock system diagram. System clock(SYSCLK) Register access LSCLK...
  • Page 118 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.2 Description of Registers 6.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F002H Frequency control register 0 FCON0 8/16 FCON01 0F003H Frequency control register 1 FCON1 0F005H Frequency control register 3 FCON3 0F00AH...

  • Page 119: Frequency Control Register 0(Fcon0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.2.2 Frequency Control Register 0 (FCON0) Address: 0F002H (FCON0) Access: R/W Access size: 8/16 bit Initial value: 33H FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0 Initial value FCON0 is a special function register (SFR) used to control the high-speed clock generation circuit and to select system clock.
  • Page 120 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit [Note] •To switch the high-speed clock mode using the OSCM1 and OSCM0 bits, stop the high-speed oscillation and set the system clock to the low-speed clock (set the ENOSC and SYSCLK bits of the FCON1 register to "0"). •...

  • Page 121: Frequency Control Register 1 (Fcon1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 1 (FCON1) Address: 0F003H (FCON1) Access: R/W Access size: 8 bit Initial value: 03H FCON1 LPLL ENOSC SYSCLK Initial value FCON01 is a special function register (SFR) used to control the high-speed clock generation circuit and to select system clock.

  • Page 122: Frequency Control Register 3(Fcon3)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.2.4 Frequency Control Register 3(FCON3) Address: 0F005H(FCON3) Access: R/W Access size: 8 bits Initial Value: 00H FCON3 LOSCB HOSCB Initial value FCON3 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. FCON3 works only when the low-speed crystal oscillation circuit is selected by Code-Option.
  • Page 123 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit • HOSCB （bit 1） The HOSCB bit shows the high-speed clock backup mode, and it is used to cancel the backup mode by clearing the HOSCB bit(by writing “1” to the HOSCB bit). The HOSCB bit works only when the low-speed crystal oscillation circuit is selected by Code-Option and PLL oscillation is selected as the high-speed clock by FCON registers.

  • Page 124: Frequency Status Register (Fstat)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.2.5 Frequency Status Register (FSTAT) Address: 0F00AH Access: R Access size: 8 bits Initial value: 06H FSTAT LOSCS HOSCS Initial value FSTAT is a special function register (SFR) used to show the clock generation circuit state. Description of Bits •...

  • Page 125: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.3 Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Crystal Oscillation Circuit Figure 6-3 shows the low-speed clock generation circuit configuration. The low-speed clock generation circuit requires an external 32.768 kHz crystal to work. To match the oscillation frequency by using a trimmer capacitor, connect external capacitors (C and C ) as required.

  • Page 126: Operation Of Low-Speed Clock Generation Circuit

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.3.1.3 Operation of Low-Speed Clock Generation Circuit The low-speed clock generation circuit is activated by the occurrence of power ON reset. After the power-on, it waits for the low-speed oscillation start time (T ) and the low-speed clock (LSCLK) oscillation stabilization time (8192 counts).

  • Page 127: High-Speed Clock

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.3.2 High-Speed Clock For the high-speed clock generation circuit, the built-in RC oscillation mode or the PLL (Phase Locked Loop) oscillation mode can be selected. 6.3.2.1 High-Speed Built-in RC Oscillation Circuit Figure 6-6 shows the block diagram of high-speed built-in RC oscillation circuit. When the RC oscillation clock is counted to 16, the high-speed oscillation clock (HSCLK) starts to be supplied.

  • Page 128: Operation Of High-Speed Clock

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.3.2.3 Operation of High-Speed Clock The high-speed clock generation circuit is activated in the built-in RC oscillation mode (2.097MHz) by power-on reset generation. As a result of the occurrence of power-on reset, the circuit goes into system reset mode and then shifts to program operating mode after the elapse of the high-speed oscillation start time (T ) and the oscillation stabilization time (Count: 32,768) of the high-speed RC oscillation clock (OSCLK) and at the same time, a high-speed clock (HSCLK) is...
  • Page 129 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit High-speed oscillation enable bit ENOSC : High-speed oscillation start time : High-speed oscillation start time High-speed Built-in PLL oscillation Built-in PLL oscillation oscillation High-speed oscillation 4096 High-speed oscillation 4096 counts 16 counts High-speed PLL oscillation PLL oscillation waveform...

  • Page 130: Switching Of System Clock

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.3.3 Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-11 shows the flow chart of the system clock switching processing (HSCLK→LSCLK), and Figure 6-12 shows the flow chart of the system clock switching processing (LSCLK→HSCLK).

  • Page 131: Specifying Port Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.4 Specifying Port Registers To enable the clock output function, each related port register bit needs to be set. See Chapter 17, "Port 2" and Chapter 18, "Port 3" for detail about the port registers. 6.4.1 Functioning P21(OUTCLK) as the high-speed clock output Set P21MD bit (bit1 of P2MOD register) to “1”...

  • Page 132: Functioning P20 (Lsclk) As The Low-Speed Clock Output

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.4.2 Functioning P20 (LSCLK) as the low-speed clock output Set P20MD bit (bit0 of P2MOD register) to “1” for specifying the low-speed clock output as the secondary function of P20. Register name P2MOD register (Address: 0F214H) P23MD P22MD...

  • Page 133: Functioning P36 (Lsclk) As The Low-Speed Clock Output

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 6 Clock Generation Circuit 6.4.3 Functioning P36 (LSCLK) as the low-speed clock output Set P36MD1 bit (bit6 of P3MOD1 register) to “0” and Set P36MD0 bit (bit6 of P3MOD0 register) to “1”for specifying the low-speed clock output as the secondary function of P36. Register name P3MOD1 register (Address: 0F21DH) Bit name...

  • Page 134: Time Base Counter

    Chapter 7 Time Base Counter ...

  • Page 135: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 7 Time Base Counter Time Base Counter 7.1 General Description This LSI includes a low-speed time base counter (LTBC) that generate base clocks for peripheral circuits and periodical interrupts. For the input clock, see Chapter 6, “Clock Generation Circuit”. For interrupt permission, interrupt request flags, etc.

  • Page 136: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 7 Time Base Counter 7.2 Description of Registers 7.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Low-speed time base counter ⎯ 0F060H LTBR register Low-speed time base counter 0F062H LTBADJL 8/16 frequency adjustment register 0 LTBADJ Low-speed time base counter...

  • Page 137: Low-Speed Time Base Counter (Ltbr)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter (LTBR) Address: 0F060H Access: R/W Access size: 8 bits Initial value: 00H LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ Initial value LTBR is a special function register (SFR) to read the T128HZ-T1HZ outputs of the low-speed time base counter. The T128HZ-T1HZ outputs are set to “0”...

  • Page 138: Low-Speed Time Base Counter Frequency Adjustment Registers (Ltbadj)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 7 Time Base Counter 7.2.3 Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJ) Address: 0F062H(LTBADJL), 0F063H(LTBADJH) Access: R/W Access size: 8/16 bits Initial value: 0000H LTBADJL LADJ7 LADJ6 LADJ5 LADJ4 LADJ3 LADJ2 LADJ1 LADJ0 Initial value ⎯...
  • Page 139 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 7 Time Base Counter The adjustment values (LADJ10 to LADJ0) to be set in LTBADJH and LTBADJL can be obtained by using the following equations: Adjustment value = Frequency adjustment ratio × 2097152 (decimal) = Frequency adjustment ratio × 200000h (hexadecimal) Example 1: When adjusting +15.0ppm (gaining time) Adjustment value = +15.0ppm ×...

  • Page 140: Low-Speed Time Base Counter Interrupt Select Registers (Ltbint)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 7 Time Base Counter 7.2.4 Low-Speed Time Base Counter Interrupt select Registers (LTBINT) Address: 0F064H(LTBINTL), 0F065H(LTBINTH) Access: R/W Access size: 8/16 bits Initial value: 0630H ⎯ ⎯ LTBINTL LTI1S2 LTI1S1 LTI1S0 LTI0S2 LTI0S1 LTI0S0 Initial value ⎯...

  • Page 141: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 7 Time Base Counter 7.3 Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The T128HZ, T64HZ, T32HZ, T16HZ, T8HZ, T4HZ, T2HZ, and T1HZ outputs of LTBC are used as time base interrupts and an interrupt is requested on the falling edge of each output.
  • Page 142 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 7 Time Base Counter Figure 7-4 shows interrupt generation timing and reset timing of the time base counter output by writing to LTBR. LTBR Write T256HZ T128HZ T64HZ T32HZ T16HZ T16HZ T8HZ T4HZ T2HZ T1HZ Indicates interrupt timing Figure 7-4 Interrupt Timing and Reset Timing by Writing to LTBR FEUL620Q150A...

  • Page 143: 8Bit Timer

    Chapter 8 8bit Timer ...

  • Page 144: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8bit Timer 8.1 General Description This LSI includes two channels of 8-bit timers. For the input clock, see Chapter 6, “Clock Generation Circuit”. 8.1.1 Features • The timer interrupt (TMnINT, n=0 to 7) is generated when the values of timer counter register (TMnC) and timer data register (TMnD) coincide.

  • Page 145: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2 Description of Registers 8.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F300H Timer 0 data register TM0D 8/16 0FFH TM01D Timer 1 data register 0F301H TM1D 0FFH 0F310H Timer 0 counter register TM0C...

  • Page 146: Timer N Data Register (Tm0D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.2 Timer n Data Register (TM0D) Address: 0F300H Access: R/W Access size: 8 bits Initial value: 0FFH TM0D T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 Initial value TM0D is a special function register (SFR) to set the value to be compared with the timer n counter register (TM0C) value. [Note] Set TM0D when the timer stops(when T0STAT bit of TMSTAT0 register is “0”).

  • Page 147: Timer N Data Register (Tm1D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.3 Timer n Data Register (TM1D) Address: 0F300H Access: R/W Access size: 8 bits Initial value: 0FFH TM1D T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 Initial value TM1D is a special function register (SFR) to set the value to be compared with the timer n counter register (TM1C) value. [Note] Set TM1D when the timer stops(when T1STAT bit of TMSTAT0 register is “0”).

  • Page 148: Timer 0 Counter Register (Tm0C)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.4 Timer 0 Counter Register (TM0C) Address: 0F308H Access: R/W Access size: 8 bits Initial value: 00H TM0C T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 Initial value TM0C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM0C is performed, TM0C is set to “00H”.

  • Page 149: Timer 1 Counter Register (Tm1C)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.5 Timer 1 Counter Register (TM1C) Address: 0F309H Access: R/W Access size: 8 bits Initial value: 00H TM1C T1C7 T1C6 T1C5 T1C4 T1C3 T1C2 T1C1 T1C0 Initial value TM1C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM1C is performed, TM0C is set to “00H”.

  • Page 150: Timer 0 Control Register

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.6 Timer 0 Control Register Address: 0F320H Access: R/W Access size: 8 bits Initial value: 00H ― ― TM0CON T0OST T01M16 T0DIV2 T0DIV1 T0DIV0 T0CS0 Initial value TM0CON is a special function register (SFR) to control timer 0. Write the TM0CON after clearing the TM0C when the timer stops(when the T0STAT bit of TMSTAT0 register is “0”).

  • Page 151: Timer 1 Control Register

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.7 Timer 1 Control Register Address: 0F321H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― TM1CON T1OST T1DIV2 T1DIV1 T1DIV0 T10CS0 Initial value TM1CON is a special function register (SFR) to control timer 1. Write the TM1CON after clearing the TM1C when the timer stops(when the T1STAT bit of TMSTAT0 register is “0”).

  • Page 152: Timer Start Register 0 (Tmstr0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.8 Timer Start Register 0 (TMSTR0) Address: 0F330H Access: W Access size: 8 bits Initial value: 00H ― ― ― ― ― ― TMSTR0 T1RUN T0RUN Initial value TMSTR0 is a special function register (SFR) to control starting the count-up of timer 0 and timer 1. [Description of Bits] •...

  • Page 153: Timer Stop Register 0 (Tmstp0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.9 Timer Stop Register 0 (TMSTP0) Address: 0F332H Access: W Access size: 8 bits Initial value: 00H ― ― ― ― ― ― TMSTP0 T1STP T0STP Initial value TMSTP0 is a special function register (SFR) to control stopping the count-up of timer 0 and timer 1. [Description of Bits] •...

  • Page 154: Timer Status Register 0 (Tmstat0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.2.10 Timer Status Register 0 (TMSTAT0) Address: 0F334H Access: R Access size: 8 bits Initial value: 00H ― ― ― ― ― ― TMSTAT0 T1STAT T0STAT Initial value TMSTAT0 is a special function register (SFR) that shows the status of timer 0 and timer 1. [Description of Bits] •...

  • Page 155: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer 8.3 Description of operation The timer counters(TMnC) starts the falling edge of the timer clock(TnCK) that are selected by the Timer control register(TMnCON) when the TnRUN bit of timer n register0(TMSTR0) are set to 1. When the count value of TMnC and the timer data register (TMnD) coincide, timer interrupt (TMnINT) occurs on the next timer clock falling edge, TMnC are reset to “00H”...
  • Page 156 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 8 8bit Timer Figure 8-3 shows the one-shot timer mode operation timing diagram TnCK TnRUN TnSTP TnSTAT Write TMnC TMnC TMnD TMnINT (n=0〜1) Figure 8-3 One-Shot Timer Mode Operation Timing Diagram [Note] TnSTAT bit is automatically cleared when the data of TMnC and TMnD matches. FEUL620Q150A 8-13...

  • Page 157: 16Bit Timer

    Chapter 9 16bit Timer ...

  • Page 158: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9 16bit Timer 9.1 General Description This LSI includes four channels of 16-bit timers. For the input clock, see Chapter 6, “Clock Generation Circuit”. 9.1.1 Features • The timer interrupt (TMnINT, n=0 to 7) is generated when the values of timer counter register (TMHnCH,TMHnCL n=8,9,A,B) and timer data register (TMHnDH,TMHnDL) coincide.

  • Page 159: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2 Description of Registers 9.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F340H 16bit timer 8 data register L TMH8DL 0FFH TMH8D 0F341H 16bit timer 8 data register H TMH8DH 8/16 0FFH...

  • Page 160: 16Bit Timer 8 Data Register L,H (Tmh8Dl,H)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.2 16bit timer 8 data register L,H (TMH8DL,H) Address: 0F340H Access: R/W Access size: 8 bits Initial value: 0FFH TMH8DL TH8D7 TH8D6 TH8D5 TH8D4 TH8D3 TH8D2 TH8D1 TH8D0 Initial value Address: 0F341H Access: R/W Access size: 8 bits Initial value: 0FFH TMH8DH...

  • Page 161: 16Bit Timer 9 Data Register L,H (Tmh9Dl,H)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.3 16bit timer 9 data register L,H (TMH9DL,H) Address: 0F342H Access: R/W Access size: 8 bits Initial value: 0FFH TMH9DL TH9D7 TH9D6 TH9D5 TH9D4 TH9D3 TH9D2 TH9D1 TH9D0 Initial value Address: 0F343H Access: R/W Access size: 8 bits Initial value: 0FFH TMH9DH...

  • Page 162: 16Bit Timer A Data Register L,H (Tmhadl,H)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.4 16bit timer A data register L,H (TMHADL,H) Address: 0F344H Access: R/W Access size: 8 bits Initial value: 0FFH TMHADL THAD7 THAD6 THAD5 THAD4 THAD3 THAD2 THAD1 THAD0 Initial value Address: 0F345H Access: R/W Access size: 8 bits Initial value: 0FFH TMHADH...

  • Page 163: 16Bit Timer B Data Register L,H (Tmhbdl,H)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.5 16bit timer B data register L,H (TMHBDL,H) Address: 0F346H Access: R/W Access size: 8 bits Initial value: 0FFH TMHBDL THBD7 THBD6 THBD5 THBD4 THBD3 THBD2 THBD1 THBD0 Initial value Address: 0F347H Access: R/W Access size: 8 bits Initial value: 0FFH TMHBDH...

  • Page 164: 16Bit Timer 8 Counter Register L,H (Tmh8Cl,H)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.6 16bit timer 8 counter register L,H (TMH8CL,H) Address: 0F350H Access: R/W Access size: 8 bits Initial value: 00H TMH8CL TH8C7 TH8C6 TH8C5 TH8C4 TH8C3 TH8C2 TH8CH TH8CL Initial value Address: 0F351H Access: R/W Access size: 8 bits Initial value: 00H TMH8CH...

  • Page 165: 16Bit Timer 9 Counter Register L,H (Tmh9Cl,H)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.7 16bit timer 9 counter register L,H (TMH9CL,H) Address: 0F352H Access: R/W Access size: 8 bits Initial value: 00H TMH9CL TH9C7 TH9C6 TH9C5 TH9C4 TH9C3 TH9C2 TH9CH TH9CL Initial value Address: 0F353H Access: R/W Access size: 8 bits Initial value: 00H TMH9CH...

  • Page 166: 16Bit Timer A Counter Register L,H (Tmhacl,H)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.8 16bit timer A counter register L,H (TMHACL,H) Address: 0F354H Access: R/W Access size: 8 bits Initial value: 00H TMHACL THAC7 THAC6 THAC5 THAC4 THAC3 THAC2 THACH THACL Initial value Address: 0F355H Access: R/W Access size: 8 bits Initial value: 00H TMHACH...

  • Page 167: 16Bit Timer B Counter Register L,H (Tmhbcl,H)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.9 16bit timer B counter register L,H (TMHBCL,H) Address: 0F356H Access: R/W Access size: 8 bits Initial value: 00H TMHBCL THBC7 THBC6 THBC5 THBC4 THBC3 THBC2 THBCH THBCL Initial value Address: 0F357H Access: R/W Access size: 8 bits Initial value: 00H TMHBCH...

  • Page 168: 16Bit Timer 8 Control Register L,H (Tmh8Con)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.10 16bit timer 8 control register (TMH8CON) Address: 0F360H Access: R/W Access size: 8 bits Initial value: 00H － － TMH8CON TH8OST TH8DIV2 TH8DIV1 TH8DIV0 TH8CS1 TH8CS0 Initial value TMH8CON is a special function (SFR) to control the 16bit timer 8. Write the TMH8CON after clearing the TMH8CON when the timer stops(when the TH8STAT bit of TMHSTAT0 register is “0”).
  • Page 169 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.11 16bit timer 9 control register (TMH9CON) Address: 0F362H Access: R/W Access size: 8 bits Initial value: 00H － － TMH9CON TH9OST TH9DIV2 TH9DIV1 TH9DIV0 TH9CS1 TH9CS0 Initial value TMH9CON is a special function (SFR) to control the 16bit timer 9. Write the TMH9CON after clearing the TMH9CON when the timer stops(when the TH9STAT bit of TMHSTAT0 register is “0”).

  • Page 170: 16Bit Timer A Control Register L,H (Tmhacon)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.12 16bit timer A control register (TMHACON) Address: 0F364H Access: R/W Access size: 8 bits Initial value: 00H － TMHACON THAOST THANEG THADIV2 THADIV1 THADIV0 THACS1 THACS0 Initial value TMHACON is a special function (SFR) to control the 16bit timer A. Write the TMHACON after clearing the TMHACON when the timer stops(when the THASTAT bit of TMHSTAT0 register is “0”).

  • Page 171: 16Bit Timer B Control Register L,H (Tmhbcon)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.13 16bit timer B control register (TMHBCON) Address: 0F366H Access: R/W Access size: 8 bits Initial value: 00H － TMHBCON THBOST THBNEG THBDIV2 THBDIV1 THBDIV0 THBCS1 THBCS0 Initial value TMHBCON is a special function (SFR) to control the 16bit timer B. Write the TMHBCON after clearing the TMHBCON when the timer stops(when the THBSTAT bit of TMHSTAT0 register is “0”).

  • Page 172: 16Bit Timer Start Register 0 (Tmhstr0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.14 16bit timer start register 0 (TMHSTR0) Address: 0F370H Access: R/W Access size: 8 bits Initial value: 00H － － － － TMHSTR0 THBRUN THARUN TH9RUN TH8RUN Initial value TMHSTR0 is a special function (SFR) to control starting count of 16bit timer 8, 9, A and B. [Description of Bits] •...

  • Page 173: 16Bit Timer Stop Register 0 (Tmhstp0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.15 16bit timer stop register 0 (TMHSTP0) Address: 0F372H Access: R/W Access size: 8 bits Initial value: 00H － － － － TMHSTP0 THBSTP THASTP TH9STP TH8STP Initial value TMHSTR0 is a special function (SFR) to control stopping count of 16bit timer 8, 9, A and B. [Description of Bits] •...

  • Page 174: 16Bit Timer Status Register 0 (Tmhstat0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.2.16 16bit timer status register 0 (TMHSTAT0) Address: 0F374H Access: R/W Access size: 8 bits Initial value: 00H － － － － TMHSTAT0 THBSTAT THASTAT TH9STAT TH8STAT Initial value TMHSTAT0 is a special function (SFR) that shows status of 16bit timer 8, 9, A and B. [Description of Bits] •...

  • Page 175: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer 9.3 Description of operation The timer counters(TMHnC) starts the falling edge of the timer clock(THnCK) that are selected by the Timer control register(TMHnCON) when the THnRUN bit of timer n register0(TMHSTR0) are set to 1. When the count value of TMHnC and the timer data register (TMHnD) coincide, timer interrupt (TMHnINT) occurs on the next timer clock falling edge, TMHnC are reset to “0000H”...
  • Page 176 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 9 16bit Timer THnCK THnRUN THnSTP THnSTAT Write TMHnC TMMnCH,L XXXX 0000 0001 0002 0087 0088 0000 0001 TMHnDH,L 0088 TMHnINT (n=8,9,A,B) TMHmOUT (m=A,B) Reverse by starting Stopping the timer returns the logic of output the timer signal to the initial value.

  • Page 177: Watchdog Timer

    Chapter 10 Watchdog Timer ...

  • Page 178: General Description

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 10 Watchdog Timer 10 Watchdog Timer 10.1 General Description This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period, the watchdog timer requests a WDT interrupt (non-maskable interrupt).

  • Page 179: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 10 Watchdog Timer 10.2 Description of Registers 10.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value ⎯ Watchdog timer control register 0F00EH WDTCON ⎯ 0F00FH Watchdog timer mode register WDTMOD FEUL620Q150A 10-2...

  • Page 180: Watchdog Timer Control Register (Wdtcon)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 10 Watchdog Timer 10.2.2 Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: R/W Access size: 8 bits Initial value: 00H WDTCON WDP/d0 Initial value WDTCON is a special function register (SFR) to control the WDT counter. When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0.

  • Page 181: Watchdog Timer Mode Register (Wdtmod)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 10 Watchdog Timer 10.2.3 Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: R/W Access size: 8 bits Initial value: 02H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ WDTMOD WDT1 WDT0 Initial value WDTMOD is a special function register to set the overflow period of the watchdog timer. [Description of Bits] •...

  • Page 182: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 10 Watchdog Timer 10.3 Description of operation The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" when WDP is "1".
  • Page 183 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 10 Watchdog Timer Figure 10-2 shows an example of watchdog timer operation. Program Low-Speed Occurrence of Clock Start abnormality Oscillation RESET_S WDTMOD WDTMOD Setting Setting System reset Data: WDTCON Write WDTP Internal pointer Overflow WDT counter Occurrence of WDTINT WDTINT Occurrence of WDT reset...
  • Page 184 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 10 Watchdog Timer 10.3.1 Handling example when not using the watch dog timer WDT counter is a free-run counter that starts count-up automatically after the system reset released and the low-speed clock (LSCLK) starts oscillating. If the WDT counter gets overflow, the WDT non-maskable interrupt occurs and then a system reset occurs.

  • Page 185: Pwm

    Chapter 11 PWM...

  • Page 186: General Description

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11 PWM 11.1 General Description This LSI includes four channels of 16-bit PWM (Pulse Width Modulation). The PWM4 output (PWM4) is assigned to P20(Port 2), P34(Port 3), P43(Port 4), P64(Port 6) and P87(Port 8) as the tertiary function.

  • Page 187: Configuration

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.1.2 Configuration Figure 11-1 shows the configuration of PWM 4 and PWM5. PnNEG P20/PWM4 PnFLG Write PWnCH P34/PWM4 PWnINT Write PWnCL Output control circuit P43/PWM4 Emergency EMGINT stop control P00/PW45EV0 P64/PWM4 circuit P87/PWM4 Duty Period P32/PW45EV0 Port control...
  • Page 188 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM P20/PWM4 P34/PWM4 P43/PWM4 P64/PWM4 P87/PWM4 PmNEG P21/PWM5 P35/PWM5 P47/PWM5 P65/PWM5 P83/PWM5 PnNEG PnFLG PmFLG PWnINT Write PWnCH Write PWnCL Output control circuit Output control circuit Emergency EMGINT stop control P00/PW45EV0 circuit Period Duty delay1 delay2 Port control P32/PW45EV0...
  • Page 189 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM Figure 11-2 shows the configuration of PWM 6 and PWM7. PnNEG P22/PWM6 PnFLG Write PWnCH P53/PWM6 PWnINT Write PWnCL Output control circuit P60/PWM6 Emergency EMGINT stop control P01/PW67EV0 P66/PWM6 circuit P70/PWM6 Duty Period P33/PW67EV0 Port control match match...
  • Page 190 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM P22/PWM6 P53/PWM6 P60/PWM6 P66/PWM6 P70/PWM6 PmNEG P23/PWM7 P57/PWM7 P61/PWM7 P71/PWM7 PnNEG PnFLG PmFLG PWnINT Write PWnCH Write PWnCL Output control circuit Output control circuit Emergency EMGINT stop control P01/PW67EV0 circuit Period Duty delay1 delay2 Port control P33/PW67EV0 match...

  • Page 191: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.1.3 List of Pins Pin name Function P44/T0P4CK Used for an external clock input for PWM4. P45/T1P5CK Used for an external clock input for PWM5. P46/ T16CK0 Used for an external clock input for PWM6. P47/ T16CK1 Used for an external clock input for PWM7.

  • Page 192: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2 Description of Registers 11.2.1 List of Registers Address Name Symbol (Byte) Size Initial Symbol (Word) value 0F4A0H PWM4 period register L PW4PL 8/16 0FFH PW4P 0F4A1H PWM4 period register H PW4PH 0FFH 0F4A2H PWM4 duty register L PW4DL 8/16...
  • Page 193 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 0F4D5H PWM7 counter register H PW7CH 0F4D6H PWM7 control register 0 PW7CON0 8/16 PW7CON0W 0F4D7H PWM7 control register 1 PW7CON1 － 0F4D8H PWM7 control register 2 PW7CON2 0F4DAH PWM7 control register 3 PW7CON4 8/16 PW7CON4W 0F4DBH PWM7 control register 4...

  • Page 194: Pwm4 Period Registers (Pw4Pl, Pw4Ph)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.2 PWM4 period register (PW4PL, PW4PH) Address: 0F4A0H Access: R/W Access size: 8/16 bits Initial value: 0FFH PW4PL P4P7 P4P6 P4P5 P4P4 P4P3 P4P2 P4P1 P4P0 Initial value Address: 0F4A1H Access: R/W Access size: 8 bits Initial value: 0FFH PW4PH P4P15...

  • Page 195: Pwm4 Duty Registers (Pw4Dl, Pw4Dh)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.3 PWM4 duty register (PW4DL, PW4DH) Address: 0F4A2H Access: R/W Access size: 8/16 bits Initial value: 00H PW4DL P4D7 P4D6 P4D5 P4D4 P4D3 P4D2 P4D1 P4D0 Initial value Address: 0F4A3H Access: R/W Access size: 8 bits Initial value: 00H PW4DH P4D15...

  • Page 196: Pwm4 Counter Registers (Pw4Cl, Pw4Ch)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.4 PWM4 counter register (PW4CL, PW4CH) Address: 0F4A4H Access: R/W Access size: 8/16 bits Initial value: 00H PW4CL P4C7 P4C6 P4C5 P4C4 P4C3 P4C2 P4C1 P4C0 Initial value Address: 0F4A5H Access: R/W Access size: 8 bits Initial value: 00H PW4CH P4C15...

  • Page 197: Pwm4 Control Register 0 (Pw4Con0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.5 PWM4 control register 0 (PW4CON0) Address: 0F4A6H Access: R/W Access size: 8/16 bits Initial value: 00H PW4CON0 P4CLIG P4STPSEL P4INI P4NEG P4IS1 P4IS0 P4CS1 P4CS0 Initial value PW4CON0 is a special function register (SFR) to control the PWM4. [Description of Bits] •...
  • Page 198 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM • P4CS1, P4CS0 (bits 1, 0) The P4CS1 and P4CS0 bits are used to select the PWM4 operation clocks. LSCLK, OSCLK, or the external clock (P44/T0P4CK) can be selected. When the OSCLK is selected for the PWM4 clock, external triggers (external input start or clear) are sampled by the OSCLK.

  • Page 199: Pwm4 Control Register 1 (Pw4Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.6 PWM4 control register 1 (PW4CON1) Address: 0F4A7H Access: R/W Access size: 8 bits Initial value: 40H － － － － － PW4CON1 P4STAT P4FLG P4RUN Initial value PW4CON1 is a special function register (SFR) to control PWM4. [Description of Bits] •...

  • Page 200: Pwm4 Control Register 2 (Pw4Con2)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.7 PWM4 control register 2 (PW4CON2) Address: 0F4A8H Access: R/W Access size: 8/16 bits Initial value: 00H － PW4CON2 P45MD P4MD P4TGSEL P4STM1 P4STM0 P4TGE1 P4TGE0 Initial value PW4CON2 is a special function register (SFR) to control PWM4. [Description of Bits] •...
  • Page 201 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM • P4TGE1、P4TGE0 (bit 1, bit 0) P4TGE1 and P4TGE0 are used to select the trigger edge of PWM4 external input control. In the coupled mode (P45MD=1), this setting is also applied to the PWM5. P4TGE1 P4TGE0 Description...

  • Page 202: Pwm4 Control Register 3 (Pw4Con3)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.8 PWM4 control register 3 (PW4CON3) Address: 0F4A9H Access: R/W Access size: 8 bits Initial value: 10H － － － － PW4CON3 P4SDST P4DTMD P4SDE1 P4SDE0 Initial value PW4CON3 is a special function register (SFR) to control PWM4. [Description of Bits] •...

  • Page 203: Pwm4 Control Register 4 (Pw4Con4)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.9 PWM4 control register 4 (PW4CON4) Address: 0F4AAH Access: R/W Access size: 8/16 bits Initial value: 00H － － － － － － PW4CON4 P4T1SEL0 P4T0SEL0 Initial value PW4CON4 is a special function register (SFR) to control PWM4. [Description of Bits] •...

  • Page 204: Pwm4 Control Register 5 (Pw4Con5)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.10 PWM4 control register 5 (PW4CON5) Address: 0F4ABH Access: R/W Access size: 8 bits Initial value: 00H － － － － PW4CON5 P4T1S1 P4T1S0 P4T0S1 P4T0S0 Initial value PW4CON5 is a special function register (SFR) to control PWM4. [Description of Bits] •...

  • Page 205: Pwm4 Control Register 6 (Pw4Con6)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.11 PWM4 control register 6 (PW4CON6) Address: 0F4ACH Access: R/W Access size: 8 bits Initial value: 00H － － － － － PW4CON6 P4DIV2 P4DIV1 P4DIV0 Initial value PW4CON6 is a special function register (SFR) to control PWM4. [Description of Bits] • ...

  • Page 206: Pwm5 Period Registers (Pw5Pl, Pw5Ph)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.12 PWM5 period register (PW5PL, PW5PH) Address: 0F4B0H Access: R/W Access size: 8/16 bits Initial value: 0FFH PW5PL P5P7 P5P6 P5P5 P5P4 P5P3 P5P2 P5P1 P5P0 Initial value Address: 0F4B1H Access: R/W Access size: 8 bits Initial value: 0FFH PW5PH P5P15...

  • Page 207: Pwm5 Duty Registers (Pw5Dl, Pw5Dh)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.13 PWM5 duty register (PW5DL, PW5DH) Address: 0F4B2H Access: R/W Access size: 8/16 bits Initial value: 00H PW5DL P5D7 P5D6 P5D5 P5D4 P5D3 P5D2 P5D1 P5D0 Initial value Address: 0F4B3H Access: R/W Access size: 8 bits Initial value: 00H PW5DH P5D15...

  • Page 208: Pwm5 Counter Registers (Pw5Cl, Pw5Ch)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.14 PWM5 counter register (PW4CL, PW4CH) Address: 0F4B4H Access: R/W Access size: 8/16 bits Initial value: 00H PW5CL P5C7 P5C6 P5C5 P5C4 P5C3 P5C2 P5C1 P5C0 Initial value Address: 0F4B5H Access: R/W Access size: 8 bits Initial value: 00H PW5CH P5C15...

  • Page 209: Pwm5 Control Register 0 (Pw5Con0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.15 PWM5 control register 0 (PW5CON0) Address: 0F4B6H Access: R/W Access size: 8/16 bits Initial value: 00H PW5CON0 P5CLIG P5STPSEL P5INI P5NEG P5IS1 P5IS0 P5CS1 P5CS0 Initial value PW5CON0 is a special function register (SFR) to control the PWM5. [Description of Bits] •...
  • Page 210 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM • P5CS1, P5CS0 (bits 1, 0) The P5CS1 and P5CS0 bits are used to select the PWM5 operation clocks. LSCLK, OSCLK, or the external clock (P45/T1P5CK) can be selected. When the OSCLK is selected for the PWM5 clock, external triggers (external input start or clear) are sampled by the OSCLK.

  • Page 211: Pwm5 Control Register 1 (Pw5Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.16 PWM5 control register 1 (PW5CON1) Address: 0F4B7H Access: R/W Access size: 8 bits Initial value: 40H － － － － － PW5CON1 P5STAT P5FLG P5RUN Initial value PW5CON1 is a special function register (SFR) to control PWM5. [Description of Bits] •...

  • Page 212: Pwm5 Control Register 2 (Pw5Con2)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.17 PWM5 control register 2 (PW5CON2) Address: 0F4B8H Access: R/W Access size: 8/16 bits Initial value: 00H － － PW5CON2 P5MD P5TGSEL P5STM1 P5STM0 P5TGE1 P5TGE0 Initial value PW5CON2 is a special function register (SFR) to control PWM5. [Description of Bits] •...
  • Page 213 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM • P5TGE1、P5TGE0 (bit 1, bit 0) P5TGE1 and P5TGE0 are used to select the trigger edge of PWM5 external input control. In the coupled mode (P45MD=1), this bit is ignored. P5TGE1 P5TGE0 Description During the external input start mode During the external input clear mode (P5STM1,P5STM0 = ”01”...

  • Page 214: Pwm5 Control Register 4 (Pw5Con4)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.18 PWM5 control register 4 (PW5CON4) Address: 0F4BAH Access: R/W Access size: 8/16 bits Initial value: 00H － － － － － － PW5CON4 P5T1SEL0 P5T0SEL0 Initial value PW5CON4 is a special function register (SFR) to control PWM5. [Description of Bits] •...

  • Page 215: Pwm5 Control Register 5 (Pw5Con5)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.19 PWM5 control register 5 (PW5CON5) Address: 0F4BBH Access: R/W Access size: 8 bits Initial value: 00H － － － － PW5CON5 P5T1S1 P5T1S0 P5T0S1 P5T0S0 Initial value PW5CON5 is a special function register (SFR) to control PWM5. [Description of Bits] •...

  • Page 216: Pwm5 Control Register 6 (Pw5Con6)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.20 PWM5 control register 6 (PW5CON6) Address: 0F4BCH Access: R/W Access size: 8 bits Initial value: 00H － － － － － PW5CON6 P5DIV2 P5DIV1 P5DIV0 Initial value PW5CON6 is a special function register (SFR) to control PWM5. [Description of Bits] • ...

  • Page 217: Pwm6 Period Registers (Pw6Pl, Pw6Ph)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.21 PWM6 period register (PW6PL, PW6PH) Address: 0F4C0H Access: R/W Access size: 8/16 bits Initial value: 0FFH PW6PL P6P7 P6P6 P6P5 P6P4 P6P3 P6P2 P6P1 P6P0 Initial value Address: 0F4C1H Access: R/W Access size: 8 bits Initial value: 0FFH PW6PH P6P15...

  • Page 218: Pwm6 Duty Registers (Pw6Dl, Pw6Dh)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.22 PWM6 duty register (PW6DL, PW6DH) Address: 0F4C2H Access: R/W Access size: 8/16 bits Initial value: 00H PW6DL P6D7 P6D6 P6D5 P6D4 P6D3 P6D2 P6D1 P6D0 Initial value Address: 0F4C3H Access: R/W Access size: 8 bits Initial value: 00H PW6DH P6D15...

  • Page 219: Pwm6 Counter Registers (Pw6Cl, Pw6Ch)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.23 PWM6 counter register (PW6CL, PW6CH) Address: 0F4C4H Access: R/W Access size: 8/16 bits Initial value: 00H PW6CL P6C7 P6C6 P6C5 P6C4 P6C3 P6C2 P6C1 P6C0 Initial value Address: 0F4C5H Access: R/W Access size: 8 bits Initial value: 00H PW6CH P6C15...

  • Page 220: Pwm6 Control Register 0 (Pw6Con0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.24 PWM6 control register 0 (PW6CON0) Address: 0F4C6H Access: R/W Access size: 8/16 bits Initial value: 00H PW6CON0 P6CLIG P6STPSEL P6INI P6NEG P6IS1 P6IS0 P6CS1 P6CS0 Initial value PW6CON0 is a special function register (SFR) to control the PWM6. [Description of Bits] •...
  • Page 221 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM • P6CS1, P6CS0 (bits 1, 0) The P6CS1 and P6CS0 bits are used to select the PWM6 operation clocks. LSCLK, OSCLK, or the external clock (P46/T16CK0) can be selected. When the OSCLK is selected for the PWM6 clock, external triggers (external input start or clear) are sampled by the OSCLK.

  • Page 222: Pwm6 Control Register 1 (Pw6Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.25 PWM6 control register 1 (PW6CON1) Address: 0F4C7H Access: R/W Access size: 8 bits Initial value: 40H － － － － － PW6CON1 P6STAT P6FLG P6RUN Initial value PW6CON1 is a special function register (SFR) to control PWM6. [Description of Bits] •...

  • Page 223: Pwm6 Control Register 2 (Pw6Con2)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.26 PWM6 control register 2 (PW6CON2) Address: 0F4C8H Access: R/W Access size: 8/16 bits Initial value: 00H － PW6CON2 P67MD P6MD P6TGSEL P6STM1 P6STM0 P6TGE1 P6TGE0 Initial value PW6CON2 is a special function register (SFR) to control PWM6. [Description of Bits] •...
  • Page 224 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM • P6TGE1、P6TGE0 (bit 1, bit 0) P6TGE1 and P6TGE0 are used to select the trigger edge of PWM6 external input control. In the coupled mode (P67MD=1), this setting is also applied to the PWM7. P6TGE1 P6TGE0 Description...

  • Page 225: Pwm6 Control Register 3 (Pw6Con3)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.27 PWM6 control register 3 (PW6CON3) Address: 0F4C9H Access: R/W Access size: 8 bits Initial value: 10H － － － － PW6CON3 P6SDST P6DTMD P6SDE1 P6SDE0 Initial value PW6CON3 is a special function register (SFR) to control PWM6. [Description of Bits] •...

  • Page 226: Pwm6 Control Register 4 (Pw6Con4)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.28 PWM6 control register 4 (PW6CON4) Address: 0F4CAH Access: R/W Access size: 8/16 bits Initial value: 00H － － － － － － PW6CON4 P6T1SEL0 P6T0SEL0 Initial value PW6CON4 is a special function register (SFR) to control PWM6. [Description of Bits] •...

  • Page 227: Pwm6 Control Register 5 (Pw6Con5)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.29 PWM6 control register 5 (PW6CON5) Address: 0F4CBH Access: R/W Access size: 8 bits Initial value: 00H － － － － PW6CON5 P6T1S1 P6T1S0 P6T0S1 P6T0S0 Initial value PW6CON5 is a special function register (SFR) to control PWM6. [Description of Bits] •...

  • Page 228: Pwm6 Control Register 6 (Pw6Con6)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.30 PWM6 control register 6 (PW6CON6) Address: 0F4CCH Access: R/W Access size: 8 bits Initial value: 00H － － － － － PW6CON6 P6DIV2 P6DIV1 P6DIV0 Initial value PW6CON6 is a special function register (SFR) to control PWM6. [Description of Bits] • ...

  • Page 229: Pwm7 Period Registers (Pw7Pl, Pw7Ph)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.31 PWM7 period register (PW7PL, PW7PH) Address: 0F4D0H Access: R/W Access size: 8/16 bits Initial value: 0FFH PW7PL P7P7 P7P6 P7P5 P7P4 P7P3 P7P2 P7P1 P7P0 Initial value Address: 0F4B1H Access: R/W Access size: 8 bits Initial value: 0FFH PW7PH P7P15...

  • Page 230: Pwm7 Duty Registers (Pw7Dl, Pw7Dh)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.32 PWM7 duty register (PW7DL, PW7DH) Address: 0F4D2H Access: R/W Access size: 8/16 bits Initial value: 00H PW7DL P7D7 P7D6 P7D5 P7D4 P7D3 P7D2 P7D1 P7D0 Initial value Address: 0F4D3H Access: R/W Access size: 8 bits Initial value: 00H PW7DH P7D15...

  • Page 231: Pwm7 Counter Registers (Pw7Cl, Pw7Ch)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.33 PWM7 counter register (PW4CL, PW4CH) Address: 0F4D4H Access: R/W Access size: 8/16 bits Initial value: 00H PW7CL P7C7 P7C6 P7C5 P7C4 P7C3 P7C2 P7C1 P7C0 Initial value Address: 0F4D5H Access: R/W Access size: 8 bits Initial value: 00H PW7CH P7C15...

  • Page 232: Pwm7 Control Register 0 (Pw7Con0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.34 PWM7 control register 0 (PW7CON0) Address: 0F4D6H Access: R/W Access size: 8/16 bits Initial value: 00H PW7CON0 P7CLIG P7STPSEL P7INI P7NEG P7IS1 P7IS0 P7CS1 P7CS0 Initial value PW7CON0 is a special function register (SFR) to control the PWM7. [Description of Bits] •...
  • Page 233 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM • P7CS1, P7CS0 (bits 1, 0) The P7CS1 and P7CS0 bits are used to select the PWM7 operation clocks. LSCLK, OSCLK, or the external clock (P47/T16CK1) can be selected. When the OSCLK is selected for the PWM7 clock, external triggers (external input start or clear) are sampled by the OSCLK.

  • Page 234: Pwm7 Control Register 1 (Pw7Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.35 PWM7 control register 1 (PW7CON1) Address: 0F4D7H Access: R/W Access size: 8 bits Initial value: 40H － － － － － PW7CON1 P7STAT P7FLG P7RUN Initial value PW7CON1 is a special function register (SFR) to control PWM7. [Description of Bits] •...

  • Page 235: Pwm7 Control Register 2 (Pw7Con2)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.36 PWM7 control register 2 (PW7CON2) Address: 0F4D8H Access: R/W Access size: 8/16 bits Initial value: 00H － － PW7CON2 P7MD P7TGSEL P7STM1 P7STM0 P7TGE1 P7TGE0 Initial value PW7CON2 is a special function register (SFR) to control PWM7. [Description of Bits] •...
  • Page 236 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM • P7TGE1、P7TGE0 (bit 1, bit 0) P7TGE1 and P7TGE0 are used to select the trigger edge of PWM7 external input control. In the coupled mode (P67MD=1), this bit is ignored. P7TGE1 P7TGE0 Description During the external input start mode During the external input clear mode (P7STM1,P7STM0 = ”01”...

  • Page 237: Pwm7 Control Register 4 (Pw7Con4)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.37 PWM7 control register 4 (PW7CON4) Address: 0F4DAH Access: R/W Access size: 8/16 bits Initial value: 00H － － － － － － PW7CON4 P7T1SEL0 P7T0SEL0 Initial value PW7CON4 is a special function register (SFR) to control PWM7. [Description of Bits] •...

  • Page 238: Pwm7 Control Register 5 (Pw7Con5)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.38 PWM7 control register 5 (PW7CON5) Address: 0F4DBH Access: R/W Access size: 8 bits Initial value: 00H － － － － PW7CON5 P7T1S1 P7T1S0 P7T0S1 P7T0S0 Initial value PW7CON5 is a special function register (SFR) to control PWM7. [Description of Bits] •...

  • Page 239: Pwm7 Control Register 6 (Pw7Con6)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.2.39 PWM7 control register 6 (PW7CON6) Address: 0F4DCH Access: R/W Access size: 8 bits Initial value: 00H － － － － － PW7CON6 P7DIV2 P7DIV1 P7DIV0 Initial value PW7CON6 is a special function register (SFR) to control PWM7. [Description of Bits] • ...

  • Page 240: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3 Description of Operation The operation of PWM4 and PWM5 are categorized into six modes. For more details about each operation mode, see the section 11.3.1 to 11.3.6. P45MD P4DTMD PnMD Operation mode Description Repeat mode PWM4 and PWM5 repeats working independently.
  • Page 241 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM The Start/Stop/Clear controls of PWM4 and PWM5 are categorized into eleven modes. “P00 or P32/PW45EV0” and “P30 or P62/PW45EV1” are selectable for the external hardware control. For more details about each mode, see the section 11.3.7. PnSTM1 PnSTM0 PnTGE1...
  • Page 242 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM The operation of PWM6 and PWM7 are categorized into six modes. For more details about each operation mode, see the section 11.3.9 to 11.3.14. P67MD P7DTMD PnMD Operation mode Description Repeat mode PWM6 and PWM7 repeats working independently. in Single mode One shot mode PWM6 and PWM7 works in one shot (one period...
  • Page 243 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM The Start/Stop/Clear controls of PWM6 and PWM7 are categorized into eleven modes. “P01 or P33/PW67EV0” and “P31 or P63/PW67EV1” are selectable for the external hardware control. For more details about each mode, see the section 11.3.15. Operation mode Description PnSTM1...

  • Page 244: Pwm4 And Pwm5, Single Mode / Repeat Mode (P45Md="0", Pnmd="0")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.1 PWM4 and PWM5, Single mode / Repeat mode (P45MD=”0”, PnMD=”0”) The PWM counter registers (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWM clock (PnCK) that are selected by the PWMn control register 0 (PWnCON0) when the PnRUN bit of PWMn control register 1 (PWnCON1) is set to “1”...
  • Page 245 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the PnRUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-3 shows the operation timing of PWMn on the condition of single mode and repeat mode (P45MD=”0”, PnMD=”0”).

  • Page 246: Pwm4 And Pwm5, Single Mode / One Shot Mode (P45Md="0", Pnmd="1")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.2 PWM4 and PWM5, Single mode / One shot mode (P45MD=”0”, PnMD=”1”) The PWM counter registers (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWM clock (PnCK) that are selected by the PWMn control register 0 (PWnCON0) when the PnRUN bit of PWMn control register 1 (PWnCON1) is set to “1”...
  • Page 247 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the PnRUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. Figure 11-4 shows the operation timing of PWMn on the condition of single mode and repeat mode (P45MD=”0”, PnMD=”1”).

  • Page 248: Pwm4 And Pwm5, Coupled Mode (With No Dead-Time Specified) / Repeat Mode (P45Md="1", P4Dtmd="0", P4Md="0")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.3 PWM4 and PWM5, Coupled mode (with no dead-time specified) / Repeat mode (P45MD=”1”, P4DTMD=”0”, P4MD=”0”) The PWM4 counter registers (PW4CH, PW4CL) are set to an operating state (P4STAT is set to “1”) on the first falling edge of the PWM clock (P4CK) that are selected by the PWM4 control register 0 (PW4CON0) and the PWM4 control register 6 (PW4CON6) when the P4RUN bit of PWM4 control register 1 (PW4CON1) is set to “1”...
  • Page 249 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the P4RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-5 shows the operation timing of PWM4 and PWM5 on the condition of coupled mode with no dead-time specified (P45MD=”1”, P4DTMD=”0”) and repeat mode (P4MD=”0”).

  • Page 250: Pwm4 And Pwm5, Coupled Mode (With No Dead-Time Specified) / One Shot Mode (P45Md="1", P4Dtmd="0", P4Md="1")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.4 PWM4 and PWM5, Coupled mode (with no dead-time specified) / One shot mode (P45MD=”1”, P4DTMD=”0”, P4MD=”1”) The PWM4 counter registers (PW4CH, PW4CL) are set to an operating state (P4STAT is set to “1”) on the first falling edge of the PWM clock (P4CK) that are selected by the PWM4 control register 0 (PW4CON0) and the PWM4 control register 6 (PW4CON6) when the P4RUN bit of PWM4 control register 1 (PW4CON1) is set to “1”...
  • Page 251 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the P4RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-6 shows the operation timing of PWM4 and PWM5 on the condition of coupled mode with no dead-time specified (P45MD=”1”, P4DTMD=”0”) and one shot mode (P4MD=”1”).

  • Page 252: Pwm4 And Pwm5, Coupled Mode (With Dead-Time Specified) / Repeat Mode (P45Md="1", P4Dtmd="1", P4Md="0")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.5 PWM4 and PWM5, Coupled mode (with dead-time specified) / Repeat mode (P45MD=”1”, P4DTMD=”1”, P4MD=”0”) The PWM4 counter registers (PW4CH, PW4CL) are set to an operating state (P4STAT is set to “1”) on the first falling edge of the PWM clock (P4CK) that are selected by the PWM4 control register 0 (PW4CON0) and the PWM4 control register 6 (PW4CON6) when the P4RUN bit of PWM4 control register 1 (PW4CON1) is set to “1”...
  • Page 253 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM The period of the PWM4 signal (T ), the first half duration (T ) of the duty, the duration of the PWM5 dead-time ) and the delay2(T ), are expressed by the following equations. PWD2 PW4P + 1 P4CK (Hz)
  • Page 254 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the P4RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-7 shows the operation timing of PWM4 and PWM5 on the condition of coupled mode with dead-time specified (P45MD=”1”, P4DTMD=”1”) and repeat mode (P4MD=”0”).

  • Page 255: Pwm4 And Pwm5, Coupled Mode (With Dead-Time Specified) / One Shot Mode (P45Md="1", P4Dtmd="1", P4Md="1")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.6 PWM4 and PWM5, Coupled mode (with dead-time specified) / One shot mode (P45MD=”1”, P4DTMD=”1”, P4MD=”1”) The PWM4 counter registers (PW4CH, PW4CL) are set to an operating state (P4STAT is set to “1”) on the first falling edge of the PWM clock (P4CK) that are selected by the PWM4 control register 0 (PW4CON0) and the PWM4 control register 6 (PW4CON6) when the P4RUN bit of PWM4 control register 1 (PW4CON1) is set to “1”...
  • Page 256 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM The period of the PWM4 signal (T ), the first half duration (T ) of the duty, the duration of the PWM5 dead-time ) and the delay2(T ), are expressed by the following equations. PWD2 PW4P + 1 P4CK (Hz)
  • Page 257 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the P4RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-8 shows the operation timing of PWM4 and PWM5 on the condition of coupled mode with dead-time specified (P45MD=”1”, P4DTMD=”1”) and one shot mode (P4MD=”1”).

  • Page 258: Pwm4/Pwm5 Start/Stop/Clear Operation By The External Control

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.7 PWM4/PWM5 start/stop/clear operation by the external control The PWM counter registers (PWnCH, PWnCL) can be enabled to start, stop and clear with external triggering inputs, by setting PnSTM1 bit, PnSTM0 bit and PnTGSEL bit of PWMn control register 2 (PWnCON2). The external input is sampled with a clock to eliminate one clock or less pulse of noise.

  • Page 259: Software Start Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.7.1 Software Start Mode With the setting of PnSTM1="0" and PnSTM0="0", the PWM counter operates being controlled by the PnRUN bit only. The operation timing is similar to the ones shown in 11.3.1 to 11.3.6. 11.3.7.2 Software Start Mode or External Start Mode With the setting of PnSTM1="0"...
  • Page 260 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM PnTGE1=1, PnTGE0=0 When "L" level start and "H" level stop & clear are selected PnRUN P00, P32/PW45EV0 P30, P62/PW45EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to output the initial value while being paused When the initial value is output, the PnINI bit allows...

  • Page 261: External Input Start Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.7.3 External Input Start Mode With the setting of PnSTM1="1" and PnSTM0="0" on the PWMn control register 2 (PWnCON2), the PWM counter operates being controlled by the edge of the external input that is selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2).
  • Page 262 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM PnTGE1=1, PnTGE0=0 When falling-edge start and rising-edge stop & clear are selected PnRUN P00, P32/PW45EV0 P30, P62/PW45EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output Count up PWnCH/L 0000 0000...

  • Page 263: Software Start Or External Input Clear Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.7.4 Software Start or External Input Clear Mode With the setting of PnSTM1="1" and PnSTM0="1" on the PWMn control register 2 (PWnCON2), the PWM counter operates being controlled by the PnRUN bit. When there is no edge input on the external input selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2), the counter operates in the same way as the software start.
  • Page 264 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM PnTGE1=1, PnTGE0=0 When rising-edge clear is selected PnRUN P00, P32/PW45EV0 The PnINI bit allows selection of P30, P62/PW45EV1 the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to output the initial value while being paused When the initial value is output, the PnINI bit allows selection of the "H/L"...
  • Page 265 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM PnTGE1=1, PnTGE0=1 Both-edge clear selected PnRUN P00, P32/PW45EV0 P30, P62/PW45EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output Count up Count up Count up 0000 0000 0000 PWnCH/L 0000...

  • Page 266: Emergency Stop Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.8 Emergency Stop Operation Setting the P4SDE1 and P4SDE0 bits of the PWM4 control register 3 (PW4CON3) enables the emergency stop function with the external input that is selected by P4TGSEL. Note that the emergency stop function is valid only in the cooperation mode (P45MD=“1”).
  • Page 267 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM Emergency stop by P4SDE1=1, P4SDE0=1 (Both edges) P00, P32/PW45EV0 P30, P62/PW45EV1 PnRUN P4SDST PW4INT PnFLG PWnCH/L 0000 0000 Count up 0000 Count up 0000 Count up 0000 0000 stop & clear stop & clear Emergency Emergency The PnINI bit allows selection of...

  • Page 268: Pwm6 And Pwm6, Single Mode / Repeat Mode (P67Md="0", Pnmd="0")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.9 PWM6 and PWM7, Single mode / Repeat mode (P67MD=”0”, PnMD=”0”) The PWM counter registers (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWM clock (PnCK) that are selected by the PWMn control register 0 (PWnCON0) when the PnRUN bit of PWMn control register 1 (PWnCON1) is set to “1”...
  • Page 269 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the PnRUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-13 shows the operation timing of PWMn on the condition of single mode and repeat mode (P67MD=”0”, PnMD=”0”).

  • Page 270: Pwm6 And Pwm7, Single Mode / One Shot Mode (P67Md="0", Pnmd="1")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.10 PWM6 and PWM7, Single mode / One shot mode (P67MD=”0”, PnMD=”1”) The PWM counter registers (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWM clock (PnCK) that are selected by the PWMn control register 0 (PWnCON0) when the PnRUN bit of PWMn control register 1 (PWnCON1) is set to “1”...
  • Page 271 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the PnRUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. Figure 11-14 shows the operation timing of PWMn on the condition of single mode and repeat mode (P67MD=”0”, PnMD=”1”).

  • Page 272: Pwm6 And Pwm7, Coupled Mode (With No Dead-Time Specified) / Repeat Mode (P67Md="1", P6Dtmd="0", P6Md="0")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.11 PWM6 and PWM7, Coupled mode (with no dead-time specified) / Repeat mode (P67MD=”1”, P6DTMD=”0”, P6MD=”0”) The PWM6 counter registers (PW6CH, PW6CL) are set to an operating state (P6STAT is set to “1”) on the first falling edge of the PWM clock (P6CK) that are selected by the PWM6 control register 0 (PW6CON0) and the PWM6 control register 6 (PW6CON6) when the P6RUN bit of PWM6 control register 1 (PW6CON1) is set to “1”...
  • Page 273 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the P6RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-15 shows the operation timing of PWM6 and PWM7 on the condition of coupled mode with no dead-time specified (P67MD=”1”, P6DTMD=”0”) and repeat mode (P6MD=”0”).

  • Page 274: Pwm6 And Pwm7, Coupled Mode (With No Dead-Time Specified) / One Shot Mode (P67Md="1", P6Dtmd="0", P6Md="1")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.12 PWM6 and PWM7, Coupled mode (with no dead-time specified) / One shot mode (P67MD=”1”, P6DTMD=”0”, P6MD=”1”) The PWM6 counter registers (PW6CH, PW6CL) are set to an operating state (P6STAT is set to “1”) on the first falling edge of the PWM clock (P6CK) that are selected by the PWM6 control register 0 (PW6CON0) and the PWM6 control register 6 (PW6CON6) when the P6RUN bit of PWM6 control register 1 (PW6CON1) is set to “1”...
  • Page 275 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the P6RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-16 shows the operation timing of PWM6 and PWM7 on the condition of coupled mode with no dead-time specified (P67MD=”1”, P6DTMD=”0”) and one shot mode (P6MD=”1”).

  • Page 276: Pwm6 And Pwm7, Coupled Mode (With Dead-Time Specified) / Repeat Mode (P67Md="1", P6Dtmd="1", P6Md="0")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.13 PWM6 and PWM7, Coupled mode (with dead-time specified) / Repeat mode (P67MD=”1”, P6DTMD=”1”, P6MD=”0”) The PWM6 counter registers (PW6CH, PW6CL) are set to an operating state (P6STAT is set to “1”) on the first falling edge of the PWM clock (P6CK) that are selected by the PWM6 control register 0 (PW6CON0) and the PWM6 control register 6 (PW6CON6) when the P6RUN bit of PWM6 control register 1 (PW6CON1) is set to “1”...
  • Page 277 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM The period of the PWM6 signal (T ), the first half duration (T ) of the duty, the duration of the PWM7 dead-time ) and the delay2(T ), are expressed by the following equations. PWD2 PW6P + 1 P6CK (Hz)
  • Page 278 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the P6RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-17 shows the operation timing of PWM6 and PWM7 on the condition of coupled mode with dead-time specified (P67MD=”1”, P6DTMD=”1”) and repeat mode (P6MD=”0”).

  • Page 279: Pwm6 And Pwm7, Coupled Mode (With Dead-Time Specified) / One Shot Mode (P67Md="1", P6Dtmd="1", P6Md="1")

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.14 PWM6 and PWM7, Coupled mode (with dead-time specified) / One shot mode (P67MD=”1”, P6DTMD=”1”, P6MD=”1”) The PWM6 counter registers (PW6CH, PW6CL) are set to an operating state (P6STAT is set to “1”) on the first falling edge of the PWM clock (P6CK) that are selected by the PWM6 control register 0 (PW6CON0) and the PWM6 control register 6 (PW6CON6) when the P6RUN bit of PWM6 control register 1 (PW6CON1) is set to “1”...
  • Page 280 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM The period of the PWM6 signal (T ), the first half duration (T ) of the duty, the duration of the PWM7 dead-time ) and the delay2(T ), are expressed by the following equations. PWD2 PW6P + 1 P6CK (Hz)
  • Page 281 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM After the P6RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error of up to 1 clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from the second time is fixed. Figure 11-18 shows the operation timing of PWM6 and PWM7 on the condition of coupled mode with dead-time specified (P67MD=”1”, P6DTMD=”1”) and one shot mode (P6MD=”1”).

  • Page 282: Pwm6/Pwm7 Start/Stop/Clear Operation By The External Control

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.15 PWM6/PWM7 start/stop/clear operation by the external control The PWM counter registers (PWnCH, PWnCL) can be enabled to start, stop and clear with external triggering inputs, by setting PnSTM1 bit, PnSTM0 bit and PnTGSEL bit of PWMn control register 2 (PWnCON2). The external input is sampled with a clock to eliminate one clock or less pulse of noise.

  • Page 283: Software Start Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.15.1 Software Start Mode With the setting of PnSTM1="0" and PnSTM0="0", the PWM counter operates being controlled by the PnRUN bit only. The operation timing is similar to the ones shown in 11.3.9 to 11.3.14. 11.3.15.2 Software Start Mode or External Start Mode With the setting of PnSTM1="0"...
  • Page 284 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM PnTGE1=1, PnTGE0=0 When "L" level start and "H" level stop & clear are selected PnRUN P01, P33/PW67EV0 P31, P63/PW67EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to output the initial value while being paused When the initial value is output, the PnINI bit allows...

  • Page 285: External Input Start Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.15.3 External Input Start Mode With the setting of PnSTM1="1" and PnSTM0="0" on the PWMn control register 2 (PWnCON2), the PWM counter operates being controlled by the edge of the external input that is selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2).
  • Page 286 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM PnTGE1=1, PnTGE0=0 When falling-edge start and rising-edge stop & clear are selected PnRUN P01, P33/PW67EV0 P31, P63/PW67EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output Count up PWnCH/L 0000 0000...

  • Page 287: Software Start Or External Input Clear Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.15.4 Software Start or External Input Clear Mode With the setting of PnSTM1="1" and PnSTM0="1" on the PWMn control register 2 (PWnCON2), the PWM counter operates being controlled by the PnRUN bit. When there is no edge input on the external input selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2), the counter operates in the same way as the software start.
  • Page 288 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM PnTGE1=1, PnTGE0=0 When rising-edge clear is selected PnRUN P01, P33/PW67EV0 The PnINI bit allows selection of P31, P63/PW67EV1 the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to output the initial value while being paused When the initial value is output, the PnINI bit allows selection of the "H/L"...
  • Page 289 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM PnTGE1=1, PnTGE0=1 Both-edge clear selected PnRUN P01, P33/PW67EV0 P31, P63/PW67EV1 The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output Count up Count up Count up 0000 0000 0000 PWnCH/L 0000...

  • Page 290: Emergency Stop Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM 11.3.16 Emergency Stop Operation Setting the P6SDE1 and P6SDE0 bits of the PWM6 control register 3 (PW6CON3) enables the emergency stop function with the external input that is selected by P6TGSEL. Note that the emergency stop function is valid only in the cooperation mode (P67MD=“1”).
  • Page 291 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 11 PWM Emergency stop by P6SDE1=1, P6SDE0=1 (Both edges) P01, P33/PW67EV0 P31, P63/PW67EV1 PnRUN Set PnRUN bit again Set PnRUN bit again P6SDST PW6INT PnFLG PWnCH/L 0000 0000 Count up 0000 Count up 0000 Count up 0000 0000 stop &...

  • Page 292: Chapter 12 Synchronous Serial Port

    Chapter 12 Synchronous Serial Port...

  • Page 293: Synchronous Serial Port (Ssio)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12 Synchronous Serial Port (SSIO) 12.1 General Description This LSI includes one channel of 8/16-bit synchronous serial ports (SSIO). It can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable pin. When the synchronous serial port is used, the tertiary functions of Port must be set.

  • Page 294: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.1.3 List of Pins Pin name Function Received data input. P40/SIN0 Used for the tertiary function of the P40 pins. Synchronous clock input/output. P41/SCK0 Used for the tertiary function of the P41 pins Transmitted data output.

  • Page 295: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2 Description of Registers 12.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value 0F700H Serial port 0 transmit/receive buffer L SIO0BUFL 8/16 SIO0BUF 0F701H Serial port 0 transmit/receive buffer H SIO0BUFH －...

  • Page 296: Serial Port 0 Transmit/Receive Buffers (Sio0Bufl, Sio0Bufh)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2.2 Serial Port 0 Transmit/Receive Buffers (SIO0BUFL and SIO0BUFH) Address: 0F700H Access: R/W Access size: 8 bits/16 bits Initial value: 00H S0B7 S0B6 S0B5 S0B4 S0B3 S0B2 S0B1 S0B0 SIO0BUFL Initial value Address: 0F701H Access: R/W Access size: 8-bit...

  • Page 297: Serial Port 0 Control Register (Sio0Con)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2.3 Serial Port 0 Control Register (SIO0CON) Address: 0F702H Access: R/W Access size: 8-bit Initial value: 00H SIO0CON — — — — — — — S0EN Initial value SIO0CON is a special function register (SFR) to control the synchronous serial port 0. [Description of Bits] •...

  • Page 298: Serial Port 0 Mode Register 0 (Sio0Mod0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2.4 Serial Port 0 Mode Register 0 (SIO0MOD0) Address: 0F704H Access: R/W Access size: 8-bit Initial value: 00H SIO0MOD0 — — — — S0LG S0MD1 S0MD0 S0DIR Initial value SIO0MOD0 is a special function register (SFR) to set mode of the synchronous serial port 0. [Description of Bits] •...

  • Page 299: Serial Port 0 Mode Register 1 (Sio0Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2.5 Serial Port 0 Mode Register 1 (SIO0MOD1) Address: 0F705H Access: R/W Access size: 8-bit Initial value: 00H SIO0MOD1 — — — S0CKT S0CK3 S0CK2 S0CK1 S0CK0 Initial value SIO0MOD1 is a special function register (SFR) to set mode of the synchronous serial port 0. [Description of Bits] •...

  • Page 300: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.3 Description of Operation 12.3.1 Transmit Operation When “1” is written to the S0MD1 bit and "0" is written to the S0MD0 bit of the serial port mode register (SIO0MOD0), this LSI is set to the transmit mode. When transmitted data is written to the serial port transmit/receive buffer (SIO0BUFL, "H") and the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission starts.

  • Page 301: Receive Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.3.2 Receive Operation When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial port mode register (SIO0MOD0), this LSI is set to a receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, reception starts.

  • Page 302: Transmit/Receive Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.3.3 Transmit/Receive Operation When “1” is written to the S0MD1 bit and "1" is written to the S0MD0 bit of the serial port mode register (SIO0MOD0), this LSI is set to the transmit/receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission/reception starts.

  • Page 303: Specifying Port Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.4 Specifying port registers To enable the SSIO0 function, the applicable bit of each related port register needs to be set. See Chapter 19, "Port 4", Chapter 20, "Port 5", Chapter 22, "Port 7" and Chapter 23, "Port 8" for detail about the port registers. 12.4.1 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input) as the SSIO0/ “Master mode”...

  • Page 304: Functioning P42 (Sout0: Output), P41 (Sck0: Input/Output), And P40 (Sin0: Input) As The Ssio0/ "Slave Mode

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.4.2 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input) as the SSIO0/ ”Slave mode” Set the P42MD1 to P40MD1 bits (P4MOD1 register bits 2 to 0) to “1” and the P42MD0 to P40MD0 bits (P4MOD0 register bits 2 to 0) to “0”...

  • Page 305: Uart

    Chapter 13 UART...

  • Page 306: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13 UART 13.1 General Description This LSI includes one channel of UART (Universal Asynchronous Receiver Transmitter), a full-duplex communication start-stop synchronous serial interface. This one full-duplex communication channel can be used as two independent half-duplex communication channels.
  • Page 307 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.1.3 List of Pins Pin name Function UART0 data input pin P02/RXD0 Used as the primary function of the P02 pin. UART0 data input pin P42/RXD0 Used as the secondary function of the P42 pin. UART0/1 data output pin P43/TXD0/TXD1 Used as the secondary or quartic function of the P43 pin.

  • Page 308: Uart0 Transmit/Receive Buffer (Ua0Buf)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.2 UART0 Transmit/Receive Buffer (UA0BUF) Address: 0F710H Access: R/W Access size: 8 bits Initial value: 00H UA0BUF U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 Initial value UA0BUF is a special function register (SFR) used to store the receive data in the full-duplex communication. It functions as a receive buffer in the full-duplex communication.

  • Page 309: Uart1 Transmit/Receive Buffer (Ua1Buf)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.3 UART1 Transmit/Receive Buffer (UA1BUF) Address: 0F718H Access: R/W Access size: 8 bits Initial value: 00H UA1BUF U1B7 U1B6 U1B5 U1B4 U1B3 U1B2 U1B1 U1B0 Initial value UA1BUF is a special function register (SFR) used to store the transmit data in the full-duplex communication. It functions as a transmit buffer in the full-duplex communication.

  • Page 310: Uart0 Control Register (Ua0Con)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.4 UART0 Control Register (UA0CON) Address: 0F711H Access: R/W Access size: 8 bits Initial value: 00H UA0CON — — — — — — — U0EN Initial value UA0CON is a special function register (SFR) used to start/stop communication of the UART. Description of bits •...

  • Page 311: Uart0 Mode Register 0 (Ua0Mod0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.6 UART0 Mode Register 0 (UA0MOD0) Address: 0F712H Access: R/W Access size: 8/16 bit Initial value: 00H UA0MOD0 U01HD U0RSS U0RSEL1 U0RSEL0 U0CK1 U0CK0 U0IO Initial value UA0MOD0 is a special function register (SFR) used to set the transfer mode of the UART. Description of bits •...
  • Page 312 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART • U0IO (bit 0) The U0IO bit is used to select transmit or receive mode. Be sure to set this bit to "1" in full-duplex communication. U0IO Description Transmit mode (initial value) Receive mode Enable/disable of registers depending on full/half-duplex communication mode setting Name Symbol (Byte)

  • Page 313: Uart1 Mode Register 0 (Ua1Mod0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.7 UART1 Mode Register 0 (UA1MOD0) Address: 0F71AH Access: R/W Access size: 8/16 bit Initial value: 00H UA1MOD0 U1RSS U1RSEL1 U1RSEL0 U1CK1 U1CK0 U1IO Initial value UA1MOD0 is a special function register (SFR) used to set the transfer mode of the UART. In full-duplex communication, this register is disabled.
  • Page 314 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART [Note] • Always set UA1MOD0 while communication is stopped, and do not rewrite it during communication. • When selecting the P52 pin as the received data input pin, it is necessary to configure settings for the Port 5 secondary functions.

  • Page 315: Uart0 Mode Register 1 (Ua0Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.8 UART0 Mode Register 1 (UA0MOD1) Address: 0F713H Access: R/W Access size: 8/16 bit Initial value: 00H UA0MOD1 U0DIR U0NEG U0STP U0PT1 U0PT0 U0LG1 U0LG0 Initial value UA0MOD1 is a special function register (SFR) used to set the transfer mode of the UART. Description of bits •...
  • Page 316 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART [Note] Always set UA0MOD1 while communication is stopped, and do not rewrite it during communication. FEUL620Q150A 13-1...

  • Page 317: Uart1 Mode Register 1 (Ua1Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.9 UART1 Mode Register 1 (UA1MOD1) Address: 0F71BH Access: R/W Access size: 8/16 bit Initial value: 00H UA1MOD1 U1DIR U1NEG U1STP U1PT1 U1PT0 U1LG1 U1LG0 Initial value UA1MOD1 is a special function register (SFR) used to set the transfer mode of the UART. In full-duplex communication, this register is disabled.
  • Page 318 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART [Note] Always set UA1MOD1 while communication is stopped, and do not rewrite it during communication. FEUL620Q150A 13-1...

  • Page 319: Uart0 Baud Rate Registers L, H (Ua0Brtl, Ua0Brth)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.10 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) Address: 0F714H Access: R/W Access size: 8/16 bit Initial value: 0FFH UA0BRTL U0BR7 U0BR6 U0BR5 U0BR4 U0BR3 U0BR2 U0BR1 U0BR0 Initial value Address: 0F715H Access: R/W Access size: 8 bits Initial value: 0FH UA0BRTH...

  • Page 320: Uart1 Baud Rate Registers L, H (Ua1Brtl, Ua1Brth)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.11 UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH) Address: 0F71CH Access: R/W Access size: 8/16 bit Initial value: 0FFH UA1BRTL U1BR7 U1BR6 U1BR5 U1BR4 U1BR3 U1BR2 U1BR1 U1BR0 Initial value Address: 0F71DH Access: R/W Access size: 8 bits Initial value: 0FH UA1BRTH...

  • Page 321: Uart0 Status Register (Ua0Stat)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.12 UART0 Status Register (UA0STAT) Address: 0F716H Access: R/W Access size: 8 bits Initial value: 00H UA0STAT U0FUL U0PER U0OER U0FER Initial value UA0STAT is a special function register (SFR) used to indicate the UART state in receive operations. When any data is written to UA0STAT, all the flags are initialized to "0".
  • Page 322 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART • U0FER (bit 0) The U0FER bit is used to indicate occurrence of a framing error of the UART. When an error occurs in the start or stop bit, this bit is set to "1". U0FER is updated each time reception is completed.

  • Page 323: Uart1 Status Register (Ua1Stat)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.2.13 UART1 Status Register (UA1STAT) Address: 0F71EH Access: R/W Access size: 8 bits Initial value: 00H UA1STAT U1FUL U1PER U1OER U1FER Initial value UA1STAT is a special function register (SFR) used to indicate the UART state in receive operations. When any data is written to UA1STAT, all the flags are initialized to "0".
  • Page 324 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART • U1FER (bit 0) The U1FER bit is used to indicate occurrence of a framing error of the UART. When an error occurs in the start or stop bit, this bit is set to "1". U1FER is updated each time reception is completed.

  • Page 325: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.3 Description of Operation 13.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can be selected as data bit.

  • Page 326: Baud Rate

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.3.2 Baud Rate Baud rates are generated by the baud rate generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (UnCK1, UnCK0) of the UARTn mode register 0 (UAnMOD0). The count value of the baud rate generator can be set by writing it in the UARTn baud rate register H or L (UAnBRTH, UAnBRTL).

  • Page 327: Transmit Data Direction

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.3.3 Transmitted Data Direction Figure 13-4 shows the relationship between the transmit/receive buffer and the transmit/receive data. Data length: 8 bits LSB transmission LSB reception U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 MSB transmission MSB reception Data length: 7 bits LSB reception...

  • Page 328: Transmit Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.3.4 Transmit Operation Transmission is started by setting the UnIO bit of the UARTn mode register 0 (UAnMOD0) to "0" to select the transmit mode and setting the UnEN bit of the UARTn control register (UAnCON) to "1". Figure 13-5 shows the operation timing for transmission.
  • Page 329 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART Figure 13-5 Operation Timing in Transmission FEUL620Q150A 13-2...

  • Page 330: Receive Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.3.5 Receive Operation Select the receive data pin using the UnRSEL bit of the UARTn mode register 0 (UAnMOD0). Reception is started by setting the UnIO bit of the UARTn mode register 0 (UAnMOD0) to "1" to select the receive mode and setting the UnEN bit of the UARTn control register (UAnCON) to "1".
  • Page 331 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART Figure 13-6 Operation Timing in Reception FEUL620Q150A 13-2...

  • Page 332: Detection Of Start Bit

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.3.5.1 Detection of Start Bit The start bit is sampled with the baud rate generator clock (HSCLK). Therefore, the start bit detection may be delayed for one cycle of the baud rate generator clock at the maximum. Figure 13-7 shows the start bit detection timing.

  • Page 333: Receive Margin

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.3.5.3 Receive Margin If there is an error between the sender baud rate and the baud rate generated by the baud rate generator of this LSI, the error accumulates until the last stop bit loading in one frame, decreasing the receive margin. Figure 13-9 shows the baud rate errors and receive margin waveforms.

  • Page 334: Specifying Port Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.4 Specifying Port Registers To enable the UART function, the applicable bit of each related port register needs to be set. See Chapter 15, "Port 0", Chapter 19, "Port 4", Chapter 20, "Port 5", Chapter 22, "Port 7", and Chapter 23, "Port 8" for details about the port registers.

  • Page 335: Functioning P43 (Txd1: Output) And P02 Pins (Rxd0: Input) As The Uart (Full-Duplex)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.4.2 Functioning P43 (TXD1: Output) and P02 pins (RXD0: Input) as the UART (Full-duplex) Set the P43MD1 bit (bit 3 of P4MOD1 register) to "1" and set the P43MD0 bit (bit 3 of P4MOD0 register) to "1", to specify the UART as the quartic function of P43.
  • Page 336 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART The P02 pin is an input-only pin and does not need input/output selection by the register. The set value ($) is arbitrary for the P02C1 and P02C0 bits. Select an arbitrary input mode depending on the state of the external circuit to which the P02 pin is connected.

  • Page 337: Functioning P85 (Txd1: Output) And P86 Pins (Rxd0: Input) As The Uart (Full-Duplex)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.4.3 Functioning P85 (TXD1: Output) and P86 pins (RXD0: Input) as the UART (Full-duplex) Set the P86MD1 to P85MD1 bits (bits 6 to 5 of P8MOD1 register) to "0", and set the P86MD0 to P85MD0 bits (bits 6 to 5 of P8MOD0 register) to "1", for specifying the UART as the secondary function of P86 and P85.

  • Page 338: Functioning P53 (Txd1: Output) And P03 Pins (Rxd1: Input) As The Uart (Half-Duplex)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.4.4 Functioning P53 (TXD1: Output) and P03 pins (RXD1: Input) as the UART (Half-duplex) Set the P53MD1 bit (bit 3 of P5MOD1 register) to "0" and set the P53MD0 bit (bit 3 of P5MOD0 register) to "1", to specify the UART as the secondary function of P53.
  • Page 339 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART The P03 pin is an input-only pin and does not need input/output selection by the register. The set value ($) is arbitrary for the P03C1 and P03C0 bits. Select an arbitrary input mode depending on the state of the external circuit to which the P03 pin is connected.

  • Page 340: Functioning P55 (Txd0: Output) And P42 Pins (Rxd0: Input) As The Uart (Half-Duplex)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.4.5 Functioning P55 (TXD0: Output) and P42 pins (RXD0: Input) as the UART (Half-duplex) Set the P55MD1 bit (bit 5 of P5MOD1 register) to "1" and set the P55MD0 bit (bit 5 of P5MOD0 register) to "1", to specify the UART as the secondary function of P55.
  • Page 341 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART Set the P42MD1 bit (bit 2 of P4MOD1 register) to "0" and set the P42MD0 bit (bit 2 of P4MOD0 register) to "1", to specify the UART as the secondary function of P42. Register name P4MOD1 register (Address: 0F249H) P47MD1 P46MD1...

  • Page 342: Functioning P43 (Txd0: Output) And P54 Pins (Rxd0: Input) As The Uart (Half-Duplex)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.4.6 Functioning P43 (TXD0: Output) and P54 pins (RXD0: Input) as the UART (Half-duplex) Set the P43MD1 bit (bit 3 of P4MOD1 register) to "0" and set the P43MD0 bit (bit 3 of P4MOD0 register) to "1", to specify the UART as the secondary function of P43.
  • Page 343 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART Set the P54MD1 bit (bit 4 of P5MOD1 register) to "0" and set the P54MD0 bit (bit 4 of P5MOD0 register) to "1", to specify the UART as the secondary function of P54. Register name P5MOD1 register (address: 0F257H) P57MD1 P56MD1...

  • Page 344: Functioning P85 (Txd1: Output) And P72 Pins (Rxd1: Input) As The Uart (Half-Duplex)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART 13.4.7 Functioning P85 (TXD1: Output) and P72 pins (RXD1: Input) as the UART (Half-duplex) Set the P85MD1 bit (bit 5 of P8MOD1 register) to "0", and set the P85MD0 bit (bit 5 of P8MOD0 register) to "1", for specifying the UART as the secondary function of P85.
  • Page 345 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 13 UART Set the P72MD1 bit (bit 2 of P7MOD1 register) to "0" and set the P72MD0 bit (bit 2 of P7MOD0 register) to "1", to specify the UART as the secondary function of P72. Register name P7MOD1 register (Address: 0F273H) P74MD1 P73MD1...

  • Page 346: I C Bus Interface

    Chapter 14 I C Bus Interface...

  • Page 347: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14 I C Bus Interface 14.1 General Description This LSI includes 1 channel of I2C bus interface (master). The I C bus interface data I/O pin and the I C bus interface clock I/O pin are assigned as the secondary function of the ports 4, 5, 6, and port 8.

  • Page 348: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.1.3 List of Pins Pin name Description C bus interface data input/output pin. P40/SDA Used for the secondary function of the P40 pin. C bus interface clock input/output pin. P41/SCL Used for the secondary function of the P41 pin. C bus interface data input/output pin.

  • Page 349: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.2 Description of Registers 14.2.1 List of Registers Initial Address Name Symbol (Word) Symbol (Byte) Size value 0F740H I2C0RD 0000Ｈ － C bus 0 receive register － － － 0F741H 0F742H I2C0SA 0000Ｈ...
  • Page 350 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.2.2 I C Bus 0 Receive Data Register (I2C0RD) Address: 0F740H Access: R Access size: 8 bits Initial value: 00H I2C0RD I20R7 I20R6 I20R5 I20R4 I20R3 I20R2 I20R1 I20R0 Initial value － －...

  • Page 351: I 2 C Bus 0 Slave Address Register (I2C0Sa)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.2.3 I C Bus 0 Slave Address Register (I2C0SA) Address: 0F742H Access: R/W Access size: 8 bits Initial value: 0000H I2C0SA I20A6 I20A5 I20A4 I20A3 I20A2 I20A1 I20A0 I20RW Initial value I2C0SA is a special function register (SFR) to set the address and the transmit/receive mode of the slave device. [Description of Bits] •...

  • Page 352: I 2 C Bus 0 Transmit Data Register (I2C0Td)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.2.4 I C Bus 0 Transmit Data Register (I2C0TD) Address: 0F744H Access: R/W Access size: 8 bits Initial value: 00H I2C0TD0 I20T7 I20T6 I20T5 I20T4 I20T3 I20T2 I20T1 I20T0 Initial value I2C0TD is a special function register (SFR) used to set the transmitted data. [Description of Bits] •...

  • Page 353: I 2 C Bus 0 Control Register (I2C0Con)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.2.5 I C Bus 0 Control Register (I2C0CON) Address: 0F746H Access: R/W Access size: 16/8 bits Initial value: 0000H I2C0CON0 I20ACT I20RS I20SP I20ST Initial value I2C0CON1 Initial value I2C0CON is a special function register (SFR) to control transmit and receive operations. [Description of Bits] •...

  • Page 354: I 2 C Bus 0 Mode Register (I2C0Mod)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.2.6 I C Bus 0 Mode Register (I2C0MOD) Address: 0F748H Access: R/W Access size: 16/8 bits Initial value: 0200H I2C0MODL — — — — I20DW1 I20DW0 I20MD I20EN Initial value I2C0MODH I20CD1 I20CD0 Initial value I2C00MOD is a special function register (SFR) used to set the operation mode.
  • Page 355 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface I20MD Description Standard mode (initial value)/100 kbps Fast mode/400 kbps • I20EN (bit 0) The I20EN bit is used to enable the operation of the I C bus interface. Only when I20EN is “1”, the I20ST bit can be set and the I2C0 bus becomes available.

  • Page 356: I 2 C Bus 0 Status Register (I2C0Stat)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.2.7 I C Bus 0 Status Register (I2C0STAT) Address: 0F74AH Access: R Access size: 16/8 bits Initial value: 0000H I2C0STAL I20ER I20ACR I20BB Initial value Initial value I2C0STAT is a read-only special function register (SFR) to indicate the state of the I C bus interface.

  • Page 357: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.3 Description of Operation 14.3.1 Communication Operation Mode Communication is started when communication mode is selected by using the I C bus 0 mode register (I2C0MOD), the C function is enabled by using the I20EN bit, a slave address and a data communication direction are set in the I C bus 0 slave address register (I2C0SA), and “1”...

  • Page 358: Communication Operation Timing

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.3.2 Communication Operation Timing Figures 14-2 to 14-4 show the operation timing and control method for each communication mode. Start Stop Restart Reception of Reception of Transmission of condition condition condition acknowledg acknowledg acknowledgment ment...
  • Page 359 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface Figure 14-5 shows the operation timing and control method when an acknowledgment error occurs. Acknowledge error Register I2C0SA=”xxxxxxx0B” setting I2C0CON=”01H” I2C0CON=”02H” Value of I2C0SA I2C0INT I2nST Value of I2C0RD I2C0SA I2nACR Figure 14-5 Operation Suspend Timing at Occurrence of Acknowledgment Error When the values of the transmitted bit and the SDA pin do not coincide, the I2nER bit of the I C bus n status register (I2C0STAT) is set to “1”...

  • Page 360: Operation Waveforms

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.3.3 Operation Waveforms Figure 14-7 shows the operation waveforms of the SDA and SCL signals and the I2nBB flag. Table 15-2 shows the relationship between communication speeds and 1/m OSCLK clock counts. Start Restart Stop...

  • Page 361: Specifying Port Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 14 I2C Bus Interface 14.4 Specifying port registers When you want to make sure the I2C bus interface function is working, please check related port registers are specified. See Chapter 19, “Port 4” , Chapter 20, “Port 5” and Chapter 21, “Port 6” for detail about the port registers. 14.4.1 Functioning P41(SCL) and P40(SDA) as the I2C Set P41MD1-P40MD1 bits(bit1-bit0 of P4MOD1 register) to “0”...
  • Page 362 Chapter 15 Port 0...

  • Page 363: Port 0

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 15 Port 0 15.1 General Description ML620Q151A/ML620Q152A/ML620Q153A includes a 5-bit input/output port, Port 0 (P00 to P04). ML620Q154A/ML620Q155A/ML620Q156A includes a 6-bit input/output port, Port 0 (P00 to P05). ML620Q157A/ML620Q158A/ML620Q159A includes a 6-bit input/output port, Port 0 (P00 to P05). For details, see Section 1.3.2, "List of Pins".

  • Page 364: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 15.1.3 List of Pins Pin name Function P00/EXI0/ Input port, External 0 interrupt, PW45EV0 input PW45EV0 P01/EXI1/ Input port, External 1 interrupt, PW67EV0 input PW67EV0 P02/EXI2/ Input port, External 2 interrupt, UART0 data input (RXD0) RXD0 P03/EXI3/ Input port, External 3 interrupt, UART1 data input (RXD1)

  • Page 365: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 15.2 Description of Registers 15.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) Port 0 data register Depends on pin 0F20CH state 0F20EH Port 0 control register 0 P0CON0 8/16 P0CON 0F20FH...

  • Page 366: Port 0 Data Register (P0D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 15.2.2 Port 0 Data Register (P0D) Address: 0F20CH Access: R Access size: 8 bits Initial value: Depends on pin state — — P05D P04D P03D P02D P01D P00D Initial value P0D is a read-only special function register (SFR) used to read the pin level of Port 0. Description of bits •...

  • Page 367: Port 0 Control Registers 0, 1 (P0Con0, P0Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 15.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) Address: 0F20EH Access: R/W Access size: 8/16 bit Initial value: 00H — P0CON0 — P05C0 P04C0 P03C0 P02C0 P01C0 P00C0 Initial value Address: 0F20FH Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 368: External Interrupt Control Registers 0, 1 (Exicon0, Exicon1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 15.2.4 External Interrupt Control Register 0, 1 (EXICON0, EXICON1) Address: 0F038H Access: R/W Access size: 8 bits Initial value: 00H EXICON0 P31E0 P30E0 P05E0 P04E0 P03E0 P02E0 P01E0 P00E0 Initial value Address: 0F039H Access: R/W Access size: 8 bits Initial value: 00H...

  • Page 369: External Interrupt Control Register 2 (Exicon2)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 15.2.5 External Interrupt Control Register 2 (EXICON2) Address: 0F03AH Access: R/W Access size: 8 bits Initial value: 00H EXICON2 P31SM P30SM P05SM P04SM P03SM P02SM P01SM P00SM Initial value EXICON2 is a special function register (SFR) to select whether the Port 0 interrupt is with sampling or without sampling.
  • Page 370 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 P00SM Description Detects the input signal edge for P00 interrupt without sampling (initial value). Detects with sampling [Note] • In STOP mode, no sampling is performed regardless of the value set in P31SM to P30SM and P05SM to P00SM since the sampling clock of 16 kHz stops.

  • Page 371: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 15.3 Description of Operation For the pins of Port 00 to 05, the setting of port 0 control registers 0, 1 (P0CON0, P0CON1) allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. High-impedance input mode is selected at system reset.
  • Page 372 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 15 Port 0 When rising-edge interrupt mode with sampling is selected, the input level of P0n and P3m pins is checked at falling edges of T16KHz. If it is "H" twice consecutively, the interrupt condition is satisfied, and an interrupt request occurs at the timing of falling edge of SYSCLK after the second falling edge of T16KHz.
  • Page 373 Chapter 16 Port 1...

  • Page 374: Port 1

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 16 Port 1 16 Port 1 16.1 General Description This LSI includes a 3-bit input port, Port 1 (P12, P13, P14). Port 1 can have a low-speed crystal oscillation pin (32.768 kHz) as a secondary function. To use it as a low-speed crystal oscillation pin, it can be selected in Code-Option.

  • Page 375: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 16 Port 1 16.2 Description of Registers 16.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) Port 1 data register Depends on pin 0F21AH state 0F21BH Port 1 direction register P1DIR 0F21CH Port 1 control register 0 P1CON0 8/16...

  • Page 376: Port 1 Data Register (P1D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 16 Port 1 16.2.2 Port 1 Data Register (P1D) Address: 0F21AH Access: R/W Access size: 8 bits Initial value: Depends on pin state — — — P14D P13D P12D — — Initial value P1D is a read-only special function register (SFR) used to read the input level of the port 1 pin. Description of bits •...

  • Page 377: Port 1 Direction Register (P1Dir)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 16 Port 1 16.2.3 Port 1 Direction Register (P1DIR) Address: 0F21BH Access: R/W Access size: 8 bits Initial value: 18H — — — — P1DIR — P14DIR P13DIR — Initial value P1DIR is a special function register (SFR) to select the input/output mode of Port 1 (P14). The P12 pin is an input-only port, and the P13 pin is an I/O port.

  • Page 378: Port 1 Control Registers 0,1 (P1Con0, P1Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 16 Port 1 16.2.4 Port 1 Control Registers 0, 1 (P1CON0, P1CON1) Address: 0F21CH Access: R/W Access size: 8/16 bit Initial value: 10H P1CON0 — — — P14C0 P13C0 P12C0 — — Initial value Address: 0F21DH Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 379 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 16 Port 1 [Note] • Do not program ML620Q150A series with an application program code that sets P14IDR bit of P1DIR register to”0”. Because the program code is executed before µEASE accesses to ML620Q150A series, P14/TEST0 pin gets output mode and from then on, the LSI cannot enter the on-chip debug mode.

  • Page 380: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 16 Port 1 16.3 Description of Operation 16.3.1 Input Port Function For each pin of Port 1, one of high-impedance input mode, input mode with a pull-down resistor, and input mode with a pull-up resistor can be selected by setting the Port 1 control registers 0, 1 (P1CON0, P1CON1). At a system reset, high-impedance input mode is selected as the initial status.
  • Page 381 Chapter 17 Port 2...

  • Page 382: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 17 Port 2 17 Port 2 17.1 General Description This LSI includes a 4-bit output-only port, Port 2 (P20 to P23). Port 2 can output the low-speed clock (LSCLK) and high-speed clock (OUTCLK) as the secondary function, the PWM4 output (PWM4), PWM5 output (PWM5), timer A out (TMHAOUT), and timer B out (TMHBOUT) as the tertiary function, and the PWM6 output (PWM6) and PWM7 output (PWM7) as the quartic function.

  • Page 383: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 17 Port 2 17.2 Description of Registers 17.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F228H Port 2 data register 0F22AH Port 2 control register 0 P2CON0 8/16 P2CON 0F22BH Port 2 control register 1 P2CON1 0F22CH Port 2 mode register 0...

  • Page 384: Port 2 Data Register (P2D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 17 Port 2 17.2.2 Port 2 Data Register (P2D) Address: 0F228H Access: R/W Access size: 8 bits Initial value: 00H — — — — P23D P22D P21D P20D Initial value P2D is a special function register (SFR) to set the output value of the Port 2. The value of this register is output to the Port 2 pin.

  • Page 385: Port 2 Control Registers 0, 1 (P2Con0, P2Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 17 Port 2 17.2.3 Port 2 Control Registers 0, 1 (P2CON0, P2CON1) Address: 0F22AH Access: R/W Access size: 8/16 bit Initial value: 00H P2CON0 — — — — P23C0 P22C0 P21C0 P20C0 Initial value Address: 0F22BH Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 386 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 17 Port 2 Description P20C1 P20C0 P20 pin: High-impedance output (initial value) P20 pin: P-channel open drain output P20 pin: N-channel open drain output P20 pin: In CMOS output mode FEUL620Q150A 17-5...

  • Page 387: Port 2 Mode Register (P2Mod)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 17 Port 2 17.2.4 Port 2 Mode Register (P2MOD) Address: 0F22CH Access: R/W Access size: 8/16 bit Initial value: 00H P2MOD0 — — — — P23MD0 P22MD0 P21MD0 P20MD0 Initial value Address: 0F22DH Access: R/W Access size: 8 bits Initial value: 00H P2MOD1 —...
  • Page 388 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 17 Port 2 • P21MD0, P21MD1 (bit 1) The P21MD0 and P21MD1 bits are used to select the primary, secondary, or tertiary function of the P21 pin. Description P21MD1 P21MD0 General-purpose output port function/LED drive mode (initial value) High-speed clock output function (OUTCLK) PWM5 output (PWM5) Do not use...

  • Page 389: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 17 Port 2 17.3 Description of Operation 17.3.1 Output Port Function For each pin of Port 2, any one of high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, and CMOS output mode can be selected by setting the Port 2 control registers 0, 1 (P2CON0, P2CON1).
  • Page 390 Chapter 18 Port 3...

  • Page 391: Port 3

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18 Port 3 18.1 General Description ML620Q151A/ML620Q152A/ML620Q153A includes a 6-bit input/output port, Port 3 (P30 to P35). ML620Q154A/ML620Q155A/ML620Q156A includes a 7-bit input/output port, Port 3 (P30 to P36). ML620Q157A/ML620Q158A/ML620Q159A includes a 8-bit input/output port, port 3 (P30 to P37). For details, see Section 1.3.2, "List of Pins".

  • Page 392: Configuration

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18.1.2 Configuration Figure 18-1 shows the configuration of Port 3. Pull-up Data bus Pull-down Controller P3DIR P3MOD0,1 P3CON0,1 Port3 Output P30 to P37 PWM output (PWM4, PWM5) Controller LSCLK,OUTCLK PW45EV1,PW67EV1, PW45EV0,PW67EV0 AIN0 to AIN5 EXICON0 EXICON1 EXICON2...

  • Page 393: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18.1.3 List of Pins Pin name Primary function Secondary function Tertiary function I/O port, External 6 interrupt P30/EXI6 PW45EV1 input, PW45EV1/ Successive AIN0 approximation type ADC input I/O port, External 7 interrupt P31/EXI7 PW67EV1 input, PW67EV1/ Successive...

  • Page 394: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18.2 Description of Registers 18.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F236H Port 3 data register 0F237H Port 3 direction register P3DIR 0F238H Port 3 control register 0 P3CON0 8/16 P3CON...

  • Page 395: Port 3 Data Register (P3D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18.2.2 Port 3 Data Register (P3D) Address: 0F236H Access: R/W Access size: 8 bits Initial value: 00H P37D P36D P35D P34D P33D P32D P31D P30D Initial value P3D is a special function register (SFR) to set the value to be output to the Port 3 pin or to read the input level of the Port 3.
  • Page 396 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 P30D Description Output or input level of the P30 pin: "L" Output or input level of the P30 pin: "H" FEUL620Q150A 18-6...

  • Page 397: Port 3 Direction Register (P3Dir)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18.2.3 Port 3 Direction Register (P3DIR) Address: 0F237H Access: R/W Access size: 8 bits Initial value: 00H P3DIR P37DIR P36DIR P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Initial value P3DIR is a special function register (SFR) to select the input/output mode of Port 3. Description of bits •...

  • Page 398: Port 3 Control Registers 0, 1 (P3Con0, P3Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18.2.4 Port 3 Control Registers 0, 1 (P3CON0, P3CON1) Address: 0F238H Access: R/W Access size: 8/16 bit Initial value: 00H P3CON0 P37C0 P36C0 P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Initial value Address: 0F239H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 399 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 When output mode is selected (P35DIR bit When input mode is selected (P35DIR bit = "0") = "1") P35C1 P35C0 Description P35 pin: High-impedance output (initial P35 pin: High-impedance input value) P35 pin: P-channel open drain output P35 pin: Input with a pull-down resistor P35 pin: N-channel open drain output P35 pin: Input with a pull-up resistor...

  • Page 400: Port 3 Mode Registers 0, 1 (P3Mod0, P3Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18.2.5 Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1) Address: 0F23AH Access: R/W Access size: 8/16 bit Initial value: 00H P3MOD0 P37MD0 P36MD0 P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Initial value Address: 0F23BH Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 401 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 • P34MD1, P34MD0 (bits 4) The P34MD1 and P34MD0 bits are used to select the primary or tertiary function of the P34 pin. Description P34MD1 P34MD0 General-purpose output port function (initial value) Do not use PWM4 output pin (PWM4) Do not use •...

  • Page 402: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 18 Port 3 18.3 Description of Operation 18.3.1 Input/Output Port Functions For each pin of Port 3, either output or input is selected by setting the Port 3 direction register (P3DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 3 control registers 0, 1 (P3CON0, P3CON1).
  • Page 403 Chapter 19 Port 4...

  • Page 404: Port 4

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 19 Port 4 19.1 General Description This LSI includes a 8-bit input/output port, Port 4 (P40 to P47). Port 4 can have the PWM output, UART, synchronous serial port, and I C bus functions as the secondary, tertiary, or quartic function.

  • Page 405: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 19.1.3 List of Pins Pin name Primary function Secondary function Tertiary function Quartic function I/O port, P40/CMP0M/ C bus 0 data SSIO0 data Analogue comparator SDA/SIN0 I/O pin input pin 0 non-inverting input I/O port, P41/CMP0P/ C bus 0 clock...
  • Page 406 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 19.2 Description of Registers 19.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F244H Port 4 data register 0F245H Port 4 direction register P4DIR 0F246H Port 4 control register 0 P4CON0 8/16 P4CON...

  • Page 407: Port 4 Data Register (P4D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 19.2.2 Port 4 Data Register (P4D) Address: 0F244H Access: R/W Access size: 8 bits Initial value: 00H P47D P46D P45D P44D P43D P42D P41D P40D Initial value P4D is a special function register (SFR) to set the value to be output to the Port 4 pin or to read the input level of the Port 4.
  • Page 408 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 P40D Description Output or input level of the P40 pin: "L" Output or input level of the P40 pin: "H" FEUL620Q150A 19-5...

  • Page 409: Port 4 Direction Register (P4Dir)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 19.2.3 Port 4 Direction Register (P4DIR) Address: 0F245H Access: R/W Access size: 8 bits Initial value: 00H P4DIR P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Initial value P4DIR is a special function register (SFR) to select the input/output mode of Port 4. Description of bits •...

  • Page 410: Port 4 Control Registers 0, 1 (P4Con0, P4Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 19.2.4 Port 4 Control Registers 0, 1 (P4CON0, P4CON1) Address: 0F246H Access: R/W Access size: 8/16 bit Initial value: 00H P4CON0 P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Initial value Address: 0F247H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 411 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 Setting of P45 pin When output mode is selected (P45DIR When input mode is selected (P45DIR bit = bit = "0") "1") P45C1 P45C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...

  • Page 412: Port 4 Mode Registers 0, 1 (P4Mod0, P4Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 19.2.5 Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1) Address: 0F248H Access: R/W Access size: 8/16 bit Initial value: 00H P4MOD0 P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Initial value Address: 0F249H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 413 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 • P45MD1, P45MD0 (bit 5) The P45MD1 and P45MD0 bits are used to select the primary or tertiary function of the P45 pin. Description P45MD1 P45MD0 General-purpose input/output mode (initial value) Do not use SIO0 clock I/O pin (SCK0) Do not use •...
  • Page 414 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 • P40MD1, P40MD0 (bit 0) The P40MD1 and P40MD0 bits are used to select the primary, secondary, or tertiary function of the P40 pin. P40MD1 P40MD0 Description General-purpose input/output mode (initial value) C bus 0 data I/O pin (SDA) SIO0 data input pin (SIN0) Do not use [Note]...

  • Page 415: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 19 Port 4 19.3 Description of Operation 19.3.1 Input/Output Port Functions For each pin of Port 4, either output or input is selected by setting the Port 4 direction register (P4DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 4 control registers 0, 1 (P4CON0, P4CON1).
  • Page 416 Chapter 20 Port 5...

  • Page 417: Port 5

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 20 Port 5 20.1 General Description ML620Q151A/ML620Q152A/ML620Q153A includes a 4-bit input/output port, Port 5 (P54 to P57). ML620Q154A/ML620Q155A/ML620Q156A includes a 5-bit input/output port, Port 5 (P53 to P57). ML620Q157A/ML620Q158A/ML620Q159A includes a 8-bit input/output port, port 5 (P50 to P57). For details, see Section 1.3.2, "List of Pins".

  • Page 418: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 20.1.3 List of Pins Pin name Primary function Secondary Tertiary function Quartic function function P50/SDA/SIN0 I/O port C data SSIO0 data I/O (SDA) input pin P51/SCL/SCK0 I/O port C clock SSIO0 clock I/O (SCL) I/O pin P52/RXD1/SOUT0 I/O port...
  • Page 419 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 20.2 Description of Registers 20.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F252H Port 5 data register 0F253H Port 5 direction register P5DIR 0F254H Port 5 control register 0 P5CON0 8/16 P5CON...

  • Page 420: Port 5 Data Register (P5D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 20.2.2 Port 5 Data Register (P5D) Address: 0F252H Access: R/W Access size: 8 bits Initial value: 00H P57D P56D P55D P54D P53D P52D P51D P50D Initial value P5D is a special function register (SFR) to set the value to be output to the Port 5 pin or to read the input level of the Port 5.

  • Page 421: Port 5 Direction Register (P5Dir)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 20.2.3 Port 5 Direction Register (P5DIR) Address: 0F253H Access: R/W Access size: 8 bits Initial value: 00H P5DIR P57DIR P56DIR P55DIR P54DIR P53DIR P52DIR P51DIR P50DIR Initial value P5DIR is a special function register (SFR) to select the input/output mode of Port 5. Description of bits •...

  • Page 422: Port 5 Control Registers 0, 1 (P5Con0, P5Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 20.2.4 Port 5 Control Registers 0, 1 (P5CON0, P5CON1) Address: 0F254H Access: R/W Access size: 8/16 bit Initial value: 00H P5CON0 P57C0 P56C0 P55C0 P54C0 P53C0 P52C0 P51C0 P50C0 Initial value Address: 0F255H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 423 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 Setting of P54 pin When output mode is selected (P54DIR When input mode is selected (P54DIR bit = bit = "0") "1") P54C1 P54C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...

  • Page 424: Port 5 Mode Registers 0, 1 (P5Mod0, P5Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 20.2.5 Port 5 Mode Registers 0, 1 (P5MOD0, P5MOD1) Address: 0F256H Access: R/W Access size: 8/16 bit Initial value: 00H P5MOD0 P57MD0 P56MD0 P55MD0 P54MD0 P53MD0 P52MD0 P51MD0 P50MD0 Initial value Address: 0F257H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 425 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 • P54MD1, P54MD0 (bit 4) The P54MD1 and P54MD0 bits are used to select the primary or secondary function of the P54 pin. P54MD1 P54MD0 Description General-purpose input/output mode (initial value) UART0 data input pin (RXD0) Do not use Do not use •...
  • Page 426 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 [Note] When the pin is set to "Do not use" and the output mode is selected (by the Port 5 control register), the Port 5 output pin state is fixed as follows regardless of the data of the port data register P5D: When high-impedance output is selected: Output pin is high-impedance When P-channel open drain output is selected: Output pin is high-impedance When N-channel open drain output is selected: Output pin is fixed to "L"...

  • Page 427: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 20 Port 5 20.3 Description of Operation 20.3.1 Input/Output Port Functions For each pin of Port 5, either output or input is selected by setting the Port 5 direction register (P5DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 5 control registers 0, 1 (P5CON0, P5CON1).
  • Page 428 Chapter 21 Port 6...

  • Page 429: Port 6

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 21 Port 6 21.1 General Description ML620Q151A/ML620Q152A/ML620Q153A includes a 4-bit input/output port, Port 6 (P60 to P63). ML620Q154A/ML620Q155A/ML620Q156A includes a 5-bit input/output port, Port 6 (P60 to P64). ML620Q157A/ML620Q158A/ML620Q159A includes a 8-bit input/output port, port 6 (P60 to P67). For details, see Section 1.3.2, "List of Pins".

  • Page 430: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 21.1.3 List of Pins Pin name Primary function Secondary Tertiary function Quartic function function P60/SDA/ C data Timer A out I/O port PWM6 output TMHAOUT/PWM6 I/O (SDA) (TMHAOUT) P61/SCL/ C clock Timer B out I/O port PWM7 output TMHBOUT/PWM7...
  • Page 431 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 21.2 Description of Registers 21.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F260H Port 6 data register 0F261H Port 6 direction register P6DIR 0F262H Port 6 control register 0 P6CON0 8/16 P6CON...

  • Page 432: Port 6 Data Register (P6D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 21.2.2 Port 6 Data Register (P6D) Address: 0F260H Access: R/W Access size: 8 bits Initial value: 00H P67D P66D P65D P64D P63D P62D P61D P60D Initial value P6D is a special function register (SFR) to set the value to be output to the Port 6 pin or to read the input level of the Port 6. In output mode, the value of this register is output to the Port 6 pin.

  • Page 433: Port 6 Direction Register (P6Dir)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 21.2.3 Port 6 Direction Register (P6DIR) Address: 0F261H Access: R/W Access size: 8 bits Initial value: 00H P6DIR P67DIR P66DIR P65DIR P64DIR P63DIR P62DIR P61DIR P60DIR Initial value P6DIR is a special function register (SFR) to select the input/output mode of Port 6. Description of bits •...

  • Page 434: Port 6 Control Registers 0, 1 (P6Con0, P6Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 21.2.4 Port 6 Control Registers 0, 1 (P6CON0, P6CON1) Address: 0F262H Access: R/W Access size: 8/16 bit Initial value: 00H P6CON0 P67C0 P66C0 P65C0 P64C0 P63C0 P62C0 P61C0 P60C0 Initial value Address: 0F263H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 435 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 Setting of P65 pin When output mode is selected (P65DIR When input mode is selected (P65DIR bit bit = "0") = "1") P65C1 P65C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...

  • Page 436: Port 6 Mode Registers 0, 1 (P6Mod0, P6Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 21.2.5 Port 6 Mode Registers 0, 1 (P6MOD0, P6MOD1) Address: 0F264H Access: R/W Access size: 8/16 bit Initial value: 00H P6MOD0 P66MD0 P65MD0 P64MD0 P61MD0 P60MD0 Initial value Address: 0F265H Access: R/W Access size: 8/16 bit Initial value: 00H P6MOD1 P66MD1...
  • Page 437 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 • P61MD1, P61MD0 (bit 1) The P61MD1 and P61MD0 bits are used to select the primary, secondary, tertiary, or quartic function of the P61 pin. Description P61MD1 P61MD0 General-purpose input/output mode (initial value) C communication clock I/O pin (SCL) Timer B out output function (TMHBOUT) PWM7 output pin (PWM7)

  • Page 438: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 21 Port 6 21.3 Description of Operation 21.3.1 Input/Output Port Functions For each pin of Port 6, either output or input is selected by setting the Port 6 direction register (P6DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 6 control registers 0, 1 (P6CON0, P6CON1).
  • Page 439 Chapter 22 Port 7...

  • Page 440: Port 7

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 22 Port 7 22.1 General Description ML620Q157A/ML620Q158A/ML620Q159A includes a 5-bit input/output port, port 7 (P70 to P74). ML620Q151A/ML620Q152A/ML620Q153A/ML620Q154A/ML620Q155A/ML620Q156A do not include the port 7. For details, see Section 1.3.2, "List of Pins". 22.1.1 Features •...

  • Page 441: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 22.1.3 List of Pins Pin name Primary function Secondary function Tertiary function Quartic function P70/PWM6 I/O port PWM6 output P71/PWM7 I/O port PWM7 output P72/RXD1/SIN0 I/O port UART1 data input SSIO0 data input P73/TXD1/SCK0/TXD0 I/O port UART1 data output...

  • Page 442: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 22.2 Description of Registers 22.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F26EH Port 7 data register 0F26FH Port 7 direction register P7DIR 0F270H Port 7 control register 0 P7CON0 8/16 P7CON...

  • Page 443: Port 7 Data Register (P7D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 22.2.2 Port 7 Data Register (P7D) Address: 0F26EH Access: R/W Access size: 8 bits Initial value: 00H P74D P73D P72D P71D P70D Initial value P7D is a special function register (SFR) to set the value to be output to the Port 7 pin or to read the input level of the Port 7. In output mode, the value of this register is output to the Port 7 pin.

  • Page 444: Port 7 Direction Register (P7Dir)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 22.2.3 Port 7 Direction Register (P7DIR) Address: 0F26FH Access: R/W Access size: 8 bits Initial value: 00H P7DIR P74DIR P73DIR P72DIR P71DIR P70DIR Initial value P7DIR is a special function register (SFR) to select the input/output mode of Port 7. Description of bits •...

  • Page 445: Port 7 Control Registers 0, 1 (Pccon0, Pccon1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 22.2.4 Port 7 Control Registers 0, 1 (P7CON0, P7CON1) Address: 0F270H Access: R/W Access size: 8/16 bit Initial value: 00H P7CON0 P74C0 P73C0 P72C0 P71C0 P70C0 Initial value Address: 0F271H Access: R/W Access size: 8 bits Initial value: 00H P7CON1 P74C1...
  • Page 446 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 Setting of P71 pin When output mode is selected (P71DIR When input mode is selected (P71DIR bit bit = "0") = "1") P71C1 P71C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...

  • Page 447: Port 7 Mode Registers 0, 1 (P7Mod0, P7Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 22.2.5 Port 7 Mode Registers 0, 1 (P7MOD0, P7MOD1) Address: 0F272H Access: R/W Access size: 8/16 bit Initial value: 00H P7MOD0 P74MD0 P73MD0 P72MD0 P71MD0 P70MD0 Initial value Address: 0F273H Access: R/W Access size: 8 bits Initial value: 00H P7MOD1 P74MD1...
  • Page 448 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 • P71MD1, P71MD0 (bit 1) The P71MD1 and P71MD0 bits are used to select the primary, secondary, or tertiary function of the P71 pin. Description P71MD1 P71MD0 General-purpose output port function (initial value) Do not use PWM7 output (PWM7) Do not use...

  • Page 449: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 22 Port 7 22.3 Description of Operation 22.3.1 Input/Output Port Functions For each pin of Port 7, either output or input is selected by setting the Port 7 direction register (P7DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 7 control registers 0, 1 (P7CON0, P7CON1).
  • Page 450 Chapter 23 Port 8...

  • Page 451: Port 8

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 23 Port 8 23.1 General Description This LSI includes a 8-bit input/output port, Port 8 (P80 to P87). 23.1.1 Features • Allows selection of high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output for each bit in output mode.

  • Page 452: List Of Pins

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 23.1.3 List of Pins Pin name Primary function Secondary function Tertiary function C data P80/SDA/SIN0 I/O port SSIO0 data input I/O (SDA) C clock P81/SCL/SCK0 I/O port SSIO0 clock I/O I/O (SCL) P82/SOUT0 I/O port SSIO0 data output P83/PWM5...

  • Page 453: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 23.2 Description of Registers 23.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F2DEH Port 8 data register 0F2DFH Port 8 direction register P8DIR 0F2E0H Port 8 control register 0 P8CON0 8/16 P8CON...

  • Page 454: Port 8 Data Register (P8D)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 23.2.2 Port 8 Data Register (P8D) Address: 0F2DEH Access: R/W Access size: 8 bits Initial value: 00H P87D P86D P85D P84D P83D P82D P81D P80D Initial value P8D is a special function register (SFR) to set the value to be output to the Port 8 pin or to read the input level of the Port 8. In output mode, the value of this register is output to the Port 8 pin.

  • Page 455: Port 8 Direction Register (P8Dir)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 23.2.3 Port 8 Direction Register (P8DIR) Address: 0F2DFH Access: R/W Access size: 8 bits Initial value: 00H P8DIR P87DIR P86DIR P85DIR P84DIR P83DIR P82DIR P81DIR P80DIR Initial value P8DIR is a special function register (SFR) to select the input/output mode of Port 8. Description of bits •...

  • Page 456: Port 8 Control Registers 0, 1 (P8Con0, P8Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 23.2.4 Port 8 Control Registers 0, 1 (P8CON0, P8CON1) Address: 0F2E0H Access: R/W Access size: 8/16 bit Initial value: 00H P8CON0 P87C0 P86C0 P85C0 P84C0 P83C0 P82C0 P81C0 P80C0 Initial value Address: 0F2E1H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 457 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 Setting of P84 pin When output mode is selected (P84DIR When input mode is selected (P84DIR bit bit = "0") = "1") P84C1 P84C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor...

  • Page 458: Port 8 Mode Registers 0, 1 (P8Mod0, P8Mod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 23.2.5 Port 8 Mode Registers 0, 1 (P8MOD0, P8MOD1) Address: 0F2E2H Access: R/W Access size: 8/16 bit Initial value: 00H P8MOD0 P87MD0 P86MD0 P85MD0 P84MD0 P83MD0 P82MD0 P81MD0 P80MD0 Initial value Address: 0F2E3H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 459 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 • P84MD1, P84MD0 (bit 4) The P84MD1 and P84MD0 bits are used to select the primary, secondary, or tertiary function of the P84 pin. Description P84MD1 P84MD0 General-purpose output port function (initial value) UART1 data input pin (RXD1) SSIO0 data input pin (SIN0) Do not use...

  • Page 460: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 23 Port 8 23.3 Description of Operation 23.3.1 Input/Output Port Functions For each pin of Port 8, either output or input is selected by setting the Port 8 direction register (P8DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 8 control registers 0, 1 (P8CON0, P8CON1).
  • Page 461 Chapter 24 Successive Approximation Type A/D Converter...

  • Page 462: Successive Approximation Type A/D Converter (Sa-Adc)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24 Successive Approximation Type A/D Converter (SA-ADC) 24.1 General Description This LSI has an internal 12-channel successive approximation type A/D converter (SA-ADC). The successive approximation type A/D converter works only when the DSAD bit of the block control register 4 (BLKCON4) is set to "0".
  • Page 463 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.1.3 List of Pins Pin name Function Positive power supply pin for the successive approximation type A/D converter Reference power supply pin for the successive approximation type A/D converter Negative power supply pin for the successive approximation type A/D converter P30/EXI6/AIN0/P I/O port, External interrupt, PW45EV1 input, Successive approximation type A/D W45EV1...
  • Page 464 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2 Description of Registers 24.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F8D0H SA-ADC result register 0L SADR0L 8/16 SADR0 0F8D1H SA-ADC result register 0H SADR0H 0F8D2H SA-ADC result register 1L...

  • Page 465: Sa-Adc Result Register 0L (Sadr0L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.2 SA-ADC Result Register 0L (SADR0L) Address: 0F8D0H Access: R Access size: 8/16 bit Initial value: 00H SADR0L SAR01 SAR00 Initial value SADR0L is a special function register (SFR) used to store SA-ADC conversion results on channel 0. SADR0L is updated after A/D conversion.

  • Page 466: Sa-Adc Result Register 1L (Sadr1L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.4 SA-ADC Result Register 1L (SADR1L) Address: 0F8D2H Access: R Access size: 8/16 bit Initial value: 00H SADR1L SAR11 SAR10 Initial value SADR1L is a special function register (SFR) used to store SA-ADC conversion results on channel 1. SADR1L is updated after A/D conversion.

  • Page 467: Sa-Adc Result Register 2L (Sadr2L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.6 SA-ADC Result Register 2L (SADR2L) Address: 0F8D4H Access: R Access size: 8/16 bit Initial value: 00H SADR2L SAR21 SAR20 Initial value SADR2L is a special function register (SFR) used to store SA-ADC conversion results on channel 2. SADR2L is updated after A/D conversion.

  • Page 468: Sa-Adc Result Register 3L (Sadr3L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.8 SA-ADC Result Register 3L (SADR3L) Address: 0F8D6H Access: R Access size: 8/16 bit Initial value: 00H SADR3L SAR31 SAR30 Initial value SADR3L is a special function register (SFR) used to store SA-ADC conversion results on channel 3. SADR3L is updated after A/D conversion.

  • Page 469: Sa-Adc Result Register 4L (Sadr4L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.10 SA-ADC Result Register 4L (SADR4L) Address: 0F8D8H Access: R Access size: 8/16 bit Initial value: 00H SADR4L SAR41 SAR40 Initial value SADR4L is a special function register (SFR) used to store SA-ADC conversion results on channel 4. SADR4L is updated after A/D conversion.

  • Page 470: Sa-Adc Result Register 5L (Sadr5L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.12 SA-ADC Result Register 5L (SADR5L) Address: 0F8DAH Access: R Access size: 8/16 bit Initial value: 00H SADR5L SAR51 SAR50 Initial value SADR5L is a special function register (SFR) used to store SA-ADC conversion results on channel 5. SADR5L is updated after A/D conversion.

  • Page 471: Sa-Adc Result Register 6L (Sadr6L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.14 SA-ADC Result Register 6L (SADR6L) Address: 0F8DCH Access: R Access size: 8/16 bit Initial value: 00H SADR6L SAR61 SAR60 Initial value SADR6L is a special function register (SFR) used to store SA-ADC conversion results on channel 6. SADR6L is updated after A/D conversion.

  • Page 472: Sa-Adc Result Register 7L (Sadr7L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.16 SA-ADC Result Register 7L (SADR7L) Address: 0F8DEH Access: R Access size: 8/16 bit Initial value: 00H SADR7L SAR71 SAR70 Initial value SADR7L is a special function register (SFR) used to store SA-ADC conversion results on channel 7. SADR7L is updated after A/D conversion.

  • Page 473: Sa-Adc Result Register 8L (Sadr8L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.18 SA-ADC Result Register 8L (SADR8L) Address: 0F8E0H Access: R Access size: 8/16 bit Initial value: 00H SADR8L SAR81 SAR80 Initial value SADR8L is a special function register (SFR) used to store SA-ADC conversion results on channel 8. SADR8L is updated after A/D conversion.

  • Page 474: Sa-Adc Result Register 9L (Sadr9L)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.20 SA-ADC Result Register 9L (SADR9L) Address: 0F8E2H Access: R Access size: 8/16 bit Initial value: 00H SADR9L SAR91 SAR90 Initial value SADR9L is a special function register (SFR) used to store SA-ADC conversion results on channel 9. SADR9L is updated after A/D conversion.

  • Page 475: Sa-Adc Result Register Al (Sadral)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.22 SA-ADC Result Register AL (SADRAL) Address: 0F8E4H Access: R Access size: 8/16 bit Initial value: 00H SADRAL SARA1 SARA0 Initial value SADRAL is a special function register (SFR) used to store SA-ADC conversion results on channel A. SADRAL is updated after A/D conversion.

  • Page 476: Sa-Adc Result Register Bl (Sadrbl)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.24 SA-ADC Result Register BL (SADRBL) Address: 0F8E6H Access: R Access size: 8/16 bit Initial value: 00H SADRBL SARB1 SARB0 Initial value SADRBL is a special function register (SFR) used to store SA-ADC conversion results on channel B. SADRBL is updated after A/D conversion.

  • Page 477: Sa-Adc Control Register 0 (Sadcon0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.26 SA-ADC Control Register 0 (SADCON0) Address: 0F8F0H Access: R/W Access size: 8/16 bit Initial value: 00H SADCON0 SACK SALP Initial value SADCON0 is a special function register (SFR) used to control the operation of the SA-ADC. Description of bits •...

  • Page 478: Sa-Adc Control Register 1 (Sadcon1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.27 SA-ADC Control Register 1 (SADCON1) Address: 0F8F1H Access: R/W Access size: 8 bits Initial value: 00H SADCON1 SARUN Initial value SADCON1 is a special function register (SFR) used to control the operation of the SA-ADC. Description of bits •...

  • Page 479: Sa-Adc Mode Register 0 (Sadmod0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.28 SA-ADC Mode Register 0 (SADMOD0) Address: 0F8F2H Access: R/W Access size: 8 bits Initial value: 00H SADMOD0 SACH7 SACH6 SACH5 SACH4 SACH3 SACH2 SACH1 SACH0 Initial value SADMOD0 is a special function register (SFR) used to choose A/D conversion channel(s). Description of bits •...
  • Page 480 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter • SACH0 (bit 0) SACH0 Description Stops conversion on channel 0 (initial value) Performs conversion on channel 0. The SACH7 to SACH0 bits are used to select channel(s) on which A/D conversion is performed. If both channel 1 and channel 0 are set to "1", A/D conversion is performed on channel 0 first, and then channel [Note] Do not start A/D conversion in the state in which all of the SACHB to SACH0 bits of SA-ADC mode register 0, 1...

  • Page 481: Sa-Adc Mode Register 1 (Sadmod1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.29 SA-ADC Mode Register 1 (SADMOD1) Address: 0F8F3H Access: R/W Access size: 8 bits Initial value: 00H SADMOD1 SACHB SACHA SACH9 SACH8 Initial value SADMOD0 is a special function register (SFR) used to choose A/D conversion channel(s). Description of bits •...

  • Page 482: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.3 Description of Operation 24.3.1 Setting of A/D Conversion Channels According to the setting of SA-ADC mode register (SADMOD), A/D conversion is performed as shown below and A/D conversion results are stored in the SA-ADC result register. SA-ADC SA-ADC Remarks...
  • Page 483 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.3.2 Operation of the Successive Approximation Type A/D Converter For direct input, operate SA-ADC in the following procedure. 1． Before starting SA-ADC, start oscillation of the high-speed clock (OSCLK) and wait until the oscillator settles. 2．...
  • Page 484 Chapter 25 Analogue Comparator...

  • Page 485: Analogue Comparator

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 25 Analogue Comparator 25 Analogue Comparator 25.1 General Description This LSI includes 1 channels of analogue comparator. Voltage comparison between two pins (CMP0P, CMP0M) that are input to the comparator is available. 25.1.1 Features • The comparator output can generate an interrupt. •...

  • Page 486: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 25 Analogue Comparator 25.2 Description of Registers 25.2.1 List of Registers Address Name Symbol (Byte) Symbol Size Initial (Word) value 0F950H Comparator 0 control register 0 CMP0CON0 8/16 CMP0CON 0F951H Comparator 0 control register 1 CMP0CON1 FEUL620Q150A 25-2...

  • Page 487: Comparator 0 Control Register 0 (Cmp0Con0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 25 Analogue Comparator 25.2.2 Comparator 0 Control Register 0 (CMP0CON0) Address: 0F950H Access: R/W Access size: 8/16 bit Initial value: 00H — — — — — — CMP0D CMP0EN CMP0CON0 Initial value CMP0CON0 is a special function register (SFR) to control the comparator. Description of bits •...

  • Page 488: Comparator 0 Control Register 1 (Cmp0Con1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 25 Analogue Comparator 25.2.3 Comparator 0 Control Register 1 (CMP0CON1) Address: 0F951H Access: R/W Access size: 8 bits Initial value: 00H CMP0CON — — — — — CMP0SM0 CMP0E1 CMP0E0 Initial value CMP0CON1 is a special function register (SFR) to control the comparator interrupt. Description of bits •...

  • Page 489: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 25 Analogue Comparator 25.3 Description of Operation 25.3.1 Comparator Functions The comparator compares the input voltages of the CMP0P and CMP0M pins to output the result to the CMP0D bit of the comparator n control register 0 (CMP0CON0). To use the comparator, set the port as high-impedance output in advance.

  • Page 490: Interrupt Request

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 25 Analogue Comparator 25.3.2 Interrupt Request When an interrupt edge selected by the comparator control register 1 (CMP0CON1) occurs on the comparison result of the comparator, a comparator interrupt (CMP0INT) is generated. For the comparator interrupt, the edge can be selected. Figure 25-3 shows the interrupt generation timing in rising-edge interrupt mode, in falling-edge interrupt mode, and in both-edge interrupt mode without sampling, and in rising-edge interrupt mode with sampling.

  • Page 491: Lld (Low Level Detector)

    Chapter 26 LLD (Low Level Detector)

  • Page 492: Chapter 26 Lld Circuit

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 26 LLD Circuit 26 LLD (Low Level Detector) 26.1 General Description This LSI includes a Low Level Detector (LLD). Four levels of threshold voltage can be selected by setting Code-Option. The operation (reset or interrupt) to be performed when the voltage drops below the threshold can be selected by setting Code-Option.

  • Page 493: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 26 LLD Circuit 26.2 Description of Registers 26.2.1 List of Registers Address Name Symbol (Byte) Symbol Size Initial (Word) value 0F8C1H LLD circuit control register 1 LLDCON1 FEUL620Q150A 26-2...

  • Page 494: Lld Circuit Control Register 1 (Lldcon1)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 26 LLD Circuit 26.2.2 LLD Circuit Control Register 1 (LLDCON1) Address: 0F8C1H Access: R/W Access size: 8 bits Initial value: 00H LLDCON1 — — — — — — LLDF ENBL Initial value LLDCON1 is a special function register (SFR) used to control the LLD circuit. Description of bits •...

  • Page 495: Threshold Voltage

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 26 LLD Circuit 26.3 Description of Operation 26.3.1 Threshold Voltage The value of the threshold voltage (V ) can be selected by Code-Option. Table 26-1 shows the threshold voltages and hysteresis width, and Table 26-2 shows the LLD operation selection. Table 26-1 Threshold Voltages and Accuracy Code option (FLASH address: *)

  • Page 496: Operation Of Lld Circuit

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 26 LLD Circuit 26.3.2 Operation of LLD Circuit Activation (ON) and deactivation (OFF) of LLD circuit are controlled by setting the ENBL bit of the LLD circuit control register 1 (LLDCON1), and the result of comparison of the power supply voltage (V ) to the threshold voltage is output to the LLDF bit of LLDCON1.

  • Page 497: Power Supply Circuit

    Chapter 27 Power Supply Circuit...

  • Page 498: Features

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 27 Power Supply Circuit 27 Power Supply Circuit 27.1 General Description This LSI includes a voltage regulator circuit for internal logic (VRL). The VRL outputs the operating voltage, V , of the internal logic circuit, program memory, RAM, etc. 27.1.1 Features •...

  • Page 499: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 27 Power Supply Circuit 27.2 Description of Operation After power-on, the V voltage becomes approximately 1.5 V in any operation mode. Figure 27-2 shows the operation waveforms of the power supply circuit. RESET_N pin Oscillation stabilization time Oscillation stabilization time System reset RESET_N...

  • Page 500: On-Chip Debug Function

    Chapter 28 On-chip Debug Function ...

  • Page 501: How To Connect The On-Chip Debug Emulator

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 10 Watchdog Timer 28 On-chip Debug Function 28.1 General Description This LSI has an on-chip debug function allowing Flash memory rewriting. The on-chip debug emulator (µEASE) is connected to this LSI to perform the on-chip debug function. 28.2 How to connect the On-Chip Debug Emulator Figure 28-1 shows connection to the on-chip debug emulator (µEASE).
  • Page 502 Chapter 29 Flash Memory Rewrite Function...

  • Page 503: Flash Memory Rewrite Function

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29 FLASH Memory Rewrite Function 29.1 General Description This LSI includes the ISP (In System Programming) function and boot area remap function that rewrite the content of the flash memory (program memory space) using a special function register (SFR) programmatically.  ...

  • Page 504: Description Of Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.2 Description of Registers 29.2.1 List of Registers Address Name Symbol Symbol Size Initial (Byte) (Word) value 0F0E0H Flash address register L FLASHAL 8/16 FLASHA 0F0E1H Flash address register H FLASHAH 0F0E2H Flash data register L FLASHDL...
  • Page 505 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.2 Flash Address Register (FLASHAL, FLASHAH) Address: 0F0E0H Access: R/W Access size: 8 bits/16 bits Initial value: 00H FLASHAL Initial value Address: 0F0E1H Access: R/W Access size: 8 bits Initial value: 00H FLASHAH FA15 FA14...
  • Page 506 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function Table 29-1 Address Setting Values for Block Erase (ML620Q151A/ML620Q154A/ML620Q157A) Area for block erase FLASHSEG FLASHAH Segment Address 0:0000H 0:1FFFH 0:2000H 0:3FFFH Segment 0 0:4000H 0:5FFFH 0:6000H 0:7FFFH Segment 7 7:0000H 7:07FFH The unit of block is 8 KB for the segment 0 and 2 KB for the segment 7.
  • Page 507 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function Table 29-3 Address Setting Values for Block Erase (ML620Q152A/ML620Q155A/ML620Q158A) Area for block erase FLASHSEG FLASHAH Segment Address 0:0000H 0:1FFFH 0:2000H 0:3FFFH 0:4000H 0:5FFFH Segment 0 0:6000H 0:7FFFH 0:8000H 0:9FFFH 0:0A000H 0:0BFFFH Segment 7 7:0000H 7:07FFH...
  • Page 508 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function Table 29-5 Address Setting Values for Block Erase (ML620Q153A/ML620Q156A/ML620Q159A) Area for block erase FLASHSEG FLASHAH Segment Address 0:0000H 0:1FFFH 0:2000H 0:3FFFH 0:4000H 0:5FFFH 0:6000H 0:7FFFH Segment 0 0:8000H 0:9FFFH 0:A000H 0:BFFFH 0:C000H 0:DFFFH 0:E000H...
  • Page 509 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.3 Flash Data Register (FLASHDL, FLASHDH) Address: 0F0E2H Access: R/W Access size: 8 bits/16 bits Initial value: 00H FLASHDL Initial value Address: 0F0E3H Access: R/W Access size: 8 bits Initial value: 00H FLASHDH FD15 FD14...

  • Page 510: Flash Control Register (Flashcon)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.4 Flash Control Register (FLASHCON) Address: 0F0E4H Access: W Access size: 8 bits Initial value: 00H FLASHCON — — — — — — FSERA FERS Initial value FLASHCON is a write-only special function register (SFR) to control the block erase and sector erase for the flash memory rewrite.

  • Page 511: Flash Acceptor (Flashacp)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.5 Flash Acceptor (FLASHACP) Address: 0F0E6H Access: W Access size: 8 bits Initial value: 00H FLASHACP fac7 fac6 fac5 fac4 fac3 fac2 fac1 fac0 Initial value FLASHACP is a write-only special function register (SFR) to control the block erase for the flash memory rewrite or enable/disable the 1-word write operation.

  • Page 512: Flash Self Register (Flashslf)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.7 Flash Self Register (FLASHSLF) Address: 0F0EAH Access: R/W Access size: 8 bits Initial value: 00H FLASHSLF — — — — — — — FSELF Initial value FLASHSLF is a special function register (SFR) used to control the flash memory self-rewrite function. Description of bits •...

  • Page 513: Flash Remap Register (Remapadd)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.8 Flash Remap Register (REMAPADD) Address: 0F0ECH Access: R/W Access size: 8 bits Initial value: 00H REMAPADD RBTA RES2 RES1 RES0 REA15 REA14 REA13 REA12 Initial value REMAPADD is a special function register (SFR) used to specify the remap area. In REMAPADD, the following two types of remapping can be specified.

  • Page 514: Description Of Operation

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.3 Description of Operation When using the self-rewrite function, prepare the program for self-rewrite in advance on a program code area with addresses that are not used for block/sector erase or 1-word write. The self-rewrite function includes the block erase function that erases by 8 K words (16 Kbytes), the sector erase function that erases by 512 words (1 Kbyte), and the 1-word write function that writes by 1 word (2 bytes).
  • Page 515 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 8.192 MHz, 4.096 MHz, 2.048 MHz, and 1.024 MHz is used as the system clock.) For details of clock modes and settings, see Chapter 6, "Clock Generation Circuit". Note on debugging flash self-write code using the U16 development environment are described below. Table 29-8 Cautions When Debugging Flash Self-Write Code State of use Cautions...

  • Page 516: Block Erase Function

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.1 Block Erase Function This function erases the flash memory data by block (8 Kbytes). Writing "01H" to the flash self register starts voltage multiplying in the LSI, and rewrite operation becomes enabled. Write "0FAH"...

  • Page 517: Sector Erase Function

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.2 Sector Erase Function This function erases the flash memory data by sector (1 Kbytes). Writing "01H" to the flash self register starts voltage multiplying in the LSI, and rewrite operation becomes enabled. After checking the completion of voltage multiplying with the flash status register, write "0FAH"...

  • Page 518: 1-Word Write Function

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.3 1-word Write Function This function writes data to the flash memory by 1 word (2 bytes). Writing "01H" to the flash self register starts voltage multiplying in the LSI, and rewrite operation becomes enabled. After checking the completion of voltage multiplication with the flash status register, write "0FAH"...

  • Page 519: Boot Area Remap Function By Software

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.4 Boot Area Remap Function by Software This function can remap the area from 0000H to 0FFFH (4 KB) to the area of the same size (4 KB or less) starting from the address set in the REMAPADD register.

  • Page 520: Notes In Use

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.5 Notes in Use When the power is down or the operation is terminated forcibly during block/sector erase or 1-word write, retry the block erase and rewrite the block area of 8K words. If the self-rewrite program does not work, write the program by using the on-chip debug emulator (µEASE).

  • Page 521: Code-Option

    Chapter 30 Code-Option...
  • Page 522 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 30 Code-Option 30 Code-Option 3.1 General Description This LSI has the code-option function. The code-option function can select the low-speed oscillation clock (External crystal oscillation or Internal RC oscillation), LLD circuit operation (Interrupt of Reset) and the LLD threshold voltage level. 3.1.1 Features •...

  • Page 523: Code-Option Register 0 (Codeop0)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 30 Code-Option 30.2.2 Code-Option Register 0 (CODEOP0) Address: 0F3D8H Access: R Access size: 8 bits Initial value: 00H ―* ―* ―* ―* CODEOP0 COLOSC LLDSEL LLD1 LLD0 Initial value CODEOP0 is a special function register (SFR) that can read Code-Option data. CODEOP0 is read only register and is not waritable by the software.

  • Page 524: The Setting Method Of The Code-Option Data

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Chapter 30 Code-Option 30.3 The Setting Method of the Code-Option Data 30.3.1 Code-Option Data Format ML620Q151A/ML620Q154A/ML620Q157A : The code-option data is set on address 0：7DE0H which is in writable test data area of program memory. ML620Q152A/ML620Q155A/ML620Q158A : The code-option data is set on address 0：BDE0H which is in writable test data area of program memory.
  • Page 525 Appendix A...

  • Page 526: Appendix A Registers

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix A Registers Contents of Registers Address Symbol Symbol 8/16 Initial name Byte Word value － 0F000H Data segment register － － － － － 0F001H Reserve 0F002H Frequency control register 0 FCON0 8/16 FCON 0F003H Frequency control register 1 FCON1 0F005H Frequency control register 3...
  • Page 527 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value 0F02EH Interrupt level control register 50 ILC50 8/16 ILC5W 0F02FH Interrupt level control register 51 ILC51 0F030H Interrupt level control register 60 ILC60 8/16 ILC6W 0F031H Interrupt level control register 61 ILC61...
  • Page 528 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value － 0F21BH Port 1 direction register P1DIR 0F21CH Port 1 control register 0 P1CON0 8/16 P1CON 0F21DH Port1 control register 1 P1CON1 － 0F228H Port 2 data register －...
  • Page 529 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value 0F310H Timer 0 counter register TM0C 8/16 TM01C Timer 1 counter register 0F311H TM1C 0F320H Timer 0 control register TM0CON 8/16 TM01CO 0F321H Timer 1 control register TM1CON －...
  • Page 530 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix A Registers 0F4A7H PWM4 control register 1 PW4CON1 Address Symbol Symbol 8/16 Initial name Byte Word value 0F4A8H PWM4 control register 2 PW4CON2 8/16 PW4CON 0F4A9H PWM4 control register 3 PW4CON3 0F4AAH PWM4 control register 4 PW4CON4 8/16 PW4CON...
  • Page 531 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value 0F700H Serial port 0 transmit/receive buffer L SIO0BUFL SIO0BUF 8/16 0F701H Serial port 0 transmit/receive buffer H SIO0BUFH － 0F702H Serial port 0 control register SIO0CON 0F704H Serial port 0 mode register 0...
  • Page 532 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value 0F8DCH SA-ADC result register 6L SADR6L SADR6 8/16 SA-ADC result register 6H 0F8DDH SADR6H 0F8DEH SA-ADC result register 7L SADR7L SADR7 8/16 0F8DFH SA-ADC result register 7H SADR7H 0F8E0H SA-ADC result register 8L...
  • Page 533 Appendix B...

  • Page 534: Appendix B Package Dimentions

    The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

  • Page 535: Ml620Q154A/Ml620Q155A/Ml620Q156A Package Dimension (52Pin Tqfp

    The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

  • Page 536: Ml620Q157A/Ml620Q158A/Ml620Q159A Package Dimension (64Pin Tqfp

    The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
  • Page 537 Appendix C...

  • Page 538: Absolute Maximum Ratings

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics Absolute Maximum Ratings = 0V) Parameter Symbol Condition Rating Unit −0.3 to +6.5 Power supply voltage 1 Ta = 25°C −0.3 to +2.0 Power supply voltage 2 Ta = 25°C −0.3 to V Reference voltage Ta = 25°C...

  • Page 539: Appendix C Electrical Characteristics

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics Flash Memory Operating Conditions = 0V) Parameter Symbol Condition Range Unit Data flash memory, At write/erase -40 to +105 °C Operating temperature Flash ROM, At write/erase 0 to +40 Operating voltage At write/erase 1.8 to 5.5 Data Flash 10,000...
  • Page 540 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics DC Characteristics (LLD) =2.2 to 5.5V, V =0V, Ta=−40 to +105°C, unless otherwise specified) Meas Parameter Symbol Condition Min. Typ. Max. Unit uring circuit LD1 to 0 = 0H LD1 to 0 = 1H 2.45 2.55 2.65...
  • Page 541 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics DC Characteristics (VOHL, IOHL) =1.8 to 5.5V, V =0V, Ta=−40 to +105°C, unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit circuit Output voltage 1 (P20 to P23) IOH1 = −0.5mA ―...
  • Page 542 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics DC Characteristics (VIHL) =1.8 to 5.5V, V =0V, Ta=−40 to +105°C, unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit circuit Input voltage 1 (RESET_N) (P14/TEST0) 0.7× ― ― VIH1 (TEST1_N) (P00 to P05)* (P12, P13) (P30 to P37)*...

  • Page 543: Measuring Circuit

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics Measuring circuit 1 32.768kHz crystal ：2.2µF ：2.2µF ：12pF ：12pF 32.768kHz Crystal oscillator (DT-26 DAISHINKU Corp.) Measuring circuit 2 (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. FEUL620Q150A...
  • Page 544 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics Measuring circuit 3 (*1) (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. Measuring circuit 4 (*3) *3: Measured at the specified input pins. Measuring circuit 5 (*1) *1: Input logic circuit to determine the specified measuring conditions.

  • Page 545: Ac Characteristics (External Interrupt)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics AC Characteristics (External Interrupt) =1.8 to 5.5V, V =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit External interrupt disable Interrupt: Enabled (MIE = 1), 2.5× 3.5× µs ―...

  • Page 546: Ac Characteristics (Synchronous Serial Port)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics AC Characteristics (Synchronous Serial Port) =1.8 to 5.5V, V =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit µs ― ― High-speed oscillation stopped SCK input cycle SCYC ―...

  • Page 547: Ac Characteristics (I2C Bus Interface: Fast Mode 400Khz)

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics AC Characteristics (I C Bus Interface: Standard Mode 100kHz) =1.8 to 5.5V, V =0V, Ta=−40 to +105°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. ⎯ ⎯ SCL clock frequency SCL hold time ⎯...

  • Page 548: Electrical Characteristics Of Successive Approximation Type A/D Converter

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix C Electrical Characteristics Electrical Characteristics of Successive Approximation Type A/D Converter =1.8 to 5.5V, V =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit ― ― ― Resolution bits 2.7V ≤ V ≤...
  • Page 549 Appendix D...

  • Page 550: Appendix D Application Circuit Example

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix D Application Circuit Example Appendix D Application Circuit Example 5.0V uEASE UVDD_O RESET_N TEST1_N TEST TEST0 ML620Q151A ML620Q152A ML620Q153A ML620Q154A ML620Q155A RESET_N Reset IC ML620Q156A ML620Q157A ML620Q158A ML620Q159A 32.768KHz Xtal /LED1 /LED0 /SCL /SDA (Output) : 2.2uF : 2.2uF : 12pF to 25pF WP SCL SDA...
  • Page 551 Appendix E...

  • Page 552: Appendix E Check List

    ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix E Check List Appendix E Check List This Check List has notes to prevent commonly-made programming mistakes and frequently overlooked or misunderstood hardware features of the MCU. Check each note listed up chapter by chapter while coding the program or evaluating it using the MCU. Chapter 1 Overview •About unused pins [ ] Please confirm how to handle the unused pins(Refer to Section 1.3.4 in the user’s manual).
  • Page 553 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix E Check List (*) ML620Q150A series have a different pin configuration for each package. See the section 1.3.2 “LIST OF PINS” for more details. Chapter 7 Time Base Counter •How to read LTBC [ ] Read consecutively LTBC(Low-speed Time Base Counter) twice until the last data coincides the previous data to prevent reading of uncertain data while counting up the clock (Refer to Section 7.3.1 in the user's manual).
  • Page 554 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Appendix E Check List (*) ML620Q150A series have a different pin configuration for each package. See the section 1.3.2 “LIST OF PINS” for more details. •Port function setting [ ] Specify the secondary function for the port (Refer to Section 14.4 in the user’s manual). Chapters 15 to 23 Port •Pin Handling [ ] Don’t leave Hi-impedance Input ports in floating state.

  • Page 555: Revision History

    Revision History...
  • Page 556 ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A User's Manual Revision of History Revision History Page Document No. Date Description Previous Current Edition Edition FEU620Q150A-01 May 7, 2015 – – Fromal 1 Revision 16-1, 16-1, 16-4, 16-4, FEU620Q150A-02 May 25, 2015 Add a notice about P14DIR bit. 16-6, 16-6, 28-1...

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