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LAPIS Semiconductor ML620Q158B
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Rohm LAPIS Semiconductor ML620Q158B manual available for free PDF download: User Manual
Rohm LAPIS Semiconductor ML620Q158B User Manual (558 pages)
Brand:
Rohm
| Category:
Microcontrollers
| Size: 10 MB
Table of Contents
Table of Contents
5
Chapter 1 Overview
16
Features
17
Configuration of Functional Blocks
20
Block Diagram
20
Pins
23
Pin Layout
23
Pin Layout of Package
23
List of Pins
26
Pin Description
30
Handling of Unused Pins
33
Chapter 2 CPU and Memory Space
34
Genral Description
35
Program Memory Space
35
Data Memory Space
38
Instruction Length
41
Data Type
41
Description of Registers
41
List of Registers
41
Data Segment Register (DSR)
41
Chapter 3 Reset Function
42
General Description
43
Features
43
Configuration
43
List of Pin
43
Description of Registers
44
List of Registers
44
Reset Status Register (RSTAT)
44
Description of Operation
46
Operation of System Reset Mode
46
Chapter 4 MCU Control Function
47
General Description
48
Features
48
Configuration
48
Description of Registers
49
List of Registers
49
Stop Code Acceptor (STPACP)
50
Standby Control Register (SBYCON)
51
Block Control Register 0 (BLKCON0)
52
Block Control Register 2 (BLKCON2)
53
Block Control Register 3 (BLKCON3)
54
Block Control Register 4 (BLKCON4)
55
Block Control Register 6 (BLKCON6)
56
Block Control Register 7 (BLKCON7)
57
Description of Operation
58
Program Operating Mode
58
HALT Mode
58
STOP Mode
59
Stop Mode When the CPU Runs with Low-Speed Clock
59
Stop Mode When the CPU Runs with High-Speed Clock
63
Note on Return Operation from STOP/HALT Mode
67
Block Control Function
68
Chapter 5 Interrupts (Ints)
69
Features
70
Description of Registers
71
List of Registers
71
Interrupt Enable Register 0 (IE0)
72
Interrupt Enable Register 1 (IE1)
73
Interrupt Enable Register 2 (IE2)
75
Interrupt Enable Register 3 (IE3)
76
Interrupt Enable Register 4 (IE4)
77
Interrupt Enable Register 5 (IE5)
78
Interrupt Enable Register 6 (IE6)
79
Interrupt Enable Register 7 (IE7)
81
Interrupt Request Register 0 (IRQ0)
82
Interrupt Request Register 1 (IRQ1)
83
Interrupt Request Register 2 (IRQ2)
85
Interrupt Request Register 3 (IRQ3)
86
Interrupt Request Register 4 (IRQ4)
88
Interrupt Request Register 5 (IRQ5)
89
Interrupt Request Register 6 (IRQ6)
90
Interrupt Request Register 7 (IRQ7)
92
Interrupt Level Control Enable Register (ILENL)
93
Current Interrupt Request Level Register (CILL)
94
Interrupt Level Control Register 01 (ILC01)
95
Interrupt Level Control Register 10 (ILC10)
96
Interrupt Level Control Register 11 (ILC11)
97
Interrupt Level Control Register 20 (ILC20)
98
Interrupt Level Control Register 21 (ILC21)
99
Interrupt Level Control Register 30 (ILC30)
100
Interrupt Level Control Register 31 (ILC31)
101
Interrupt Level Control Register 40 (ILC40)
102
Interrupt Level Control Register 51 (ILC51)
103
Interrupt Level Control Register 60 (ILC60)
104
Interrupt Level Control Register 61 (ILC61)
105
Interrupt Level Control Register 70 (ILC70)
106
Description of Operation
107
Maskable Interrupt Processing
109
Non-Maskable Interrupt Processing
109
Software Interrupt Processing
109
Notes on Interrupt Routine (When Interrupt Level Control Disabled)
110
Flow Chart When Interrupt Level Control Enabled
113
How to Write Interrupt Processing When Interrupt Level Control Enabled
114
Writing Interrupt Function to Disable Multiple Interrupts
114
Writing Interrupt Function to Enable Multiple Interrupts
116
Interrupt Disable State
117
Chapter 6 Clock Generation Circuit
118
Features
119
Configuration
120
List of Pins
121
Clock Configuration Diagram
121
Description of Registers
122
List of Registers
122
Frequency Control Register 0(FCON0)
123
Frequency Control Register 1 (FCON1)
124
Frequency Control Register 3(FCON3)
125
Frequency Status Register (FSTAT)
127
Description of Operation
128
Low-Speed Clock
128
Low-Speed Crystal Oscillation Circuit
128
Low-Speed Built-In RC Oscillation Circuit
128
Operation of Low-Speed Clock Generation Circuit
129
High-Speed Clock
132
High-Speed Built-In RC Oscillation Circuit
132
PLL Oscillation Circuit
132
Operation of High-Speed Clock
133
Switching of System Clock
135
Specifying Port Registers
136
Functioning P21(OUTCLK) as the High-Speed Clock Output
136
Functioning P20 (LSCLK) as the Low-Speed Clock Output
137
Functioning P36 (LSCLK) as the Low-Speed Clock Output
138
Chapter 7 Time Base Counter
139
Features
140
Configuration
140
Description of Registers
141
List of Registers
141
Low-Speed Time Base Counter (LTBR)
142
Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJL, LTBADJH)
143
Low-Speed Time Base Counter Interrupt Select Registers (LTBINT0, LTBINT1)
145
Description of Operation
146
Low-Speed Time Base Counter
146
Chapter 8 8Bit Timer
148
Features
149
Configuration
149
Description of Registers
150
List of Registers
150
Timer 0 Data Register (TM0D)
151
Timer 1 Data Register (TM1D)
152
Timer 0 Counter Register (TM0C)
153
Timer 1 Counter Register (TM1C)
154
Timer 0 Control Register (TM0CON)
155
Timer 1 Control Register (TM1CON)
157
Timer Start Register 0 (TMSTR0)
158
Timer Stop Register 0 (TMSTP0)
159
Timer Status Register 0 (TMSTAT0)
160
Description of Operation
161
Chapter 9 16Bit Timer
163
Features
164
Configuration
164
Description of Registers
165
List of Registers
165
16Bit Timer 8 Data Register L,H (TMH8DL,H)
166
16Bit Timer 9 Data Register L,H (TMH9DL,H)
167
16Bit Timer a Data Register L,H (TMHADL,H)
168
16Bit Timer B Data Register L,H (TMHBDL,H)
169
16Bit Timer 8 Counter Register L,H (TMH8CL,H)
170
16Bit Timer 9 Counter Register L,H (TMH9CL,H)
171
16Bit Timer a Counter Register L,H (TMHACL,H)
172
16Bit Timer B Counter Register L,H (TMHBCL,H)
173
16Bit Timer 8 Control Register L,H (TMH8CON)
174
16Bit Timer a Control Register L,H (TMHACON)
176
16Bit Timer B Control Register L,H (TMHBCON)
177
16Bit Timer Start Register 0 (TMHSTR0)
178
16Bit Timer Stop Register 0 (TMHSTP0)
179
16Bit Timer Status Register 0 (TMHSTAT0)
180
Description of Operation
181
Chapter 10 Watchdog Timer
183
General Description
184
Features
184
Configuration
184
Description of Registers
185
List of Registers
185
Watchdog Timer Control Register (WDTCON)
186
Watchdog Timer Mode Register (WDTMOD)
187
Description of Operation
188
Chapter 11 PWM
191
General Description
192
Features
192
Configuration
193
List of Pins
197
Description of Registers
198
List of Registers
198
PWM4 Period Register L, H (PW4PL, PW4PH)
200
PWM4 Duty Register L, H (PW4DL, PW4DH)
201
PWM4 Counter Register L, H (PW4CL, PW4CH)
202
PWM4 Control Register 0 (PW4CON0)
203
PWM4 Control Register 1 (PW4CON1)
205
PWM4 Control Register 2 (PW4CON2)
206
PWM4 Control Register 3 (PW4CON3)
208
PWM4 Control Register 4 (PW4CON4)
209
PWM4 Control Register 5 (PW4CON5)
210
PWM4 Control Register 6 (PW4CON6)
211
PWM5 Period Register L, H (PW5PL, PW5PH)
212
PWM5 Duty Register L, H (PW5DL, PW5DH)
213
PWM5 Counter Register L, H (PW5CL, PW5CH)
214
PWM5 Control Register 0 (PW5CON0)
215
PWM5 Control Register 1 (PW5CON1)
217
PWM5 Control Register 2 (PW5CON2)
218
PWM5 Control Register 4 (PW5CON4)
220
PWM5 Control Register 5 (PW5CON5)
221
PWM5 Control Register 6 (PW5CON6)
222
PWM6 Period Register L, H (PW6PL, PW6PH)
223
PWM6 Duty Register L, H (PW6DL, PW6DH)
224
PWM6 Counter Register L, H (PW6CL, PW6CH)
225
PWM6 Control Register 0 (PW6CON0)
226
PWM6 Control Register 1 (PW6CON1)
228
PWM6 Control Register 2 (PW6CON2)
229
PWM6 Control Register 3 (PW6CON3)
231
PWM6 Control Register 4 (PW6CON4)
232
PWM6 Control Register 5 (PW6CON5)
233
PWM6 Control Register 6 (PW6CON6)
234
PWM7 Period Register L, H (PW7PL, PW7PH)
235
PWM7 Duty Register L, H(PW7DL, PW7DH)
236
PWM7 Counter Register L, H (PW7CL, PW7CH)
237
PWM7 Control Register 0 (PW7CON0)
238
PWM7 Control Register 1 (PW7CON1)
240
PWM7 Control Register 2 (PW7CON2)
241
PWM7 Control Register 4 (PW7CON4)
243
PWM7 Control Register 5 (PW7CON5)
244
PWM7 Control Register 6 (PW7CON6)
245
Description of Operation
246
PWM Single Mode / Continuous Mode
248
PWM Single Mode / One Shot Mode
250
PWM Coupled Mode / Continuous Mode
252
With no Dead-Time Specified
252
With Dead-Time Specified
254
PWM Coupled Mode / One Shot Mode
256
With no Dead-Time Specified
256
With Dead-Time Specified
258
PWM Control by the Software
260
Start/Stop/Clear Operation
260
Period and Duty Update
260
PWM Control by the External Input
261
Start/Stop/Clear Operation
261
Period and Duty Update
262
PWM Control Mode
263
Software Start Mode
263
Software Start Mode or External Start Mode
263
External Input Start Mode
265
Software Start or External Input Clear Mode
267
PWM Emergency Stop Operation
270
Specifying Port Registers
272
Functioning P34 Pin (PWM4) as PWM Output
272
Functioning P43 Pin (PWM4) as PWM Output
273
Functioning P35 Pin (PWM5) as PWM Output
274
Functioning P47 Pin (PWM5) as PWM Output
275
Chapter 12 Synchronous Serial Port (SSIO)
277
Features
277
Configuration
277
List of Pins
278
Description of Registers
279
List of Registers
279
Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH)
280
Serial Port Control Register (SIO0CON)
281
Serial Port Mode Register 0 (SIO0MOD0)
282
Serial Port Mode Register 1 (SIO0MOD1)
283
Description of Operation
284
Transmit Operation
284
Receive Operation
285
Transmit/Receive Operation
286
Specifying Port Registers
287
Functioning P42 (SOUT0: Output), P41 (SCK0: Input/Output), and P40 (SIN0: Input) as the SSIO/ "Master Mode
287
Functioning P42 (SOUT0: Output), P41 (SCK0: Input/Output), and P40 (SIN0: Input) as the SSIO/ "Slave Mode
288
Chapter 13 UART
289
Features
290
Configuration
290
List of Pins
291
Description of Registers
291
List of Registers
291
UART0 Transmit/Receive Buffer (UA0BUF)
292
UART1 Transmit/Receive Buffer (UA1BUF)
293
UART0 Control Register (UA0CON)
294
UART1 Control Register (UA1CON)
295
UART0 Mode Register 0 (UA0MOD0)
296
UART1 Mode Register 0 (UA1MOD0)
298
UART0 Mode Register 1 (UA0MOD1)
299
UART1 Mode Register 1 (UA1MOD1)
301
UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH)
303
UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH)
304
UART0 Status Register (UA0STAT)
305
UART1 Status Register (UA1STAT)
307
Description of Operation
309
Transfer Data Format
309
Baud Rate
310
Transmitted Data Direction
311
Transmit Operation (Full-Duplex Communication Mode)
312
Transmit Operation (Half-Duplex Communication Mode)
313
Receive Operation (Full-Duplex/Half-Duplex Communication Mode)
314
Detection of Start Bit
315
Sampling Timing
316
Specifying Port Registers
318
Functioning P53 (TXD1: Output) and P54 Pins (RXD0: Input) as the UART (Full-Duplex)
318
Functioning P43 (TXD1: Output) and P02 Pins (RXD0: Input) as the UART (Full-Duplex)
319
Functioning P85 (TXD1: Output) and P86 Pins (RXD0: Input) as the UART (Full-Duplex)
321
Functioning P53 (TXD1: Output) and P03 Pins (RXD1: Input) as the UART (Half-Duplex)
322
Functioning P55 (TXD0: Output) and P42 Pins (RXD0: Input) as the UART (Half-Duplex)
324
Functioning P43 (TXD0: Output) and P54 Pins (RXD0: Input) as the UART (Half-Duplex)
326
Functioning P85 (TXD1: Output) and P72 Pins (RXD1: Input) as the UART (Half-Duplex)
328
Chapter 14 I C Bus Interface
330
Features
331
Configuration
331
List of Pins
332
Description of Registers
333
List of Registers
333
C Bus 0 Receive Register I2C0RD
333
I 2 C Bus 0 Slave Address Register (I2C0SA)
335
I 2 C Bus 0 Transmit Data Register (I2C0TD)
336
I 2 C Bus 0 Control Register 0 (I2C0CON0)
337
I 2 C Bus 0 Mode Register L (I2C0MODL)
338
I 2 C Bus 0 Mode Register H (I2C0MODH)
339
I 2 C Bus 0 Status Register (I2C0STAT)
340
Description of Operation
341
Communication Operating Mode
341
Start Condition
341
Restart Condition
341
Slave Address Transmit Mode
341
Data Transmit Mode
341
Data Receive Mode
341
Control Register Setting Wait State
341
Stop Condition
341
Communication Operation Timing
342
Operation Waveforms
344
Specifying Port Registers
345
Chapter 15 Port 0
347
Features
347
Configuration
347
List of Pins
348
Description of Registers
349
List of Registers
349
Port 0 Data Register (P0D)
350
Port 0 Control Registers 0, 1 (P0CON0, P0CON1)
351
Description of Operation
352
Input Port Function
352
Chapter 16
354
Features
354
Configuration
354
List of Pins
355
Description of Registers
356
List of Registers
356
Port 1 Data Register (P1D)
357
Port 1 Direction Register (P1DIR)
358
Port 1 Control Registers 0,1 (P1CON0, P1CON1)
359
Description of Operation
361
Input Port Function
361
Input/Output Port Function
361
Secondary Function
361
Chapter 17 Port2
363
Features
363
Configuration
363
List of Pins
364
Description of Registers
365
List of Registers
365
Port 2 Data Register (P2D)
366
Port 2 Control Registers 0, 1 (P2CON0, P2CON1)
367
Port 2 Mode Registers 0, 1 (P2MOD0, P2MOD1)
369
Description of Operation
371
Output Port Function
371
Secondary, Tertiary, and Quaternary Functions
371
Chapter 18
374
Port3
374
Configuration
374
List of Pins
375
Description of Registers
376
List of Registers
376
Port 3 Data Register (P3D)
377
Port 3 Direction Register (P3DIR)
379
Port 3 Control Registers 0, 1 (P3CON0, P3CON1)
380
Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1)
382
Description of Operation
384
Input/Output Port Functions
384
Secondary and Tertiary Functions
384
Chapter 19 Port4
386
Features
386
Configuration
386
List of Pins
387
Description of Registers
388
List of Registers
388
Port 4 Data Register (P4D)
389
Port 4 Direction Register (P4DIR)
391
Port 4 Control Registers 0, 1 (P4CON0, P4CON1)
392
Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1)
394
Description of Operation
396
Input/Output Port Functions
396
Secondary, Tertiary, and Quaternary Functions
396
Chapter 20 Port5
398
Features
398
Configuration
398
List of Pins
399
Description of Registers
400
List of Registers
400
Port 5 Data Register (P5D)
401
Port 5 Direction Register (P5DIR)
403
Port 5 Control Registers 0, 1 (P5CON0, P5CON1)
404
Port 5 Mode Registers 0, 1 (P5MOD0, P5MOD1)
406
Description of Operation
408
Input/Output Port Functions
408
Secondary, Tertiary, and Quaternary Functions
408
Chapter 21 Port6
410
Features
410
Configuration
410
List of Pins
411
Description of Registers
412
List of Registers
412
Port 6 Data Register (P6D)
413
Port 6 Direction Register (P6DIR)
415
Port 6 Control Registers 0, 1 (P6CON0, P6CON1)
416
Port 6 Mode Registers 0, 1 (P6MOD0, P6MOD1)
418
Description of Operation
420
Input/Output Port Functions
420
Secondary, Tertiary, and Quaternary Functions
420
Chapter 22 Port7
422
Features
422
Configuration
422
List of Pins
423
Description of Registers
424
List of Registers
424
Port 7 Data Register (P7D)
425
Port 7 Direction Register (P7DIR)
426
Port 7 Mode Registers 0, 1 (P7MOD0, P7MOD1)
429
Description of Operation
431
Input/Output Port Functions
431
Secondary, Tertiary, and Quaternary Functions
431
Chapter 23 Port8
433
Features
433
Configuration
433
List of Pins
434
Description of Registers
435
List of Registers
435
Port 8 Data Register (P8D)
436
Port 8 Direction Register (P8DIR)
438
Port 8 Control Registers 0, 1 (P8CON0, P8CON1)
439
Port 8 Mode Registers 0, 1 (P8MOD0, P8MOD1)
441
Description of Operation
443
Input/Output Port Functions
443
Secondary and Tertiary Functions
443
Chapter 24 Successive Approximation Type A/D Converter (SA-ADC)
445
Features
445
Configuration
445
Description of Registers
447
List of Registers
447
SA-ADC Result Register 0L (SADR0L)
448
SA-ADC Result Register 0H (SADR0H)
448
SA-ADC Result Register 1L (SADR1L)
449
SA-ADC Result Register 1H (SADR1H)
449
SA-ADC Result Register 2L (SADR2L)
450
SA-ADC Result Register 2H (SADR2H)
450
SA-ADC Result Register 3L (SADR3L)
451
SA-ADC Result Register 3H (SADR3H)
451
SA-ADC Result Register 4L (SADR4L)
452
SA-ADC Result Register 4H (SADR4H)
452
SA-ADC Result Register 5L (SADR5L)
453
SA-ADC Result Register 5H (SADR5H)
453
SA-ADC Result Register 6L (SADR6L)
454
SA-ADC Result Register 6H (SADR6H)
454
SA-ADC Result Register 7L (SADR7L)
455
SA-ADC Result Register 7H (SADR7H)
455
SA-ADC Result Register 8L (SADR8L)
456
SA-ADC Result Register 8H (SADR8H)
456
SA-ADC Result Register 9L (SADR9L)
457
SA-ADC Result Register 9H (SADR9H)
457
SA-ADC Result Register al (SADRAL)
458
SA-ADC Result Register AH (SADRAH)
458
SA-ADC Result Register BL (SADRBL)
459
SA-ADC Result Register BH (SADRBH)
459
SA-ADC Control Register 0 (SADCON0)
460
SA-ADC Control Register 1 (SADCON1)
461
SA-ADC Mode Register 0 (SADMOD0)
462
SA-ADC Mode Register 1 (SADMOD1)
464
Description of Operation
465
Operation of the Successive Approximation Type A/D Converter
466
Chapter 25 General Description
468
Features
468
Configuration
468
List of Pins
468
Description of Registers
469
List of Registers
469
Comparator 0 Control Register 0 (CMP0CON0)
470
Comparator 0 Control Register 1 (CMP0CON1)
471
Description of Operation
472
Comparator Functions
472
Interrupt Request
473
Chapter 26 LLD (Low Level Detector)
474
General Description
475
Features
475
Configuration
475
Description of Registers
476
List of Registers
476
LLD Circuit Control Register 1 (LLDCON1)
477
Description of Operation
478
Threshold Voltage
478
Operation of LLD Circuit
478
Chapter 27 Power Supply Circuit
480
Features
481
Configuration
481
List of Pins
481
Description of Operation
482
Chapter 28 On-Chip Debug Function
483
How to Connect the On-Chip Debug Emulator
484
Flash Memory Rewrite Function
486
Features
487
Description of Registers
488
List of Registers
488
Flash Control Register (FLASHCON)
494
Flash Acceptor (FLASHACP)
495
Flash Segment Register (FLASHSEG)
495
Flash Self Register (FLASHSLF)
496
Flash Remap Register (REMAPADD)
497
Description of Operation
498
Block Erase Function
500
Sector Erase Function
502
1-Word Write Function
504
Boot Area Remap Function by Software
506
Notes in Use
507
Chapter 30 Code-Option
509
Features
509
Description of Registers
509
List of Registers
509
Code-Option Register 0 (CODEOP0)
510
The Setting Method of the Code-Option Data
511
Code-Option Data Format
511
Code-Option Programming Method
511
Chapter 31 External Interrupt Control Circuit
512
Features
513
Configuration
513
List of Pins
514
Description of Registers
515
List of Registers
515
External Interrupt Control Register 0, 1 (EXICON0, EXICON1)
516
External Interrupt Control Register 2 (EXICON2)
517
Description of Operation
519
External Interrupt
519
Interrupt Request
519
Appendix A Contents of Registers
522
Appendix B Package Dimensions
530
Appendix C Electrical Characteristics
537
Appendix D Application Circuit Example
548
Appendix E Check List
550
Revision History
554
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