Sony CDX-G1200U Service Manual page 30

CDX-G1200U/G1201U/G1202U/G1280UM
MAIN BOARD IC1305 LC78615E-01US-H (RF AMP, DIGITAL SERVO PROCESSOR)
Pin No. Pin Name
1 EFMIN
2 RFOUT
3 LPF
4 PHLPF
5 AIN
6 CIN
7 BIN
8 DIN
9 SLCISET
10 RFMON
11 VREF
12 JITTC
13 EIN
14 FIN
15 TE
16 TEIN
17 AVSS
18 AVDD
19 LDD
20 LDS
21 FDO
22 TDO
23 SLDO
24 SPDO
25 VVSS1
26, 27 PDOUT1, PDOUT0
28 PCKIST
29 VVDD1
30, 31 NC
32 DVDD15
33 DVDD
34 DVSS
35 TEST
36 L_SW
37, 38 NC
39 OPCDM
40 SBSY
41 SFSY
42 PW
43 SBCK
44 CE
45 CL
46 DI
47 DO
48 RESB
49 BUSYB
50 MCLK
51 LRCK
52 BCK
53 DATA
54 to 56 SMOIN0 to SMOIN2
57 MODE
58 DVDD15
59 DVDD
60 XVSS
61 XOUT
62 XIN
63 XVDD
64 SLCO
30
I/O
I RF signal input terminal
O RF signal output terminal
- External low-pass fi lter capacitor connection terminal for DC level detection of RF signal
- External low-pass fi lter capacitor connection terminal for defect detection
I Main beam (B) input from the CD mechanism deck block
I Main beam (C) input from the CD mechanism deck block
I Main beam (A) input from the CD mechanism deck block
I Main beam (C) input from the CD mechanism deck block
- External resistor connection terminal for current setting of SLCO output
O Internal analog signal monitor terminal of LSI
O Reference voltage (+1.65V) output terminal for RF
- External capacitor connection terminal for jitter detection
I Sub beam (F) input from the CD mechanism deck block
I Sub beam (E) input from the CD mechanism deck block
O Tracking error signal output terminal
I Tracking error signal input terminal
- Ground terminal (analog system)
- Power supply terminal (+3.3V) (analog system)
O Laser power control signal output to the CD mechanism deck block
I Laser power detection signal input from the CD mechanism deck block
O Focus coil control signal output to the CD mechanism deck block
O Tracking coil control signal output to the CD mechanism deck block
O Sled motor control signal output to the CD mechanism deck block
O Spindle motor control signal output to the CD mechanism deck block
- Ground terminal (for EFMPLL)
O Charge pump output terminal for EFMPLL
- External resistor connection terminal for charge pump current setting for EFMPLL
- Power supply terminal (+3.3V) (for EFMPLL)
- Not used
- External power capacitor connection terminal for digital system power
- Power supply terminal (+3.3V) (digital system)
- Ground terminal (digital system)
I Test mode setting terminal
I Limit in detection switch input terminal
- Not used
O External decode permission signal output to the audio DSP
O CD sub-code block sync signal output to the audio DSP
O CD sub-code fl ame sync signal output to the audio DSP
O CD sub-code PW data output to the audio DSP
O CD sub-code data transfer clock signal output to the audio DSP
I Chip enable signal input from the audio DSP
I Serial data transfer clock signal input from the audio DSP
I Serial data input from the audio DSP
O Serial data output to the audio DSP
I Reset signal input from the audio DSP
O Busy signal output to the audio DSP
O Master clock signal output to the audio DSP
O L/R sampling clock signal output to the audio DSP
O Bit clock signal output to the audio DSP
O Audio data output to the audio DSP
O Servo internal signal monitor output terminal
I LSI operation mode setting terminal
- External power capacitor connection terminal for digital system power
- Power supply terminal (+3.3V) (digital system)
- Ground terminal (for oscillation circuit)
O System clock output terminal (16.934 MHz)
I System clock input terminal (16.934 MHz)
- Power supply terminal (+3.3V) (for oscillation circuit)
O Slice level control signal output terminal
Description
Not used
Fixed at "L"
"L": reset
"L": busy
Not used
Fixed at "H"