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RadiSys EPC-100 Hardware Reference Manual

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EPC
-100
Hardware Reference
®
RadiSys Corporation
5445 NE Dawson Creek Drive
Hillsboro, OR 97124
Phone: (503) 615-1100
Fax: (503) 615-1150
http://www.radisys.com
_____________________________________________________________________
07-0930-00
August 1997

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  • Page 1 ® -100 Hardware Reference ® RadiSys Corporation 5445 NE Dawson Creek Drive Hillsboro, OR 97124 Phone: (503) 615-1100 Fax: (503) 615-1150 http://www.radisys.com _____________________________________________________________________ 07-0930-00 August 1997...
  • Page 2 Microsoft and MS-DOS are registered trademarks of Microsoft Corporation. PhoenixBIOS and NuBIOS are trademarks of Phoenix Technologies, Ltd. RadiSys and EPC are registered trademarks and EPConnect is a trademark of RadiSys Corporation. All other trademarks and registered trademarks are the property of their respective owners.

  • Page 3: Table Of Contents

    Other Specifications................1-8 Chapter 2 - Installation..................2-1 Introduction ....................2-1 Inserting the EPC-100...................2-2 Removing the EPC-100 ................2-2 Configuring the EPC-100 ................2-2 Connecting Peripherals to the EPC-100..........2-2 SCSI Termination ................2-3 System Software Installation ................2-3 Operating System Software..............2-3 Video Driver Software .................2-3 Ethernet Software.................2-3 Chapter 3 - BIOS Configuration................3-1...
  • Page 4 EPC-100 Hardware Reference IDE Adapter Sub-menu ................3-5 Type .....................3-6 Multi-Sector Transfers .................3-6 LBA Mode Control ................3-6 32-bit I/O....................3-6 Transfer Mode..................3-7 Boot Options Sub-menu................3-8 Boot Delay: ..................3-8 Boot Sequence:..................3-8 Setup Prompt:..................3-9 POST Errors:..................3-9 Floppy Check: ..................3-9 Summary Screen: .................3-9 Extended Memory Test:...............3-9 Keyboard Features Menu................3-10...
  • Page 5 EPC-100 Hardware Reference Advanced Chipset Control Sub-menu............3-17 DRAM Speed..................3-17 DMA Aliasing..................3-17 8-bit I/O Recovery ................3-18 16-bit I/O Recovery ................3-18 IRQ 12 used by ..................3-18 ECC/Parity Config ................3-18 Memory Cache Sub-menu ................3-19 Internal Cache ..................3-19 External Cache ..................3-19 Cache System BIOS Area ..............3-19 Cache Video BIOS Area ..............3-20...
  • Page 6 EPC-100 Hardware Reference Chapter 4 - Theory of Operation ...............4-1 Introduction ....................4-1 Block Diagram....................4-2 Processor Module Daughterboard..............4-2 Cache Memory .....................4-2 Main System Memory ..................4-2 Upgrading Main System Memory..............4-4 Memory Map ....................4-4 Interrupt Usage .....................4-5 Watchdog Timer ...................4-6 Flash Boot Device..................4-7 Keyboard/Mouse Controller .................4-7...
  • Page 7 EPC-100 Hardware Reference Appendix D - Error Messages ................D-1 Introduction ....................D-1 Boot Failures ....................D-1 Page vii...
  • Page 8 Figure 3-8. Advanced Chipset Control Sub-menu...........3-17 Figure 3-9. Memory Cache Sub-menu..............3-19 Figure 3-10. Memory Shadow Sub-menu..............3-21 Figure 3-11. Advanced Power Management Sub-menu..........3-23 Figure 3-12. Exit Menu...................3-28 Figure 4-1. Block Diagram of the EPC-100............. 4-3 Page viii...

  • Page 9: Chapter 1 - Product Description

    This manual was written to provide detailed hardware reference information for OEMs, system integrators, and others who use the EPC-100 as a component of their cPCI bus systems. The reader should be able to install the EPC-100 and configure the BIOS based on the information in this manual.
  • Page 10 Chipset and I/O Map. Maps the addresses used for I/O and by the chipset registers. Appendix B Interrupts and DMA Channels. Shows the DMA channel and IRQ assignments to the peripherals supported by the EPC-100. Appendix C Connectors. Details the location, form, and pin-outs of the connectors used in the EPC-100.

  • Page 11: Overview

    Product Description Overview The EPC-100 is a highly integrated PC-compatible computer designed for use in the full 32-bit CompactPCI (cPCI) bus environment. The EPC-100 is a two-slot 6U cPCI bus module that supports up to seven 3U/6U cPCI peripheral slots via a DEC 21150 PCI-PCI bridge chip.

  • Page 12: Cpci Bus

    Optional on-board 2.5" ATA hard drive. cPCI bus The cPCI bus is accessed from the EPC-100’s PCI bus via a DEC 21150 PCI-PCI bridge. This bridge connects the onboard PCI bus (bus 0) with the mainframe’s cPCI bus (bus 1), which may have as many as seven additional cPCI devices connected to it.

  • Page 13: Cpci Device Interface

    Device Interface The EPC-100 implements a 32 bit CompactPCI system slot board capable of driving seven CompactPCI slots. A DEC 21150 PCI-PCI bridge chip is used to interface between the base board’s local PCI bus and the CompactPCI bus. The bridge chip controls a layer of buffers between it and the CompactPCI bus and has a glueless interface to the local PCI bus.

  • Page 14: Specifications

    Product Description Specifications Environmental Specifications The following are the environmental specifications for the EPC-100. Characteristic Value Temperature operating 100MHz: 0-60°C at point of entry of forced air derated 2°C per 1000 ft (300 m) over 6600 ft (2000m) 133MHz: 0-60°C at point of entry of forced air derated 2°C per 1000 ft (300 m) over 6600 ft...
  • Page 15 HDD storage 5mm P-P (5 - 22 Hz) 5G (max.) (22 - 400 Hz) Shock operating 1470m/s (150G) (2ms half sine wave) with HDD storage 2450m/s (250G) (2ms half sine wave) Table 1-1 (continued). EPC-100 Environmental Specifications EPC-100 Hardware Reference...

  • Page 16: Other Specifications

    2.7 lb. (1.3 kg) Dimensions see cPCI Specification Rev. 1.0 for a 6U 2-slot module. Safety UL 1244 (not tested) IEC 1010.1 (1990) Incl. Amend 1 (1992)/EN61010 (1993) CSA C22. #1010.1 (1992) (not tested) Table 1-2. Additional EPC-100 Specifications. EPC-100 Hardware Reference...
  • Page 17 Product Description CE Mark CISPR 11:1990/EN 55011(1991): Group 1 Class A IEC 801-2:1991/EN50082-1 (1992): 4kV CD, 8kV AD IEC 801-3:1984/EN50082-1 (1992): 3V/m IEC 801-4:1988/EN50082-1 (1992): 1kV Power Line Low Voltage Directive 89/336/EEC Table 1-2. Additional EPC-100 Specifications. (cont’d) EPC-100 Hardware Reference...

  • Page 18: Chapter 2 - Installation

    Chapter 2 - Installation Introduction This chapter tells you how to install the EPC-100 in a Compact PCI (cPCI) chassis. There are three user-configurable jumpers. One enables/disables the CPU fan failure test during Power On Self-test (POST). The second enables/disables the SCSI termination, so that the EPC-100 can be used as any element in a SCSI daisy-chain.

  • Page 19: Inserting The Epc-100

    Then pull outward on the extractor handles until the EPC-100 disengages from the rear connector. Slide the EPC-100 out of the cPCI chassis and place it in the anti-static bag that it came in. Configuring the EPC-100...

  • Page 20: Scsi Termination

    When you configure SCSI peripherals to work with the EPC-100, you need to consider the placement of the EPC-100 in the SCSI chain. If the EPC-100 is to be the last device in the SCSI chain, it must be terminated. The SCSI termination jumper placement is described in Appendix C - Connectors and Jumpers.

  • Page 21: Ethernet Software

    The Ethernet driver software is supplied on a diskette with part number 80-1677-00 labeled Ethernet Drivers, DEC 21143/Windows NT 4.0. If you need to install a different driver for an operating system other than Windows NT 4.0, consult Digital Equipment Corporation at http://www.digital.com/info/semiconductor/support.htm. EPC-100 Hardware Reference...

  • Page 22: Chapter 3 - Bios Configuration

    Refer to Appendix D - Error Messages & Diagnosis. BIOS Setup Screens The EPC-100’s BIOS contains a setup function to display and modify the system configuration. This information is maintained in the EPC-100’s nonvolatile CMOS RAM and is used by the BIOS to initialize the EPC-100 hardware.

  • Page 23: Figure 3-1. Bios Setup Screen Menu Map

    Once the desired entry appears, use the up and down arrow to move to the next field. The fields in each menu and sub-menu are explained below the menu. Additional help information is available in the help area on the Setup screen. EPC-100 Hardware Reference...

  • Page 24: Main Setup Menu

    These fields are headings for menus that allow entering complete disk drive information. Once the information is entered for the drive, the entry in the Main Menu shows the drive selected. See “IDE Adapter Sub-menu” on page 3-5 for more information. EPC-100 Hardware Reference...

  • Page 25: Video System

    This field is not editable and displays the amount of conventional memory (below 1MB). No user interaction is required. Extended Memory This field is not editable and displays the amount of extended memory (above 1MB). No user interaction is required. EPC-100 Hardware Reference...

  • Page 26: Ide Adapter Sub-Menu

    The specific cylinder, head, sector information as listed on the label attached to the drive at the factory must be manually entered on this screen using a “User” type described below. EPC-100 Hardware Reference...

  • Page 27: Type

    This selection is not affected by autotyping. If the PCI IDE controller in the T2 chipset is being used, then this option should be set to “Enabled” to maximize system performance. The default is “Enabled”. EPC-100 Hardware Reference...

  • Page 28: Transfer Mode

    The fast DMA modes take full advantage of the onboard bus mastering hard disk controller and should yield the highest performance when used in conjunction with multitasking operating systems that support it. The default is “Standard”. EPC-100 Hardware Reference...

  • Page 29: Boot Options Sub-Menu

    Booting can occur from a floppy in the A: drive or directly from the fixed disk drive. To reduce the amount of time required to boot, the boot sequence should be set to “C: only”. Note that the C: drive may be either an IDE or SCSI drive. EPC-100 Hardware Reference...

  • Page 30: Setup Prompt

    This option is used to enable or disable a summary of the system configuration, which displays before the operating system starts to load. To speed up the boot process, the summary screen should be disabled. The default is “Enabled”. EPC-100 Hardware Reference...

  • Page 31: Extended Memory Test

    BIOS Configuration Extended Memory Test: This option enables or disables testing of memory above 1MB during boot-up. To speed up the boot process, disable the extended memory test. The default is “Enabled”. EPC-100 Hardware Reference 3-10...

  • Page 32: Keyboard Features Menu

    This option is used to set the auto-repeat rate if holding a key down on the keyboard. The rates can be set to one of: “2/sec”, “6/sec”, “10/sec”, “13.3/sec”, “18.5/sec”, “21.8/sec”, 26.7/sec”, and “30/sec”. The default rate is “30/sec”. EPC-100 Hardware Reference 3-11...

  • Page 33: Keyboard Auto-Repeat Delay

    This option is used to set the delay between when a key is pressed and when the auto- repeat feature begins. Options are “1/4 sec”, “1/2 sec”, “3/4 sec”, and “1 sec” . The default delay is “1/4 sec”. EPC-100 Hardware Reference 3-12...

  • Page 34: Advanced Menu

    This option is used to select the Integrated Peripherals sub-menu in order to configure the onboard I/O ports, IDE controller, and Ethernet controller. Advanced Chipset Control Sub-menu This option is used to select the Advanced Chipset Control sub-menu in order to configure the chipset. EPC-100 Hardware Reference 3-13...

  • Page 35: Plug & Play Os

    These items control the loading (shadowing) of BIOS extensions contained in the FBD main block #3. Note that there are actually three groups of Setup items to control the shadowing of up to three BIOS extensions. The screen graphic only shows the first group. EPC-100 Hardware Reference 3-14...

  • Page 36: Bios Extension Offset In Fbd

    CC0000h through DFFFFh in 8KB increments. The default is “D0000h”. BIOS Extension Size: This option selects the number of bytes to copy from the FBD into shadow memory. BIOS extension sizes can be selected in 8KB increments from 2000h through 10000h. The default is “2000h”. EPC-100 Hardware Reference 3-15...

  • Page 37: Integrated Peripherals Sub-Menu

    “2F8, IRQ3”, “3E8, IRQ4”, “2E8, IRQ3”, and “Auto”. “Auto” causes the System BIOS to choose a base address and IRQ setting that avoids conflicting with the other ports. The default I/O base and IRQ for this COM port are “2F8, IRQ3”. EPC-100 Hardware Reference 3-16...

  • Page 38: Lpt Port

    IDE channels. Onboard Ethernet controller This option enables or disables the onboard PCIbus Ethernet controller. The default is “Enabled”. Onboard SCSI controller This option enables or disables the onboard PCIbus SCSI controller. The default is “Enabled”. EPC-100 Hardware Reference 3-17...

  • Page 39: Advanced Chipset Control Sub-Menu

    This option allows I/O accesses to the range 90-9Fh (except 92h) to alias to 80-8Fh. If an ISAbus device uses the address range 90-9Fh, then this option must be disabled to access the device. The default is “Enabled”. EPC-100 Hardware Reference 3-18...

  • Page 40: 8-Bit I/O Recovery

    “PCI bus” to allow an ISAbus peripheral to use this interrupt line. Systems using a PS/2 mouse must have this option set to “PS/2 Mouse” for the mouse to operate correctly. Since the EPC-100 supports the PS/2 mouse connector, the default is “PS/2 Mouse”.

  • Page 41: Memory Cache Sub-Menu

    This option enables or disables the Level 2 (L2) cache. The default is “Enabled”. Cache System BIOS Area This option enables or disables caching of the System BIOS area in the E0000h through FFFFFh DRAM area. The default is “Enabled”. EPC-100 Hardware Reference 3-20...

  • Page 42: Cache Video Bios Area

    C7FFFh region. The default is “Enabled”. Cache Memory Regions These options enable or disable caching of the associated memory regions. When BIOS extensions are present in these regions, enabling caching for that region increases performance. The default is “Disabled”. EPC-100 Hardware Reference 3-21...

  • Page 43: Memory Shadow Sub-Menu

    BIOS extension to be shadowed is larger than 16KB. System Shadow This option is not editable since the System BIOS is always shadowed. Video Shadow This option is not editable since the VGA BIOS is always shadowed. EPC-100 Hardware Reference 3-22...

  • Page 44: Shadow Memory Regions

    BIOS Configuration Shadow Memory Regions These options enable or disable shadowing for the associated memory region. The default is “Disabled”. EPC-100 Hardware Reference 3-23...

  • Page 45: Power Management Menu

    Figure 3-11. Advanced Power Management Sub-menu. Power Savings This option enables and selects the kind of power management, or it disables power management. The options are: “Off”, “Customize”, “Maximum Performance”, and “Maximum Power Savings. The default is “Off”. EPC-100 Hardware Reference 3-24...

  • Page 46: Standby Timeout

    This option enables or disables the Break Event for IRQ3. The options are: “Disabled” and “Enabled”. The default is “Disabled”. IRQ4 (Break Event, COM A) This option enables or disables the Break Event for IRQ4. The options are: “Disabled” and “Enabled”. The default is “Disabled”. EPC-100 Hardware Reference 3-25...
  • Page 47 This option enables or disables the Break Event for IRQ12. The options are: “Disabled” and “Enabled”. The default is “Disabled”. IRQ13 (System Event, Numeric Coprocessor) This option enables or disables the System Event for IRQ13. The options are: “Disabled” and “Enabled”. The default is “Disabled”. EPC-100 Hardware Reference 3-26...
  • Page 48 “Disabled” and “Enabled”. The default is “Disabled”. NMI (System Event, PIIX3 Bridge when SERR# or IOCHK# is asserted by software) This option enables or disables the System Event for NMI. The options are: “Disabled” and “Enabled”. The default is “Disabled”. EPC-100 Hardware Reference 3-27...

  • Page 49: Exit Menu

    Setup was entered. The system reboots with the old values. Get default values This option is used to reset the Setup values to the original, default values that were set at the factory, before any suppliers or other end users made changes. EPC-100 Hardware Reference 3-28...

  • Page 50: Backup Cmos To Flash

    This option is used to load the system with the previous values before an editing session started. Save Changes This option is used to save the edits made during a session. Exit & Update BIOS This option is used to initiate a System BIOS update. EPC-100 Hardware Reference 3-29...

  • Page 51: Chapter 4 - Theory Of Operation

    Chapter 4 - Theory of Operation Introduction The EPC-100 is a double-slot 6U size module designed to the cPCI Revision 1.0 specification. It consists of a main board with the following connectors: On the front panel: PS/2 style Keyboard Connector...

  • Page 52: Block Diagram

    EIDE Controller consisting of two master and two slave drive controllers System BIOS implemented as a Flash ROM supporting BIOS extensions Block Diagram Figure 4-1 shows the division and interconnection of EPC-100 functions. These are described below. Processor Module Daughterboard An Intel Pentium processor (with integral FPU) runs at 100, 133, 166, or 200 MHz.

  • Page 53: Figure 4-1. Block Diagram Of The Epc-100

    Theory of Operation Figure 4-1. Block Diagram of the EPC-100. EPC-100 Hardware Reference...

  • Page 54: Upgrading Main System Memory

    The area between 0 and 1 MB is largely defined by the IBM PC/AT architecture. The area between 1 MB and 256 MB depends on how much DRAM is installed in the EPC-100. Memory addresses from the Pentium or Pentium Pro between 0 and 4 MB (0FFFFFFFh) is mapped as follows:...

  • Page 55: Interrupt Usage

    System BIOS Shadow 10000000 - FFF7FFFF ISA Bus (aliased) FFF80000 - FFFFFFFF BIOS Table 4-2. System Memory Map. Interrupt Usage The EPC-100 PC-compatible interrupt usage is as follows: Interrupt Interrupt Function IRQ0 System timer (internal PIIX3 connection) IRQ1 Keyboard controller...

  • Page 56: Watchdog Timer

    11 interrupts (IRQ[15,14, 12-9, 7-3]) using the MBIRQx Route Control Register. Note also that the secondary IDE channel is assigned to MIRQ0 by the PIIX3 (when not using the APIC, as on EPC-100). Table 4-3. Interrupt Usage.

  • Page 57: Flash Boot Device

    The boot block is NEVER reprogrammed by the user, even when the main and parameter blocks are reprogrammed. The capability to program the boot block is provided to facilitate changes by RadiSys manufacturing. A “force recovery” jumper is provided that is connected to the P1-3 input of the 82C4PE keyboard controller.

  • Page 58: Bios Rom And Rom Shadowing

    Theory of Operation BIOS ROM and ROM Shadowing The EPC-100 utilizes a Flash Boot Device (FBD) as its BIOS ROM. The BIOS ROM is mapped into the top of the processor’s 32-bit address space. The BIOS consists of a 16 KByte boot block and the System BIOS in the 96KB Main block and both 8KB parameter blocks.

  • Page 59: Cmos Save And Restore

    Chapter 3 - BIOS Configuration. Ethernet Controller The EPC-100 implements 10/100BaseT Ethernet communications by using the DEC 21143-TA Ethernet Controller chip coupled to a QSI 6611 Physical Interface (PHY) chip that provides wave shaping and line filtering for both 10- and 100-Mbps operation, adaptive equalization, baseline wander compensation, 10/100 switching, and clock generation and recovery.

  • Page 60: Battery

    +5V power supply voltage can supply power and neither power source affects the other. The 3.0V lithium battery supplied with the EPC-100 is a Renata CR2032 “coin cell” or equivalent. It is mounted on the main circuit board, beneath the EPC-100 Video Board.

  • Page 61: Peripheral Ports

    Figure 4-3. Replacing the Lithium CMOS Battery. CAUTION: There is danger of explosion if battery is incorrectly replaced. Replace only with same or equivalent type recommended by RadiSys. Dispose of used batteries according to manufacturer’s instructions. Peripheral Ports The I/O address and IRQ of the peripheral ports are determined by the CMOS parameters established by default and modified via BIOS Setup screens.
  • Page 62 COM B can be disabled in the BIOS Setup Integrated Peripherals Sub- Menu to free up the I/O address and interrupt for usage by other expansion products. COM B is mapped to I/O address 2F8h-2FFh and uses interrupt IRQ3. EPC-100 Hardware Reference 4-12...

  • Page 63: Parallel Port

    Two host-side USB ports are provided on the front panel. The USB root hub is built into the PIIX3 chip as part of the 82430HX chip set. The USB’s PCI configuration EPC-100 Hardware Reference 4-13...

  • Page 64: Front Panel Indicators

    (10BASE–T link or 100BASE–TX link). When off, the adapter did not find a valid 10/100BASE-TX link on its network connection; transmit and receive are not possible. Note that this LED is always off when using 10BASE2. EPC-100 Hardware Reference 4-14...
  • Page 65 World Wide Web RadiSys maintains an active site on the World Wide Web. The home-page URL is http://www.radisys.com. The site contains current information about the company and locations of sales offices, new and existing products, contacts for sales, service, and technical support information.
  • Page 66 RadiSys analyzes the product after it is received. When instructed to do so, RadiSys informs the customer of repair costs for authorization.
  • Page 67 The RMA Dispatcher will issue a Returned Materials Authorization (RMA) number, a code number by which RadiSys tracks the product while it is being processed. Once you receive the RMA number, follow the instructions of the technical support representative and return the product to RadiSys, freight prepaid.
  • Page 68 Support and Service Other Countries Use the RadiSys web site to contact us, or contact the sales organization from which you purchased your RadiSys product for service and support. EPC-100 Hardware Reference...

  • Page 69: Appendix A - Chipset And I/O Map

    This section contains the port I/O addresses for the address-mapped devices in the EPC-100. As is standard for the ISA bus, the A[15:0] bits are decoded for the 0200h-03FFh range and A[15] and A[9:0] are decoded for addresses above 8000h.
  • Page 70 Interrupt controller 1 Port 0 Port 1 Counter-Timer functions Timer Counter 0 Counter 1 Counter 2 Control (W) Keyboard Port Keyboard controller Data I/O register NMI status PIIX3 Keyboard controller Command/status register - resets IRQ1 and 12/M EPC-100 Hardware Reference...
  • Page 71 RTC data register (64 bits) seconds seconds alarm minutes minutes alarm hours hours alarm day of week date of month month year status A status B status C status D E…3F Phoenix NuBIOS Phoenix BIOS Status Information EPC-100 Hardware Reference...
  • Page 72 Port 1 Power Management Controller Power Management Control Status DMA Controller Channel 4 address Channel 4 count Channel 5 address Channel 5 count Channel 6 address Channel 6 count Channel 7 address Channel 7 count Command/status DMA request EPC-100 Hardware Reference...
  • Page 73 Reset coprocessor IDE Control Secondary IDE Control Data Register Sector Count Sector Number Cylinder LSB Cylinder MSB Drive/ Head Status/ Command Primary IDE Control Data Register Sector Count Sector Number Cylinder LSB Cylinder MSB Drive/ Head Status/ Command EPC-100 Hardware Reference...
  • Page 74 Line status register Modem status register Parallel I/O (LPT1) Port LPT1 parallel port Printer data register Printer status register Printer control register EPP Registers Address Port Data Port 0 Data Port 1 Data Port 2 Data Port 3 EPC-100 Hardware Reference...
  • Page 75 Feature control readback Miscellaneous output readback Graphics controller index Graphics controller data CRT controller index CRT controller data Feature control, pinput status Configuration 37C651 Super I/O Combo chip Configuration 37C651 Super I/O Combo chip 46E8 Adapter Sleep EPC-100 Hardware Reference...
  • Page 76 Watchdog Control and System Slot ID 8150 Watchdog Control and Usage System Slot ID WDTV - Watchdog Timer Value WDTV WDIE - Watchdog Timer Interrupt Event WDEV - Watchdog Event ENEV - ENUM# Event ENIE - ENUM# Interrupt Event Reserved Reserved EPC-100 Hardware Reference...
  • Page 77 A write of the this register has a side effect of resetting the watchdog timer and the watchdog event indication register (bit 3) and the hotswap indication register (bit 4). Please refer to the Watchdog Timer section of Chapter 4, Theory of Operation for more information about the watchdog timer. EPC-100 Hardware Reference...
  • Page 78 Chipset and I/O Map If you are using the watchdog timer, it is required to write to this register within the defined period of the timer to prevent generating either an interrupt or a warm reset. EPC-100 Hardware Reference A-10...

  • Page 79: Appendix B - Interrupts

    Floppy Disk or Unassigned IRQ7 LPT1: or Unassigned IRQ8 Real Time Clock IRQ9 Watchdog Timer IRQ10 Unassigned IRQ11 Unassigned IRQ12 PS/2 Mouse IRQ13 Floating Point Unit IRQ14 Primary IDE IRQ15 Secondary IDE ISAbus IOCCHK/Memory Parity Error Power Management/ECC/USB EPC-100 Hardware Reference...

  • Page 80: Appendix C - Connectors And Jumpers

    Connectors Appendix C - Connectors and Jumpers Introduction This section details the connectors and jumpers used by the EPC-100 and gives the signal pinout of each connector. 8Q8D S@T@U T8TD T8TD! 8PHÃ6 76T@! 8PHÃ7 76T@UY 76T@UY HPVT@ Figure C-1. EPC-100 Front Panel Connectors.
  • Page 81 Table C-1. Keyboard Pin-Out. Mouse Connector The PS/2 mouse connector is a 6-pin mini-DIN connector defined as follows: Pin Signal Pin Signal 1 Data 2 not used Clock 3 Ground not used Table C-2. Mouse Pin-Out. EPC-100 Hardware Reference...

  • Page 82: Rs-232 Ports (Com A, Com B

    Signal ground 6 DB4 Signal ground 7 DB5 Signal ground 8 DB6 Signal ground 9 DB7 Signal Ground 10 Acknowledge Signal ground 11 Busy Signal ground 12 Paper End Signal ground 13 Select Table C-4. DB-25 Pin-Out. EPC-100 Hardware Reference...

  • Page 83: Svga Connector

    Table C-5. DB-15 Pin-Out. RJ45 Connector The DTE RJ45 phone jack that supplies the 10Base-TX/100Base-TX interface to the Ethernet controller is defined as follows: Signal No connect No connect No connect No connect Table C-6. RJ45 Phone Jack Pin-Out. EPC-100 Hardware Reference...

  • Page 84: Dual Usb Connector

    The USB (Universal Serial Bus) connector is a dual, stacked 4-pin connector defined as follows: Description Mechanical Shield Ground Solder Lug VCC (1Amp Fused) DATA- DATA+ Signal Ground Mechanical Shield Ground Solder Lug Table C-7. Dual USB Connector EPC-100 Hardware Reference...

  • Page 85: Scsi-2 Connector

    Signal GND Signal GND ~ATN Signal GND Signal GND Signal GND ~BSY Signal GND ~ACK Signal GND ~RST Signal GND ~MSG Signal GND ~SEL Signal GND ~C/D Signal GND ~REQ Signal GND ~I/O Table C-8. SCSI-2 Connector EPC-100 Hardware Reference...

  • Page 86: Eide (Primary) Connector

    41-44 of the connector. If you wish to connect a 40-pin connector, omit these power supply lines. The pins and signals are defined in the following table: Signal Signal ~RST N.C. ~IOW ~IOR IORDY ~DAK IOCS16 N.C. ~CS0 ~CS1 Table C-9. Primary EIDE Connector EPC-100 Hardware Reference...

  • Page 87: Floppy Disk Drive Connector

    INDEX Vcc* MTR1 Vcc* MTR0 STEP WDATA WGATE TRK0 WRPRT RDATA HDSEL DSKCHG * - Vcc if jumper JP2 is installed (RadiSys floppy drive) N.C. if jumper JP2 is not installed. Table C-11. Floppy Disk Drive Connector. EPC-100 Hardware Reference...

  • Page 88: Compactpci J1 & J2 Connectors

    AD[23] AD[22] AD[21] 3.3V AD[20] AD[19] AD[18] AD[17] AD[16] C/BE[2]# 12-14 Key Area FRAME# IRDY# TRDY# 3.3V × DEVSEL V(I/O) STOP# LOCK# 3.3V SDONE SBO# PERR# SERR# C/BE[1]# 3.3V 3.3V AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] V(I/O) EPC-100 Hardware Reference...
  • Page 89 AD[52] V(I/O) AD[51] AD[50] AD[49] AD[48] AD[47] AD[46] AD[45] V(I/O) AD[44] AD[43] AD[42] AD[41] AD[40] AD[39] AD[38] V(I/O) AD[37] AD[36] AD[35] AD[34] AD[33] AD[32] BRSV FAL# REQ5# GNT5# BRSV BRSV DEG# BRSV BRSV PRST# REQ6# GNT6# EPC-100 Hardware Reference C-10...
  • Page 90 C27 is grounded at the system slot only. Remaining slots leave C27 unconnected. System slot adapters that do not support seven REQ#/GNT# signals must provide a mechanism to connect any of the Peripheral Slots 2-8 that may need arbitration service depending on the adapter installed. EPC-100 Hardware Reference C-11...

  • Page 91: Fan Failure Detect Enable Jumper

    To disable the SCSI terminator, apply a jumper. The last module in a SCSI chain must have an active terminator, while all other modules must have the terminator disabled. The EPC-100 is shipped with the jumper removed, enabling the SCSI terminator.
  • Page 92 • Drive initialization failed • Drive recalibration failed • Last track seek failed Video error • Color/Mono switch not set correctly Timer error • System timer (0) failed Diskette error • Floppy type does not match setup EPC-100 Hardware Reference...
  • Page 93 Keyboard interrupts failed • RTC error • RTC lost power • CMOS error • RTC battery failed • CMOS checksum failed Configuration error • Previous POST execution was incomplete • User BIOS Extension Region X exceeds DFFFFh EPC-100 Hardware Reference...

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