Summary of Contents for VXI VM4016
- Page 1 VM4016 NALOG OMPARATOR ’ ANUAL P/N: 82-0022-000 Rev. September 5, 2008 VXI Technology, Inc. 2031 Main Street Irvine, CA 92614-6509 (949) 955-1894...
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Page 3: Table Of Contents
Terms and Symbols...7 Warnings...7 Support Resources ...9 1...11 ECTION Introduction...11 Introduction...11 Description...12 VM4016 General Specifications...14 2...15 ECTION Preparation for Use ...15 Installation ...15 Calculating System Power and Cooling Requirements...15 Setting the Chassis Backplane Jumpers ...16 Setting the Logical Address ...16 Front Panel Interface Wiring ...16... - Page 4 OUTPut:POLarity:EXTernal:INTerrupt ...78 OUTPut:POLarity:EXTernal:LATChed ...79 Required SCPI Commands ...80 STATus:OPERation:CONDition? ...80 STATus:OPERation:ENABle...81 STATus:OPERation[:EVENt]? ...82 STATus:PRESet ...83 STATus:QUEStionable:CONDition? ...84 STATus:QUEStionable:ENABle...85 STATus:QUEStionable[:EVENt] ...86 SYSTem:ERRor? ...87 SYSTem:VERSion?...88 5...89 ECTION Theory of Operation ...89 Introduction...89 Input Range Control...90 Signal Comparison...92 Interrupt Generation...93 ...95 NDEX VM4016 Preface...
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Page 5: Certification
EGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subdivision (b)(3)(ii) of the Rights in Technical Data and Computer Software clause in DFARS 252.227-7013. VM4016 Preface VXI Technology, Inc. 2031 Main Street Irvine, CA 92614-6509 U.S.A. -
Page 6: Declaration Of Conformity
Analog Comparator VM4016 EN61010 (2001) EN61326 (1997 w/A1:98) Class A CISPR 22 (1997) Class A ICES-003 Class A (ANSI C63.4 1992) AS/NZS 3548 (w/A1 & A2:97) Class A FCC Part 15 Subpart B Class A Steve Mauga, QA Manager VM4016 Preface... -
Page 7: General Safety Instructions
ARNINGS Follow these precautions to avoid injury or damage to the product: Use Proper Power Cord Use Proper Power Source VM4016 Preface AFETY NSTRUCTIONS Indicates that a procedure or condition may cause bodily injury or death. Indicates that a procedure or condition could possibly cause damage to equipment or loss of data. - Page 8 Product should be inspected or serviced only by qualified personnel. The operator of this instrument is advised that if equipment is used in a manner not specified in this manual, the protection provided by this equipment be may be impaired. VM4016 Preface...
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Page 9: Support Resources
Lake Stevens Instrument Division VXI Technology, Inc. 1924 - 203 Bickford Snohomish, WA 98290 Phone: (425) 212-2285 Fax: (425) 212-2289 Technical Support Phone: (949) 955-1894 Fax: (949) 955-3041 E-mail: support@vxitech.com http://www.vxitech.com for worldwide support sites and service plan information. Visit VM4016 Preface... - Page 10 VXI Technology, Inc. VM4016 Preface...
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Page 11: Section 1
VMIP family to form a customized and highly integrated instrument (see Figure 1-1). This allows the user to reduce system size and cost by combining the VM4016 with two other instrument functions in a single-wide C-size VXIbus module. Figure 1-2 shows the 48-channel version of the VM4016. -
Page 12: Description
VXIbus registers as can the First Latched register. This information may also be retrieved using the message-based word serial ACC/ FAIL interface. The block diagram of Figure 1-3 shows the overall functionality of the VM4016 Analog Comparator instrument. J202 1-2: F IGURE... - Page 13 VM4016 Introduction DEBOUNCE 10 uS TO 0.5 S INVERT MASK REGISTER REGISTER FIRST LIMIT INVERT REGISTER INTERRUPT INVERT REGISTER 1-3: VM4016 B IGURE LOCK IAGRAM TO VXIBUS COMPARE REGISTERS INTERRUPT VXIbus AND FIRST INTERRUPT LIMIT LOGIC FIRST LIMIT TO VXIBUS...
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Page 14: Vm4016 General Specifications
VM4016 G ENERAL PECIFICATIONS HANNELS VM4016-1 VM4016-2 VM4016-3 NPUT ANGE ±10.0 V, ±100 V NPUT HRESHOLD ESOLUTION 78 mV ±10.0 V 780 mV ±100.0 V NPUT HRESHOLD CCURACY ±3% NPUT Differential, may be configured for single-ended by grounding the negative input... -
Page 15: Section 2
All components should be immediately inspected for damage upon receipt of the unit. Once the VM4016 is assessed to be in good condition, it may be installed into an appropriate C-size or D-size VXIbus chassis in any slot other than slot 0. The chassis should be checked to ensure that it is capable of providing adequate power and cooling for the VM4016. -
Page 16: Setting The Chassis Backplane Jumpers
OGICAL DDRESS The logical address of the VM4016 is set by a single 8-position DIP switch located near the module’s backplane connectors (this is the only switch on the module). The switch is labeled with positions 1 through 8 and with an ON position. A switch pushed toward the ON legend will signify a logic 1;... - Page 17 The connector used in the VM4016 is a commonly available 44-pin high density D-sub receptacle connector. A mating solder cup pin connector from AMP is included, crimp type connectors are available from a variety of sources. SIGNAL CHANNEL 1 +...
- Page 18 VXI Technology, Inc. VM4016 Preparation for Use...
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Page 19: Section 3
(masked and inverted) state of the inputs. It is important to note that this information is also available at the VXIbus register level at offset 0x28. FETCh:CONDitioned? EXAMPLES FETCh:CONDitioned? VM4016 Programming ECTION No query parameters. Returns the state of the conditioned 0 (masked and inverted) inputs. -
Page 20: Fetch:latched
VXIbus register level at offset 0x30. FETch:LATChed? EXAMPLES FETCh:LATChed? FETC:LATC? No query parameters Returns the active signals in the First Latched register. Channel 1. Returns the active signals in the First Latched Register. Channels 1 and 2. VM4016 Programming... -
Page 21: Fetch:raw
(unmasked and non-inverted) state of the inputs. It is important to note that the above information is also available at the register level at offset 0x20. FETCH:RAW? EXAMPLES FETch:RAW? FETC:RAW? 65535 VM4016 Programming No query parameters Returns the state of the unconditioned (unmasked non-inverted) Channel 1. All 16 channels crossed the programmed threshold. -
Page 22: Inhouse:pseudo
Where <boolean> is 0 | OFF | 1 | ON. Sets the pseudo register interface ON. (The unit must be powered for the change to take effect.) Returns 1 which states that the register interface is set to pseudo. VM4016 Programming... -
Page 23: Inhouse:regint
EXAMPLES INHOUSE:REGINT 1 INHOUSE:REGINT? INHOUSE:REGINT 0 INHOUSE:REGENT? VM4016 Programming Where <boolean> is 0 | OFF | 1 | ON. Sets the type of module interrupt response to one backplane interrupts for every first latched event. Returns the type of module interrupt response as 1. -
Page 24: Inhouse:reg_Enable
Where <boolean> is 0 | OFF | 1 | ON. Enables the REGINT type interrupt generation Returns 1 to state that backplane interrupting is currently enabled. Disabling REGINT interrupt generation. Returns 0 to state that backplane interrupting is currently disabled. VM4016 Programming... -
Page 25: Inhouse:clear_Latch
EXAMPLES INHOUSE:CLEAR_LATCH 1 INHOUSE:CLEAR_LATCH? FETC:LATC? FETC:LATC? VM4016 Programming Where <boolean> is 0 | OFF | 1 | ON. Clears the first latched information on a read. Returns 1 stating that the first latched information will be cleared on a read. -
Page 26: Input:debounce
0.0000096 s. This will not allow a signal to generate an interrupt unless the input signal crosses the signal for more than 9.6 e-6 seconds. Setting input debounce time to 0.6 s. Returns the input debounce time as 0.6 s. VM4016 Programming... -
Page 27: Input:mask
INPut:MASK <state>, <channel_list> EXAMPLES INPut:MASK ON,(@1:8) INPut:MASK? 3 INP:MASK? 9 VM4016 Programming Where <state> is 0 | OFF | 1 | ON. Where <channel_list> is standard channel list format supporting channels 1 through Enables channels 1 through 8 to generate interrupts. -
Page 28: Input:mask:interrupt
MASK values are changed. When set to 1, interrupts are generated even as MASK values are changed. INPut:MASK:INTerrupt <boolean> EXAMPLES INPut:MASK:INT 0 INPut:MASK:INT? Where <boolean> is 0 | OFF | 1 | ON. Disables interrupt generation Reports that interrupt generation is disabled VM4016 Programming... -
Page 29: Input:offset
EXAMPLES INPut:RANGe 100,(@5:10) INPut:OFFSet -5.0,(@5:10) INP:OFFS? 9 -5.000 INP:RANG 10,(@1:4) INP:OFFS -5.0,(@1:4) INP:OFFS? 3 -5.000 VM4016 Programming Range Entered Threshold ±10.0 ±100.0 Where -10.00 V to +9.96 V. Where <channel_list> is the standard channel list format supporting Channels 1 through 16. -
Page 30: Input:polarity
5 to NORMal. This will generate an interrupt when the input signal on Channels 3, 4, or 5 is greater than the input offset. Returns the input polarity for Channel 5 as NORMal Sets input polarity for Channel 6 to invert. VM4016 Programming... -
Page 31: Input:range
EXAMPLES INPut:RANGe 100,(@1:16) INPut:RANGe? 7 INP:RANG 10,(@4:6) INP:RANG? 5 VM4016 Programming Where <range> is 10 V | 100 V. Where <channel_list> is the standard channel list format supporting channels 1 through 16. Sets the input range for Channels 1 through 16 to 100 V. -
Page 32: Output:polarity:external:interrupt
Sets the external interrupt output polarity to a low pulse (NORMal), when an interrupt occurs. Returns the external interrupt output polarity as NORMal. Sets the external interrupt output polarity to INVert. Returns the polarity of the external interrupt output as INVert. VM4016 Programming... -
Page 33: Output:polarity:external:latched
When set to invert, the output will be high when there is an interrupt event. OUTPut:POLarity:EXTernal:LATChed <polarity> EXAMPLES OUTPut:POLarity:EXTernal:LATChed NORM OUTPut:POLarity:EXTernal:LATChed? NORM OUTP:POL:EXT:LATC INV OUTP:POL:EXT:LATC? VM4016 Programming Where <polarity> either NORMal or INVerted. Sets the external latched output polarity to low when an interrupt occurs. -
Page 34: Application Examples
The code is functional and will contain a brief description about the operation. Example 1 In this example, the VM4016 sets the output interrupt polarity on the front panel and the debounce time period for the digital debounce circuitry. -
Page 35: Single Channel Operation
INP:POL NORM,(@1) INP:OFFS +3.5,(@1) OUTP:POL:EXT:LATC INV Table 3-1 and the explanation that follows illustrates what is occurring during this example. VM4016 Programming DESCRIPTION Selects ±100 V as the input range for Channel 1. Sets the debounce time limit to 250 ms. - Page 36 K9 selecting a gain of 0.1 for the differential amplifier U17A. 10pf U17A BUFCH1 D A C TRIGLEV1 RELAY DRIVER TO RELAY K9 3-1: S IGURE INGLE HANNEL PERATION 4.7K 4.7K U13A 470K COMPCH1 LATIRQOUT TO FRONT PANEL CONNECTOR 4.7K VM4016 Programming...
- Page 37 INV to cause U3 to output an active low EXTLATIRQ signal to the front panel connector when an interrupt occurs. Now that the VM4016 is configured, it can be determined how this works. The output of the differential amplifier U17A (BUFCH1) is voltage divided by 4. Since the gain of U17A is 0.1, this makes BUFCH1 0.875 V when -CH1 reaches +35.0 V.
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Page 38: Bracketing A Voltage
Channel 2 is less than the offset voltage. Selects +5.25 Vas the offset (reference) voltage for Channel 1. Selects +4.75 V as the offset (reference) voltage for Channel 2. Sets the external interrupt output to be active high. VM4016 Programming... - Page 39 (U4) buffers and routed to the control FPGA (U3). The register for the debounce circuitry is contained internally in the control FPGA. The register will be loaded with a value that corresponds to a 750 μs time delay. VM4016 Programming 100K 10pf...
- Page 40 500 ns. This pulse drives the base of Q33 low causing Q33 to shut off and the pull-up resistor provides a high on the front panel connector signal EXTIRQ. When an interrupt condition is detected by U3 a VXI IRQ* is generated to the VMIP bus. VM4016 Programming...
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Page 41: Register Access Examples
EGISTER CCESS VM4016 Programming XAMPLES 3-1: R ABLE EGISTER Interrupt enable (write only, pseudo only) First latched (read only) Conditioned (read only) Raw (read only) - Page 42 The VM4016 module supports direct register access for very high-speed data retrieval. The register map is as specified in Table 3-1. In order to access the raw data using register access, the register at offset 0x20 must be read. Each bit in this register corresponds to the state of the 16 channel inputs (unmasked and non-inverted).
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Page 43: Pseudo Register Access
EGISTER CCESS The VM4016 can be operated upon using (a) Word Serial Commands or (b) Register Access. The VM4016 allows two types of register accesses (a) Direct Register Access using Hardware registers (b) Pseudo Register Access. This can be configured using the INHOUSE:PSEUDO command. -
Page 44: Vxiplug&Play Driver Examples
- This parameter specifies the number of channels in the channel list. Valid Range: vtvm4016_MIN_CHANNEL_NO (1) to vtvm4016_MAX_CHANNEL_NO (16) ViReal32 offset[], - This parameter specifies the offset voltage to be configured for the input channels. Valid Range: vtvm4016_MIN_VOLTAGE_LEVEL (-10.00 V) to vtvm4016_MAX_VOLTAGE_LEVEL (9.96 V) RIVER XAMPLES VM4016 Programming... - Page 45 - This parameter specifies the polarity to be configured for the specified channels. Valid Range: vtvm4016_INVERTED_POLARITY (0) or vtvm4016_NORMAL_POLARITY ViInt16 voltage_range[] - This parameter specifies the voltage range to be configured for the specified channels. Valid Range: vtvm4016_10VOLTS_RANGE vtvm4016_100VOLTS_RANGE (1) VM4016 Programming (0) or...
- Page 46 ***************************************************************************/ ViStatus_VI_FUNC vtvm4016_setup_and_read_data(ViSession instr_hndl, ViInt16 offset[],ViInt16 polarity[],ViInt16 voltage_range[], ViPInt16 first_latched_reg,ViPInt16 raw_data, ViPInt16 conditioned_data) /* Variable used to store return status of the function */ ViStatus status = VI_NULL; state of the inputs. channels interrupt channel_list[],ViInt16 generation num_of_channels,ViReal32 VM4016 Programming...
- Page 47 /* Reset to the default state */ status = vtvm4016_reset(instr_hndl); if (status < VI_SUCCESS) return status; /* Function to enable the selected channels to cause interrupt */ status = vtvm4016_enable_disable_channels (instr_hndl, vtvm4016_ENABLE_CHANNEL, channel_list, num_of_channels); if (status < VI_SUCCESS) return vtvm4016_ERROR_MASK_OR_UNMASK_CHANNELS; VM4016 Programming...
- Page 48 /* Function to query the Raw data */ status = vtvm4016_read_data (instr_hndl, vtvm4016_READ_RAW_DATA, raw_data); if (status < VI_SUCCESS) return vtvm4016_ERROR_READING_RAW_DATA; /* Function to query the Conditioned data */ status = vtvm4016_read_data (instr_hndl, vtvm4016_READ_CONDITIONED_DATA, conditioned_data); if (status < VI_SUCCESS) return vtvm4016_ERROR_READING_CONDITIONED_DATA; return VI_SUCCESS; channel_list, VM4016 Programming...
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Page 49: Section 4
OMMAND ISTING The following tables provide an alphabetical listing of each command supported by the VM4016 along with a brief description. If an X is found in the column titled *RST, then the value or setting controlled by this command is possibly changed by the execution of the *RST command. If no X is found, then *RST has no effect. - Page 50 Resets the module to a known state Set the service request enable register Query the Status Byte Register Causes a trigger event to occur Starts and reports a self-test procedure Halts execution and queries *RST RST Value VM4016 Command Dictionary...
- Page 51 INHOUSE:CLEAR_LATCH INPut:DEBounce INPut:MASK INPut:MASK:INTerrupt INPut:OFFSet INPut:POLarity INPut:RANGe OUTPut:POLarity:EXTernal:INTerrupt OUTPut:POLarity:EXTernal:LATChed VM4016 Command Dictionary 4-2: I SCPI C NSTRUMENT PECIFIC Description Reads back the 16-bit value that represents the current conditioned (masked and inverted) output state of the comparators in the group.
- Page 52 Queries the Questionable Status Condition Register Sets the Questionable Status Enable Register. Queries the Questionable Status Event Register Queries the Error Queue Queries which version of the SCPI standard the module complies with *RST *RST Value Clears Queue VM4016 Command Dictionary...
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Page 53: Command Dictionary
Describes in detail what the command does and refers to additional sources. Description Present the proper use of each command and its query (when available). Examples Lists commands that affect the use of this command or commands that are affected by Related Commands this command. VM4016 Command Dictionary... -
Page 54: Common Scpi Commands
This command clears the Status Event Register, Operation Status Register, and the Description Questionable Data/Signal Register. It also clears the OPC flag and clears all queues (except the output queue). Examples Command / Query *CLS Related Commands OMMANDS *CLS Response / Descriptions (Clears all status and event registers) VM4016 Command Dictionary... -
Page 55: Ese
The Event Status Enable query reports the current contents of the Event Status Enable Register. Examples Command / Query *ESE 36 *ESE? *ESR? Related Commands VM4016 Command Dictionary *ESE Response (Description) 36 (Returns the value of the event status enable register) -
Page 56: Esr
The Power On bit is set when the module is first powered on or after it receives a reset via the VXI Control Register. Once the bit is cleared (by executing the *ESR? command) it will remain cleared. Examples Command / Query *ESR? *ESE Related Commands *ESR? Response (Description) VM4016 Command Dictionary... -
Page 57: Idn
0 (zero). Examples Command / Query *IDN Related Commands VM4016 Command Dictionary *IDN? Response (Description) VXI Technology, Inc.,VM4016,0,1.0 (The revision listed here is for reference only; the response will always be the current revision of the... -
Page 58: Opc
Examples Command / Query *OPC *OPC? *WAI Related Commands Response (Description) (Sets the OPC bit in the Event Status Register) 1 (Returns the value of the Event Status Register) VM4016 Command Dictionary... -
Page 59: Rst
The Reset (RST) command resets the module’s hardware and software to a known Description state. See the command index at the beginning of this chapter for the default parameter values used with this command. Examples Command / Query *RST Related Commands VM4016 Command Dictionary *RST Response (Description) (Resets the module) -
Page 60: Sre
Bit 6 – 0 (per IEEE 488.2 section 11.3.2.3) Bit 7 – Operation Status Summary Examples Command / Query *SRE 4 *SRE? Related Commands *SRE Response (Description) (Sets the service request enable register) 4 (Returns the value of the SRE register) VM4016 Command Dictionary... -
Page 61: Stb
Bit 4 – Questionable Status Summary (not used) Bit 5 – Message Available Bit 6 – Master Summary Status Bit 7 – Operation Status Summary Examples Command / Query *STB? Related Commands VM4016 Command Dictionary *STB? Response (Description) 16 (Queries the Status Byte Register) -
Page 62: Trg
Type *TRG Command Syntax Command Parameters *RST Value Query Syntax Query Parameters Query Response The Trigger command causes a trigger event to occur. Description Examples Command / Query *TRG Related Commands *TRG Response (Description) (Triggers an event) VM4016 Command Dictionary... -
Page 63: Tst
*RST Value *TST? Query Syntax Query Parameters Numeric ASCII value from 0 to 143 Query Response The Self-Test query causes the VM4016 to run its self-test procedures and report on Description the results. Examples Command / Query *TST Related Commands... -
Page 64: Wai
It provides a way of synchronizing the module with its commander. Examples Command / Query *WAI *OPC Related Commands *WAI Response (Description) (Pauses the execution of additional commands until the No Operation Pending message is true.) VM4016 Command Dictionary... -
Page 65: Instrument Specific Scpi Commands
(masked and inverted) state of the inputs. This information is also available at the VXIbus register level at offset 0x28. Examples Command / Query FETC:COND? FETch:RAW? Related Commands VM4016 Command Dictionary SCPI C OMMANDS FETCh:CONDitioned? Response (Description) 0 (Returns the current conditioned state of the inputs) -
Page 66: Fetch:latched
This information is also available at the VXIbus register level at offset 0x30. Examples Command / Query FETC:LATC? INHOUSE:CLEAR_LATCH Related Commands FETCh:LATChed? Response (Description) 1 (Returns the active signal in the First Latched register.) VM4016 Command Dictionary... -
Page 67: Fetch:raw
(unmasked and non-inverted) state of the inputs. This information is also available at the register level at offset 0x20. Examples Command / Query FETC:RAW? FETch:CONDitioned? Related Commands VM4016 Command Dictionary FETCh:RAW? Response (Description) 1 (Returns the current unconditioned state of the inputs) -
Page 68: Inhouse:clear_Latch
When the information is cleared, all following reads will return a value of 0 until a new first latched event occurs. Note: All letters of the command are required; there is no short form of the command. Examples Command / Query INHOUSE:CLEAR_LATCH 1 INHOUSE:CLEAR_LATCH? INHOUSE:PSEUDO Related Commands FETCh:LATChed? INHOUSE:CLEAR_LATCH Response (Description) VM4016 Command Dictionary... -
Page 69: Inhouse:pseudo
Note: All letters of the command are required; there is no short form of the command. Examples Command / Query INHOUSE:PSEUDO 1 INHOUSE:PSEUDO? INHOUSE:REG_ENABLE Related Commands INHOUSE:CLEAR_LATCH VM4016 Command Dictionary INHOUSE:PSEUDO Factory Default = 1 Response (Description) (Selects the PSEUDO register) 1 (Indicates that the PSEUDO register is selected) -
Page 70: Inhouse:regint
Note: All letters of the command are required; there is no short form of the command. Examples Command / Query INHOUSE:REGINT 1 INHOUSE:REGINT? INHOUSE:REG_ENABLE Related Commands INHOUSE:PSEUDO INHOUSE:REGINT Response (Description) (Sets REGINT to true) 1 (Indicates that REGINT is set to true) VM4016 Command Dictionary... -
Page 71: Inhouse:reg_Enable
Note: All letters of the command are required; there is no short form of the command. Examples Command / Query INHOUSE:REG_ENABLE 1 INHOUSE:REG_ENABLE? INHOUSE:PSEUDO Related Commands INHOUSE:REGINT VM4016 Command Dictionary INHOUSE:REG_ENABLE Response (Description) -
Page 72: Input:debounce
9.6 μs. The debounce time set is applied to all channels. Examples Command / Query INP:DEB 9.6e-6 INP:DEB None Related Commands INPut:DEBounce Response (Description) (Sets a digital debounce time of 9.6 μs) 0.0000096 (Indicates that the debounce time is set to 9.6 μs) VM4016 Command Dictionary... -
Page 73: Input:mask
VXIbus interrupts. Examples Command / Query INP:MASK 0,(@1:8) INP:MASK? 3 None Related Commands VM4016 Command Dictionary INPut:MASK Response (Description) (Makes Channels 1 – 8 incapable of generating VXIbus interrupts) 0 (Indicates that Channel 3 is incapable of generating VXIbus interrupts.) -
Page 74: Input:mask:interrupt
INPut:DEBounce time, another interrupt will be generated. Examples Command / Query INP:MASK:INT 1 INP:MASK:INT? All INPut commands Related Commands INPut:MASK:INTerrupt Response (Description) (Enables interrupt generation while changing mask values) 1 (Indicates that Input Mask Interrupt is enabled) VM4016 Command Dictionary... -
Page 75: Input:offset
INP:OFFS 2.5,(@9:16) INP:OFFS? 11 INP:RANG 10,(@1:8) INP:OFFS 2.5,(@1:8) INP:OFFS? 5 INPut:RANGe <range>,<channel_list> Related Commands INPut:POLarity <polarity>,<channel_list> VM4016 Command Dictionary INPut:OFFSet Range Entered Threshold ±10.0 ±100.0 Response (Description) (Selects an input range of ±100 V for Channels 9 - (Selects an input threshold of 25 V for Channels 9 - 16) 2.500 (Returns the set input threshold for Channel... -
Page 76: Input:polarity
Examples Command / Query INP:POL INV,(@5:12) INP:POL? 6 INPut:OFFset Related Commands INPut:RANGe INPut:POLarity Response (Description) (Inverts the input polarity for Channels 5 - 12) INV (Indicates the polarity for Channel 6 is inverted) VM4016 Command Dictionary... -
Page 77: Input:range
Command / Query INP:RANG 100,(@1,3,5,7) INP:RANG? 7 INPut:OFFset <voltage_level>, <channel_list> Related Commands VM4016 Command Dictionary INPut:RANGe Response (Description) (Sets the input range for Channels 1, 3, 5, and 7 to 100 V) 100 (Returns the set input range for Channel 7) -
Page 78: Output:polarity:external:interrupt
When set for invert, the output will be low when there is an interrupt event. Examples Command / Query OUTP:POL:EXT:INT NORM OUTP:POL:EXT:INT? None Related Commands Response (Description) (Sets the front panel interrupt output polarity to normal) NORM (Returns the set value for the front panel interrupt output polarity) VM4016 Command Dictionary... -
Page 79: Output:polarity:external:latched
Examples Command / Query OUTP:POL:EXT:LATC INV OUTP:POL:EXT:LATC? None Related Commands VM4016 Command Dictionary Response (Description) (Sets the polarity of the front panel latched interrupt output to inverted) INV (Returns the value for the front panel latched interrupt output) -
Page 80: Required Scpi Commands
Query Parameters Query Response The Operation Status Condition Register query is provided for SCPI compliance only. Description The VM4016 does not alter the state of any of the bits in this register and always reports a 0. Examples Command / Query... -
Page 81: Status:operation:enable
Query Response The Operation Status Enable Register is included for SCPI compatibility and the Description VM4016 does not alter any of the bits in this register. The register layout is as follows: Bit 0 - Calibrating Bit 1 - Setting... -
Page 82: Status:operation[:Event]
None Query Parameters Query Response The Status Operation Event Register query is included for SCPI compliance. The Description VM4016 does not alter any of the bits in this register and always reports a 0. Examples Command / Query STAT:OPER? None... -
Page 83: Status:preset
Enable Register is set to 0 and the Questionable Status Enable Register is set to 0. This command is provided for SCPI compliance only. Examples Command / Query STAT:PRES None Related Commands VM4016 Command Dictionary STATus:PRESet Response (Description) (Presets the Status Registers) -
Page 84: Status:questionable:condition
Query Parameters Query Response The Questionable Status Condition Register query is provided for SCPI compliance Description only. The VM4016 does not alter any of the bits in this register and a query always reports a 0. Examples Command / Query... -
Page 85: Status:questionable:enable
Enable Register. This command is provided only to comply with the SCPI standard. The Status Questionable Enable query reports the contents of the Questionable Status Enable Register. The VM4016 does not alter the bit settings of this register and will report the last programmed value. -
Page 86: Status:questionable[:Event]
None Query Parameters Query Response The Questionable Status Event Register is provided for SCPI compliance only. The Description VM4016 does not alter the bits in this register and queries always report a 0. Examples Command / Query STAT:QUES? None Related Commands... -
Page 87: System:error
Volume 2: Command Reference for details on errors and reporting them. Refer to the “Error Messages” section of this manual for specific details regarding the reported errors. Examples Command / Query SYST:ERR? None Related Commands VM4016 Command Dictionary SYSTem:ERRor? Response (Description) -350, “Queue overflow”... -
Page 88: System:version
Command Parameters *RST Value SYSTem:VERSion? Query Syntax None Query Parameters Numeric ASCII value Query Response The System Version query reports version of the SCPI standard to which the VM4016 Description complies. Examples Command / Query SYST:VERS? None Related Commands SYSTem:VERSion? Response (Description) 1994.0... -
Page 89: Section 5
VXIbus registers, as can the First Latched register. This information may also be retrieved using the message-based word serial interface. All channels on the VM4016 are identical in functionality, therefore, descriptions in this theory of operation will pertain to Channel 1 (CH1) only. -
Page 90: Input Range Control
± 100 V. When the K9 relay is de-energized it will default to a 100 kΩ resistor that provides a gain of 1 thereby allowing ±10 V input voltage range. VM4016 Theory of Operation... - Page 91 FROM FRONT PANEL CONNECTORS VMIP BUS COM M AND BUFFER D A T A BUFFER VM4016 Theory of Operation 100K K9:B 10pf 100K -CH1 U17A 100K +CH1 100K K9:C RELAYDATA BA 0-5, 29 RELAYUPDATE RELAYCLK RELAYENA* CONTROL FPGA DATA 5-1: I...
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Page 92: Signal Comparison
DAC 1. The output TRIGLEV1 of the U8, is used by the comparator U13A as the reference. 100K 10pf U17A 100K BUFCH1 DACDATA D A C TRIGLEV1 DACLOAD# DACCLK 5-2: S IGURE IGNAL OMPARISON 4.7K 4.7K U13A 470K COMPCH1 VM4016 Theory of Operation... -
Page 93: Interrupt Generation
TRIGLEV1. The debounce circuitry and the mask register use this signal INV to determine polarity (see Figure 5-3). INV determines whether COMPCH1 is treated as an active low for normal and active high for an inverted signal. VM4016 Theory of Operation... - Page 94 VXI Technology, Inc. 5-3: I IGURE NTERRUPT ENERATION VM4016 Theory of Operation...
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Page 95: Index
INPut:MASK:INTerrupt ...28, 51, 74 INPut:OFFSet ...29, 51, 75 INPut:POLarity ...30, 51, 76 INPut:RANGe...31, 51, 77 interrupt generation ...93 interrupts...89 VM4016 Index latched register ... 89 logical address ...15, 16 mask register circuitry ...37, 40 OPC ... 50 OUTPut:POLarity:EXTernal:INTerrupt...32, 51, 78 OUTPut:POLarity:EXTernal:INTerrupt NORM...