ZiLOG Z8F64200100KITG User Manual page 16

5
L1
VCC_33V AVDD
1 3
VCC_33V IO IO
D
EMI Filter
GND AGND
GND
PA0_T0IN
RESET
-RESET
SW2
C15 C16
0.001uF
JP13
0.1uF
PF7
1
C
Header 1
JP14
PF6
1
C19 C20
0.001uF
Header 1
0.1uF
JP6
PF5
1
Header 1
JP7 R12
PF4 220
1
Y1
Header 1
JP8
PF3
18.432MHz
1
Header 1 R13 100K
JP9 C23
PF2 18pF
B
1
Header 1
JP10
PF1
1
Header 1
PH0_ANA8 PH1_ANA9 PB0_ANA0 PB1_ANA1
C26 C27 C28 C29
0.001uF 0.001uF 0.001uF 0.001uF
A
5
Schematics
4
PA2
PA1_T0OUT
C11 C12
0.001uF
0.1uF
U6
PA0_T0IN
1
PA0/T0IN PA7/SDA
PD2
2
PD2 PD6/CTS1
PC2_SS
3
PC2/SS PC3/SCK
PF6
4
PF6 PD7/RCOUT
5
RESET PG0
VCC_33V
6
VDD GND
PF5
7
PF5 PG1
PF4
8
PF4 PG2
PF3
9
PF3 PE5
PE4
10
PE4 PE6
PE3
11
PE3 PE7
GND
12
GND VDD
PE2
13
PE2 PG3
PE1
14
PE1 PG4
PE0
15
PE0 PG5
GND
16
GND PG6
PF2
17
PF2 VDD
PF1
18
PF1 PG7
PF0
19
PF0 PC7/T2OUT
VCC_33V
20
VDD PC6/T2IN
PD1_T3OUT
21
PD1/T3OUT DBG
PD0_T3IN
22
PD0/T3IN PC1/T1OUT
XOUT
23
XOUT PC0/T1IN
XIN
24
XIN GND
Z8F642
18pF
C24
PB4_ANA4 PB5_ANA5 PB6_ANA6 PB7_ANA7 PB3_ANA3 PB2_ANA2
C30 C31 C32 C33 C34
0.001uF 0.001uF 0.001uF 0.001uF 0.001uF
J2
PH0_ANA8
25 26
PH1_ANA9
23 24
PB0_ANA0
21 22
PB1_ANA1
19 20
PB4_ANA4
17 18
PB5_ANA5
15 16
PB6_ANA6
13 14
PB7_ANA7
11 12
PB3_ANA3
9 10
PB2_ANA2
7 8
PH2_ANA10
5 6
PH3_ANA11
3 4
VREF
1 2
4
Figure 4. Z8 Encore! XP F64XX Series Development Board (Continued)
Z8 Encore! XP
3 2
C13 C14
0.001uF
0.1uF
DBG
DBG
PA5_TXD0
PA5_TXD0
PA3_CTS0
PA3_CTS0
PA4_RXD0
PA4_RXD0
PA7_SDA
64
PD6_CTS1 PG1
63
PC3_SCK
62
PD7_RCOUT
61
PG0
Header 1
60
GND
59
PG1 PG2
58
PG2
57
PE5 C17 C18
56
PE6 0.1uF 0.001uF Header 1
55
PE7
54
VCC_33V PG3
53
PG3
52
PG4
51
PG5 Header 1
50
PG6
49
VCC_33V PG4
48
PG7
47
PC7_T2OUT
46
PC6_T2IN
C21 C22 Header 1
45
DBG 0.1uF 0.001uF
44
PC1_T1OUT PG5
43
PC0_T1IN
42
GND
41
Header 1
PC0_T1IN
PG6
Header 1
PG7
Header 1
connector 1
for
reference
only
PH2_ANA10 PH3_ANA11
+ C25
C35 C36 C37 22uF C38
0.001uF 0.001uF 0.001uF 0.01uF
AGND
3 2
®
F64XX Series Development Kit
User Manual
1
connector 2
JP2
PE7 PE6
1 2
PE5 PE4
3 4
PE3 PE2
5 6
PE1 PE0
7 8
VCC_33V GND
9 10
PC4_MOSI PC5_MISO
11 12
PC7_T2OUT PC6_T2IN
13 14
PC3_SCK PC2_SS
15 16
PC0_T1IN PA0_T0IN
17 18
GND PA1_T0OUT
19 20
PC1_T1OUT PA2
21 22
PD1_T3OUT PD6_CTS1
23 24
PD3 PD4_RXD1
25 26
PD5_TXD1 PD0_T3IN
27 28
PD7_RCOUT GND
29 30
PF0 PD2
31 32
PA3_CTS0 PG0
33 34
PA4_RXD0 PA5_TXD0
35 36
JP15 37 38
NC NC
GND
39 40
1 NC
41 42
NC NC
43 44
NC NC
PA6_SCL
45 46
PA7_SDA GND
JP16
47 48
49 50
NC
1 -DIS_232
-DIS_IrDA
51 52
NC -DIS_IRDA
-RESET
53 54
NC
VCC_33V GND
55 56
JP17 57 58
NC NC
VCC_33V
59 60
NC
1
HEADER 30x2/SM
JP18
1
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
JP19
1
JP1
JP20
1
1 2
3 4
-TRSTN
5 6
-F91_WE
JP21 7 8
GND VCC_33V
9 10
1 VCC_33V
A6
11 12 A0
A10
A3
13 14
VCC_33V
GND
15 16
A8
A7
17 18
A13 A9
19 20
A15 A14
21 22
A18 A16
23 24
A19 GND
25 26
A2 A1
27 28
A11
A12
29 30
A4 A20
31 32
A5 A17
33 34
-DIS_FLASH
35 36
A21 VCC_33V
37 38
A22 A23
39 40
-CS0 41 42 -CS1
-CS2 43 44 D0
D1 D2
45 46
D3 D4
47 48
D5 GND
49 50
D7 D6
51 52
-MREQ -IOREQ
53 54
GND -RD
55 56
-WR 57 58 -INSTRD
-BUSACK -BUSREQ
59 60
HEADER 30x2/SM
Title
Encore! F642. Evaluation Module. Schematic.
Size Document Number
B
96C0918-001
Date: Friday, June 06, 2003 Sheet 2 of
1
UM015110-0508
13
D
C
B
A
Rev
A
2