Microchip Technology dsPIC33 Series Reference Manual
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Microchip Technology dsPIC33 Series Reference Manual

Can flexible data-rate (fd) protocol module
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CAN Flexible Data-Rate (FD) Protocol Module
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0 FIFO Behavior................................................................................................................. 92
11.0 Timestamping................................................................................................................ 103
12.0 Interrupts....................................................................................................................... 104
13.0 Error Handling................................................................................................................111
14.0 Related Application Notes............................................................................................. 113
15.0 Revision History ............................................................................................................ 114
 2018 Microchip Technology Inc.
Introduction ....................................................................................................................... 2
CAN FD Message Frames................................................................................................ 5
Control Registers .............................................................................................................. 9
Modes of Operation ........................................................................................................ 51
Configuration................................................................................................................... 57
Message Transmission ................................................................................................... 67
Transmit Event FIFO - TEF ............................................................................................ 76
Message Filtering............................................................................................................ 81
Message Reception ........................................................................................................ 86
DS70005340A-page 1

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Summary of Contents for Microchip Technology dsPIC33 Series

  • Page 1: Table Of Contents

    Transmit Event FIFO – TEF .................... 76 Message Filtering......................81 Message Reception ......................86 10.0 FIFO Behavior......................... 92 11.0 Timestamping........................ 103 12.0 Interrupts........................104 13.0 Error Handling........................111 14.0 Related Application Notes..................... 113 15.0 Revision History ......................114  2018 Microchip Technology Inc. DS70005340A-page 1...

  • Page 2: Introduction

    Message Transmission • Message Transmission Prioritization: - Based on priority bit field and/or - Message with lowest ID gets transmitted first using the TXQ • Programmable Automatic Retransmission Attempts: Unlimited, 3 Attempts or Disabled  2018 Microchip Technology Inc. DS70005340A-page 2...
  • Page 3 • A free-running Time Base Counter (TBC) is used to timestamp received messages. Messages in the TEF can also be timestamped. • The CAN FD controller module generates interrupts when new messages are received or when messages are transmitted successfully.  2018 Microchip Technology Inc. DS70005340A-page 3...
  • Page 4 Object 0 Object 0 Object 0 • • • • • • • • • • • • • • • Message Message Message Message Object 31 Object 31 Object 31 Object 31  2018 Microchip Technology Inc. DS70005340A-page 4...

  • Page 5: Can Fd Message Frames

    20 or more data bytes. Technically, there are a total of six different CAN data/remove frames in the CAN FD. Figure 2-1: General Data Frame DATA FRAME DATA CRC (16/18/22b) ARBITRATION (12/32b) CTRL (6/8/9b) ACK (2b) EOF (7b) (= 3b) (1b) (0 to 64b) CRC (16/22/26b) (= 3b)  2018 Microchip Technology Inc. DS70005340A-page 5...
  • Page 6 CAN FD Ext. DLC<3:0> Figure 2-4: ISO CRC Field CRC (16/22/26b) CAN Base CRC (15b) STUFF CRC (17/21b) CAN FD Base CNT (4b) CAN Ext. CRC (15b) STUFF CAN FD Ext. CNT (4b)  2018 Microchip Technology Inc. DS70005340A-page 6...
  • Page 7 Error and Overload Frame ERROR ANYWHERE WITHIN DATA FRAME ERRFLAG (6b) ERRDEL (8b) IFS (= 3b) or OVL OVERLOAD EOF or ERRDEL or OVLDEL OVLFLAG (6b) OVLDEL (8b) IFS (= 3b) or OVL  2018 Microchip Technology Inc. DS70005340A-page 7...
  • Page 8 The Data Length Code (DLC) specifies the number of data bytes a message frame contains. Table 2-1 illustrates the encoding. Table 2-1: DLC Encoding Frame Number of Data Bytes CAN 2.0 and CAN FD CAN 2.0 9-15 CAN FD  2018 Microchip Technology Inc. DS70005340A-page 8...

  • Page 9: Control Registers

    3-47: C1BDIAG0L • Register 3-48: C1BDIAG1H • Register 3-49: C1BDIAG1L • Register 3-50: C1FLTCONxH • Register 3-51: C1FLTCONxL • Register 3-52: C1FLTOBJxH • Register 3-53: C1FLTOBJxL • Register 3-54: C1MASKxH • Register 3-55: C1MASKxL  2018 Microchip Technology Inc. DS70005340A-page 9...
  • Page 10 TXQEN: Enable Transmit Queue bit 1 = Enables TXQ and reserves space in RAM 0 = Does not reserve space in RAM for TXQ These bits can only be modified in Configuration mode (OPMOD<2:0> = Note 1:  2018 Microchip Technology Inc. DS70005340A-page 10...
  • Page 11 1 = Restricted retransmission attempts, uses TXAT<1:0> (C1FIFOCONxH<6:5>) 0 = Unlimited number of retransmission attempts, TXAT<1:0> bits will be ignored These bits can only be modified in Configuration mode (OPMOD<2:0> = Note 1:  2018 Microchip Technology Inc. DS70005340A-page 11...
  • Page 12 10010 = Compares up to DATA Byte 2, bit 6 with EID17 00001 = Compares up to Data Byte 0, bit 7 with EID0 00000 = Does not compare data bytes These bits can only be modified in Configuration mode (OPMOD<2:0> = Note 1:  2018 Microchip Technology Inc. DS70005340A-page 12...
  • Page 13 SJW<6:0>: Synchronization Jump Width bits 111 1111 = Length is 128 x T 000 0000 = Length is 1 x T These bits can only be modified in Configuration mode (OPMOD<2:0> = Note 1:  2018 Microchip Technology Inc. DS70005340A-page 13...
  • Page 14 SJW<3:0>: Synchronization Jump Width bits 1111 = Length is 16 x T 0000 = Length is 1 x T This register can only be modified in Configuration mode (OPMOD<2:0> = 100). Note 1:  2018 Microchip Technology Inc. DS70005340A-page 14...
  • Page 15 10-11 = Auto: Measures delay and adds TSEG1<4:0> (C1DBTCFGH<4:0>); add TDCO<6:0> 01 = Manual: Does not measure, uses TDCV<5:0> + TDCO<6:0> from register 00 = Disables This register can only be modified in Configuration mode (OPMOD<2:0> = 100). Note 1:  2018 Microchip Technology Inc. DS70005340A-page 15...
  • Page 16 TDCV<5:0>: Transmitter Delay Compensation Value bits (Secondary Sample Point (SSP)) 11 1111 = 63 x T 00 0000 = 0 x T This register can only be modified in Configuration mode (OPMOD<2:0> = 100). Note 1:  2018 Microchip Technology Inc. DS70005340A-page 16...
  • Page 17 This is a free-running timer that increments every TBCPRE<9:0> clock when TBCEN is set. The TBC will be stopped and reset when TBCEN = 0 to save power. Note 1: The TBC prescaler count will be reset on any write to C1TBCH/L (TBCPREx will be unaffected).  2018 Microchip Technology Inc. DS70005340A-page 17...
  • Page 18 = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 TBCPRE<9:0>: CAN Time Base Counter Prescaler bits 1023 = TBC increments every 1024 clocks 0 = TBC increments every 1 clock  2018 Microchip Technology Inc. DS70005340A-page 18...
  • Page 19 1000001-1111111 = Reserved 1000000 = No interrupt 0100000-0111111 = Reserved 0011111 = FIFO 31 interrupt (TFIF<31> is set) 0000001 = FIFO 1 interrupt (TFIF<1> is set) 0000000 = FIFO 0 interrupt (TFIF<0> is set)  2018 Microchip Technology Inc. DS70005340A-page 19...
  • Page 20 1000000 = No interrupt 0100000-0111111 = Reserved 0011111 = FIFO 31 interrupt (TFIF31 or RFIF31 is set) 0000001 = FIFO 1 Interrupt (TFIF1 or RFIF1 is set) 0000000 = FIFO 0 Interrupt (TFIF0 is set)  2018 Microchip Technology Inc. DS70005340A-page 20...
  • Page 21 1 = Receive object interrupt is enabled 0 = Receive object interrupt is disabled bit 0 TXIE: Transmit Object Interrupt Enable bit 1 = Transmit object interrupt is enabled 0 = Transmit object interrupt is disabled  2018 Microchip Technology Inc. DS70005340A-page 21...
  • Page 22 TXIF: Transmit Object Interrupt Flag bit 1 = Transmit object interrupt is pending 0 = No transmit object interrupts are pending C1INTL: Flags are set by hardware and cleared by application. Note 1:  2018 Microchip Technology Inc. DS70005340A-page 22...
  • Page 23 0 = No enabled receive FIFO interrupts are pending bit 0 Unimplemented: Read as ‘0’ C1RXIFL: FIFO: RFIFx = ‘or’ of enabled RX FIFO flags (flags need to be cleared in the FIFO register). Note 1:  2018 Microchip Technology Inc. DS70005340A-page 23...
  • Page 24 RFOVIF<15:1>: Receive FIFO Overflow Interrupt Pending bits 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 Unimplemented: Read as ‘0’ C1RXOVIFL: FIFO: RFOVIFx (flag needs to be cleared in the FIFO register) Note 1:  2018 Microchip Technology Inc. DS70005340A-page 24...
  • Page 25 0 = No enabled transmit FIFO/TXQ interrupts are pending C1TXIFL: FIFO: TFIFx = ‘or’ of the enabled TX FIFO flags (flags need to be cleared in the FIFO register). Note 1: TFIF0 is for the TXQ.  2018 Microchip Technology Inc. DS70005340A-page 25...
  • Page 26 TFATIF<15:0>: Transmit FIFO/TXQ Attempt Interrupt Pending bits 1 = Interrupt is pending 0 = Interrupt is not pending C1TXATIFL: FIFO: TFATIFx (flag needs to be cleared in the FIFO register). Note 1: TFATIF0 is for the TXQ.  2018 Microchip Technology Inc. DS70005340A-page 26...
  • Page 27 Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when the message(s) queued in the object is (are) successfully sent. This bit can NOT be used for aborting a transmission.  2018 Microchip Technology Inc. DS70005340A-page 27...
  • Page 28 ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FIFOBA<15:0>: Message Memory Base Address bits Defines the base address for the transmit event FIFO followed by the message objects.  2018 Microchip Technology Inc. DS70005340A-page 28...
  • Page 29 00 = Disable retransmission attempts bit 4-0 TXPRI<4:0>: Message Transmit Priority bits 11111 = Highest message priority 00000 = Lowest message priority These bits can only be modified in Configuration mode (OPMOD<2:0> = 100). Note 1:  2018 Microchip Technology Inc. DS70005340A-page 29...
  • Page 30 1 = Interrupt is enabled for TXQ not full 0 = Interrupt is disabled for TXQ not full Please refer to the specific device data sheet for the Reset value of the TXEN bit. Note 1:  2018 Microchip Technology Inc. DS70005340A-page 30...
  • Page 31 (FSIZE = 3), TXQCIx will take on a value of 0 to 3, depending on the state of the TXQ. These bits are updated when a message completes (or aborts) or when the TXQ is reset.  2018 Microchip Technology Inc. DS70005340A-page 31...
  • Page 32 00 = DisableS retransmission attempts bit 4-0 TXPRI<4:0>: Message Transmit Priority bits 11111 = Highest message priority 00000 = Lowest message priority Note 1: These bits can only be modified in Configuration mode (OPMOD<2:0> = 100).  2018 Microchip Technology Inc. DS70005340A-page 32...
  • Page 33 RXOVIE: Overflow Interrupt Enable bit 1 = Interrupt is enabled for overflow event 0 = Interrupt is disabled for overflow event Note 1: These bits can only be modified in Configuration mode (OPMOD<2:0> = 100).  2018 Microchip Technology Inc. DS70005340A-page 33...
  • Page 34 Receive FIFO Not Empty Interrupt Enable 1 = Interrupt is enabled for FIFO not empty 0 = Interrupt is disabled for FIFO not empty Note 1: These bits can only be modified in Configuration mode (OPMOD<2:0> = 100).  2018 Microchip Technology Inc. DS70005340A-page 34...
  • Page 35 (FSIZE = 3), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO. This bit is updated when a message completes (or aborts) or when the FIFO is reset. This bit is reset on any read of this register or when the TXQ is reset.  2018 Microchip Technology Inc. DS70005340A-page 35...
  • Page 36 (FSIZE = 3), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO. This bit is updated when a message completes (or aborts) or when the FIFO is reset. This bit is reset on any read of this register or when the TXQ is reset.  2018 Microchip Technology Inc. DS70005340A-page 36...
  • Page 37 00001 = FIFO is 2 messages deep 00000 = FIFO is 1 message deep bit 7-0 Unimplemented: Read as ‘0’ These bits can only be modified in Configuration mode (OPMOD<2:0> = 100). Note 1:  2018 Microchip Technology Inc. DS70005340A-page 37...
  • Page 38 TEFNEIE: Transmit Event FIFO Not Empty Interrupt Enable bit 1 = Interrupt is enabled for FIFO not empty 0 = Interrupt is disabled for FIFO not empty These bits can only be modified in Configuration mode (OPMOD<2:0> = 100). Note 1:  2018 Microchip Technology Inc. DS70005340A-page 38...
  • Page 39 TEFNEIF: Transmit Event FIFO Not Empty Interrupt Flag bit 1 = FIFO is not empty 0 = FIFO is empty These bits are read-only and reflect the status of the FIFO. Note 1:  2018 Microchip Technology Inc. DS70005340A-page 39...
  • Page 40 A read of this register will return the address where the next message is to be read (FIFO tail). This register is not ensured to read correctly in Configuration mode and should only be accessed when the Note 1: module is not in Configuration mode.  2018 Microchip Technology Inc. DS70005340A-page 40...
  • Page 41 A read of this register will return the address where the next event is to be read (FIFO tail). This register is not ensured to read correctly in Configuration mode and should only be accessed when the Note 1: module is not in Configuration mode.  2018 Microchip Technology Inc. DS70005340A-page 41...
  • Page 42 A read of this register will return the address where the next message is to be written (TXQ head). This register is not ensured to read correctly in Configuration mode and should only be accessed when the Note 1: module is not in Configuration mode.  2018 Microchip Technology Inc. DS70005340A-page 42...
  • Page 43 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 TERRCNT<7:0>: Transmit Error Counter bits bit 7-0 RERRCNT<7:0>: Receive Error Counter bits  2018 Microchip Technology Inc. DS70005340A-page 43...
  • Page 44 ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 NTERRCNT<7:0>: Nominal Bit Rate Transmit Error Counter bits bit 7-0 NRERRCNT<7:0>: Nominal Bit Rate Receive Error Counter bits  2018 Microchip Technology Inc. DS70005340A-page 44...
  • Page 45 During bus off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the bus off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).  2018 Microchip Technology Inc. DS70005340A-page 45...
  • Page 46 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EFMSGCNT<15:0>: Error-Free Message Counter bits  2018 Microchip Technology Inc. DS70005340A-page 46...
  • Page 47 00010 = Message matching filter is stored in Object 2 00001 = Message matching filter is stored in Object 1 00000 = Reserved; Object 0 is the TX Queue and cannot receive messages  2018 Microchip Technology Inc. DS70005340A-page 47...
  • Page 48 00010 = Message matching filter is stored in Object 2 00001 = Message matching filter is stored in Object 1 00000 = Reserved; Object 0 is the TX Queue and cannot receive messages  2018 Microchip Technology Inc. DS70005340A-page 48...
  • Page 49 = Bit is unknown bit 15-11 EID<4:0>: Extended Identifier Filter bits In DeviceNet™ mode, these are the filter bits for the first 2 data bytes. bit 10-0 SID<10:0>: Standard Identifier Filter bits  2018 Microchip Technology Inc. DS70005340A-page 49...
  • Page 50 = Bit is unknown bit 15-11 MEID<4:0>: Extended Identifier Mask bits In DeviceNet™ mode, these are the mask bits for the first 2 data bytes. bit 10-0 MSID<10:0>: Standard Identifier Mask bits  2018 Microchip Technology Inc. DS70005340A-page 50...

  • Page 51: Modes Of Operation

    (eleven consecutive recessive bits), under the following conditions: • Change from Configuration mode to one of the Normal modes or Debug modes • Change from Disable mode to one of the Normal modes  2018 Microchip Technology Inc. DS70005340A-page 51...
  • Page 52 Clear All TXREQx Restricted Operation bits (Reset TX Mode FIFOs/TXQ) TX: Only ACK, TXREQx Ignored “Normal” Modes “Debug” Modes External/Internal Normal FD Loopback Mode Mode Normal 2.0 Listen Only Mode Mode Restricted Operation Mode  2018 Microchip Technology Inc. DS70005340A-page 52...
  • Page 53 CAN FD frames. It might send error frames if CAN FD frames are detected on the bus. The FDF, BRS and ESI bits in the TX objects will be ignored and transmitted as ‘0’.  2018 Microchip Technology Inc. DS70005340A-page 53...
  • Page 54 The transmit signal is internally connected to receive and the CxTX pin is driven high. 4.5.3.2 External Loopback Mode The transmit signal is internally connected to receive and transmit messages can be monitored on the CxTX pin.  2018 Microchip Technology Inc. DS70005340A-page 54...
  • Page 55 WAKE-UP FROM SLEEP Figure 4-2 depicts how the CAN module will execute the SLEEP instruction and how the module wakes up on bus activity. Upon a wake-up from Sleep mode, the WAKIF flag is set.  2018 Microchip Technology Inc. DS70005340A-page 55...
  • Page 56 Disable, Sleep or Idle mode. This feature can be used to protect the module from wake-up due to short glitches on the CAN bus lines. The WAKFIL bit (C1CONL<8>) enables or disables the filter while the module is in Sleep.  2018 Microchip Technology Inc. DS70005340A-page 56...

  • Page 57: Configuration

    640 MHz will result in unpredictable behavior. The CANCLKDIVx divider value must not be changed during CAN module operation. The user must ensure the maximum clock output frequency of the divider is 80 MHz or less.  2018 Microchip Technology Inc. DS70005340A-page 57...
  • Page 58 Setting the TXQEN bit will reserve RAM for the TXQ. If the TXQEN bit is cleared, then the TXQ cannot be used. Setting the STEF bit will reserve RAM for the TEF and all transmitted messages will be stored in the TEF.  2018 Microchip Technology Inc. DS70005340A-page 58...
  • Page 59 Phase Segment 1 (PHSEG1) – Compensates for errors that may occur due to phase shifts in the edges. The time segment may be automatically lengthened during resynchronization to compensate for the phase shift.  2018 Microchip Technology Inc. DS70005340A-page 59...
  • Page 60 Table 5-1: Nominal Bit Rate Configuration Ranges Segment Min. Max. NSYNC NTSEG1 NTSEG2 NSJW NTQ per Bit Table 5-2: Data Bit Rate Configuration Ranges Segment Min. Max. DSYNC DTSEG1 DTSEG2 DSJW DTQ per Bit  2018 Microchip Technology Inc. DS70005340A-page 60...
  • Page 61 Transceiver Propagation Delay (t Delay (t TXD – RXD TXD – RXD Delay (t Delay (t TXD-RXD TXD-RXD Delay: Node B to A (T PROPBA    PROP PROPAB PROPBA TXD RXD –  2018 Microchip Technology Inc. DS70005340A-page 61...
  • Page 62 SYNC segment. The bit time counter is restarted with SYNC. • Resynchronization – If the edge falls outside the SYNC segment, PHSEG1 or PHSEG2 will be adjusted. For a more detailed description of the CAN synchronization, please refer to ISO11898-1:2015.  2018 Microchip Technology Inc. DS70005340A-page 62...
  • Page 63 --------------- - 1 –     DBRP  ------------------------------------------------------------------------------------------------------------------------------------------------------------------ -     NBRP      ----------- - HNSEGP2 --------------- - DPHSEG2 ----------- -     DBRP  2018 Microchip Technology Inc. DS70005340A-page 63...
  • Page 64 Equation 5-11 through Equation 5-16. Conditions 1-5 Table 5-5: Bit Time Register Initialization (500k/2M) C1NBTCFGH/L Value C1DBTCFGH/L Value C1TDCH/L Value BRP<7:0> BRP<7:0> TDCMOD<1:0> TSEG1<7:0> TSEG1<4:0> TDCO<6:0> TSEG2<6:0> TSEG2<3:0> TDCV<5:0> SJW<6:0> SJW<3:0> — —  2018 Microchip Technology Inc. DS70005340A-page 64...
  • Page 65 The number of message objects in each transmit FIFO is configured using the FSIZE<4:0> bits (C1FIFOCONxH<12:8>). All objects in one transmit FIFO use the same payload size (number of data bytes), which is determined by the PLSIZE<2:0> bits (C1FIFOCONxH<15:13>).  2018 Microchip Technology Inc. DS70005340A-page 65...
  • Page 66 (FIFO) = 3, PayLoad (FIFO) = 8, Elements then the size of FIFO = S = 3 x (8 + 8) = 48 bytes FIFO Therefore, SRAM = S = 32 + 20 + 48 = 100 bytes. FIFO  2018 Microchip Technology Inc. DS70005340A-page 66...

  • Page 67: Message Transmission

    UINC bit (C1FIFOCONxL<8>). Doing so will cause the CAN FD Protocol Module to increment the head of the FIFO and update C1FIFOUAxH/L. Now the message is ready for transmission and the next message can be loaded at the new address.  2018 Microchip Technology Inc. DS70005340A-page 67...
  • Page 68 IDE: Identifier Extension bit; distinguishes between base and extended format bit 3-0 (T2) DLC<3:0>: Data Length Code bits bit 15:0 (T3) Unimplemented: Read as ‘x’ Data Bytes 0-n: Payload size is configured individually in the PLSIZE<2:0> bits (C1FIFOCONxH<15:13>). Note 1:  2018 Microchip Technology Inc. DS70005340A-page 68...
  • Page 69 TXQ will be transmitted first. The transmit priority will be recalculated after every successful transmission of a single message. 6.7.1 TRANSMIT PRIORITY OF MESSAGES IN FIFO In this method, the messages in a FIFO are transmitted First-In-First-Out.  2018 Microchip Technology Inc. DS70005340A-page 69...
  • Page 70 TX FIFO or TXQ is selected for transmission, or if a message is received after the last transmission attempt. 6.9.3 UNLIMITED RETRANSMISSIONS TXREQ will be cleared only after all messages in the TX FIFO or TXQ are successfully transmitted.  2018 Microchip Technology Inc. DS70005340A-page 70...
  • Page 71 • If the DLC is bigger than the reserved payload, the module will not transmit the message. Instead, it will set the IVMIF (C1INTL<15>) and DLCMM (C1BDIAG1H<15>) flags and clear the TXREQ flag. The application can use the TEF to identify the message that is not transmitted.  2018 Microchip Technology Inc. DS70005340A-page 71...
  • Page 72 Bus Idle & Waited for Suspend Time TX Successful RX Message TX In Progress Set TXIF[Index] TX Attempts Exhausted? Clr TXREQ[Index] Transmit[Index] Error TX ERR Success Set TXERRIF Flag TX Attempts-- Lost Arbitration Lost Arbitration TXLARB[Index]  2018 Microchip Technology Inc. DS70005340A-page 72...
  • Page 73 RTR:1; unsigned BRS:1; unsigned FDF:1; unsigned ESI:1; unsigned SEQ:7; unsigned unimplemented1:16; } CANFD_TX_MSGOBJ_CTRL; /* CANFD TX Message ID*/ typedef struct _CANFD_MSGOBJ_ID { unsigned SID:11; unsigned long EID:18; unsigned SID11:1; unsigned unimplemented1:2; } CANFD_MSGOBJ_ID;  2018 Microchip Technology Inc. DS70005340A-page 73...
  • Page 74 //2 messages C1FIFOCON1Hbits.PLSIZE = 0x2; //16 bytes of data C1FIFOCON1Lbits.TXEN = 0x1; // Set TXEN bit ,transmit fifo /* Place the CAN module in Normal mode. */ C1CONHbits.REQOP = 0; while(C1CONHbits.OPMOD != 0);  2018 Microchip Technology Inc. DS70005340A-page 74...
  • Page 75 // CANFD frame txObj->bF.ctrl.IDE = 0; //Standard frame for (index=0;index<0xC;index++ ) txObj->byte[index+8] = 0x55 ; // 12 bytes of 0x55 C1FIFOCON1Lbits.UINC = 1; // Set UINC bit C1FIFOCON1Lbits.TXREQ = 1; // Set TXREQ bit while(1);  2018 Microchip Technology Inc. DS70005340A-page 75...

  • Page 76: Transmit Event Fifo - Tef

    • Placing the module in Configuration mode (OPMOD<2:0> = 100) Resetting the FIFO will reset the Head and Tail Pointers, and the C1TEFSTA register. The settings in the C1TEFCONH and C1TEFCONL registers will not change.  2018 Microchip Technology Inc. DS70005340A-page 76...
  • Page 77 Unimplemented: Read as ‘x’ bit 15-0 (TE4) TXMSGTS<15:0>: Transmit Message Timestamp bits bit 15-0 (TE5) TXMSGTS<31:16>: Transmit Message Timestamp bits TE4 and TE5 (TXMSGTSx) only exit in objects where TEFTSEN (C1TEFCONL<5>) is set. Note 1:  2018 Microchip Technology Inc. DS70005340A-page 77...
  • Page 78 } bF; unsigned int word[4]; unsigned char byte[8]; } CANFD_TX_MSGOBJ; /* CANFD TEF Message Object */ typedef union _CAN_TEF_MSGOBJ { struct CANFD_MSGOBJ_ID id; CANFD_TX_MSGOBJ_CTRL ctrl; CANFD_MSG_TIMESTAMP timeStamp; } bF; unsigned int word[4]; } CANFD_TEF_MSGOBJ;  2018 Microchip Technology Inc. DS70005340A-page 78...
  • Page 79 /* then set the UINC bit. Set the TXREQ bit to send the message. */ CANFD_TX_MSGOBJ *txObj; /* Transmit 5 messages from FIFO 1 - CANFD base frame with BRS*/ /* SID = 0x300 , 64 bytes of data */ (fifoSize= 0; fifoSize < 5; fifoSize++)  2018 Microchip Technology Inc. DS70005340A-page 79...
  • Page 80 /* Keep reading the TEF objects until the last transmitted message*/ (fifoSize= 0; fifoSize < 5; fifoSize++) while(C1TEFSTAbits.TEFNEIF ==0); CANFD_TEF_MSGOBJ *tefObj; tefObj = (CANFD_TEF_MSGOBJ *)C1TEFUAL; //ProcessTEFMessages (currentMessageBuffer) ; C1TEFCONLbits.UINC = 1 ; // Set UINC bit while(1);  2018 Microchip Technology Inc. DS70005340A-page 80...

  • Page 81: Message Filtering

    If none of the filters match, the received message will be discarded. Note: If the module receives a message that matches a filter, but the corresponding FIFO is a TX FIFO (TXEN = 1, RTREN = 0), the module will discard the received message.  2018 Microchip Technology Inc. DS70005340A-page 81...
  • Page 82 Identifiers 0, 1, 2 and 3, it is required to mask the lower two bits of the identifier by clearing the corresponding bits of the mask object.  2018 Microchip Technology Inc. DS70005340A-page 82...
  • Page 83 N = DNCNTx Calculate Index: M = 18-N Assemble Receive Data Bytes: No Match RXDB = {RXMAB.DB0, RXMAB.DB1, RXMAB.DB2[7:6]} Compare: C1FLTOBJm.EID[0:N] == RXDB[17 : M] ? Don’t Care if C1MASKm.MEID[i] = 0 Match  2018 Microchip Technology Inc. DS70005340A-page 83...
  • Page 84 EID<0:14> 01111 Data Byte 0<7:0> and Data Byte 1<7:0> EID<0:15> 10000 Byte 0<7:0> and Byte 1<7:0> and Byte 2<7> EID<0:16> 10001 10010 to 11111 Byte 0<7:0> and Byte 1<7:0> and Byte 2<7:6> EID<0:17>  2018 Microchip Technology Inc. DS70005340A-page 84...
  • Page 85 SID10 SID9 SID0 EID0 EID1 EID7 EID8 EID9 EID15 EID16 EID17 MESSAGE ACCEPTANCE FILTER MESSAGE ACCEPTANCE FILTER SID<10:0> EID<0:17> The DeviceNet™ filtering configuration shown for the EIDx bits is DNCNT<4:0> = 10010. Note:  2018 Microchip Technology Inc. DS70005340A-page 85...

  • Page 86: Message Reception

    UINC bit (C1FIFOCONxL<8>). This will make the CAN FD Protocol Module increment to the tail of the FIFO and update C1FIFOUAxH/L. Now the application can read the next message from the RX FIFO.  2018 Microchip Technology Inc. DS70005340A-page 86...
  • Page 87 15:0 (R5) RXMSGTS<31:16>: Receive Message Timestamp bits Receive Message Object: Data Bytes 0-n; payload size is configured individually with the PLSIZE<2:0> bits. Note 1: R2 (RXMSGTSx) only exits in objects where RXTSEN is set.  2018 Microchip Technology Inc. DS70005340A-page 87...
  • Page 88 DNCNTx > 0 and DLC > 0? Error Error Filter Match? Error Success Receive Success Data Bytes 0-3 Receive Rest of Message Set RXOVIF Object Full? Receive Remaining RXIF Set? Data Bytes and Store them Success  2018 Microchip Technology Inc. DS70005340A-page 88...
  • Page 89 CANFD_MSG_TIMESTAMP; /* CANFD RX Message Object Control*/ typedef struct _CANFD_RX_MSGOBJ_CTRL { unsigned DLC:4; unsigned IDE:1; unsigned RTR:1; unsigned BRS:1; unsigned FDF:1; unsigned ESI:1; unsigned unimplemented1:2; unsigned FilterHit:5; unsigned unimplemented2:16; } CANFD_RX_MSGOBJ_CTRL;  2018 Microchip Technology Inc. DS70005340A-page 89...
  • Page 90 //Don't save transmitted messages in TEF C1CONHbits.TXQEN = 0x0; // No TXQ /* Configure FIFO1 to Receive 2 messages*/ C1FIFOCON1Hbits.FSIZE = 0x1; //2 messages C1FIFOCON1Hbits.PLSIZE = 0x7; //64 bytes of data C1FIFOCON1Lbits.TXEN = 0x0; //Receive fifo  2018 Microchip Technology Inc. DS70005340A-page 90...
  • Page 91 /* Get the address of the message buffer to read the received messages.*/ /* set UINC bit to update the FIFO tail */ CANFD_RX_MSGOBJ *rxObj; rxObj = (CANFD_RX_MSGOBJ *)C1FIFOUA1L; while(C1FIFOSTA1bits.TFNRFNIF ==0); //Process the received messages C1FIFOCON1Lbits.UINC = 1; // Update the FIFO message pointer. while(1);  2018 Microchip Technology Inc. DS70005340A-page 91...

  • Page 92: Fifo Behavior

    The status flags of the TXQ are set when there is space to load a new message object into the TXQ. Before the first message object is loaded (after the TXQ is reset), all status flags are set. When the TXQ is fully loaded, all flags are cleared.  2018 Microchip Technology Inc. DS70005340A-page 92...
  • Page 93 The user application now sets TXREQ to request the transmission of MSG0. Figure 10-2: FIFO 1 – First Message Loaded C1FIFOUA1L = 0x218 MO0/MSG0 C1FIFOSTA1: FIFOCIx = 0 TFEIF = 0 TFHIF = 1 TFNIF = 1 C1FIFOCON1L: TXREQ = 1  2018 Microchip Technology Inc. DS70005340A-page 93...
  • Page 94 Figure 10-5: FIFO 1 – FIFO Fully Loaded C1FIFOUA1L = 0x218 MO0/MSG5 C1FIFOSTA1: MO1/MSG1 FIFOCIx = 1 TFEIF = 0 MO2/MSG2 TFHIF = 0 MO3/MSG3 TFNIF = 0 C1FIFOCON1L: MO4/MSG4 TXREQ = 1  2018 Microchip Technology Inc. DS70005340A-page 94...
  • Page 95 FIFO 2 after MSG0 is read. The user application reads the message from RAM and sets the UINC bit (C1FIFOCON2L<8>). The user address increments and points to MO1. The FIFO index is unchanged. The FIFO is empty again. All flags are cleared.  2018 Microchip Technology Inc. DS70005340A-page 95...
  • Page 96 The user address still points to MO1. The FIFO index points to MO0. RFNIF and RFHIF are set. Figure 10-11: FIFO 2 – FIFO Almost Full C1FIFOUA2L = 0x384 C1FIFOSTA2: MO1/MSG1 FIFOCIx = 0 RFFIF = 0 MO2/MSG2 RFHIF = 1 RFNIF = 1 RXOVIF = 0 MO15/MSG15  2018 Microchip Technology Inc. DS70005340A-page 96...
  • Page 97 MO3. The FIFO index has not changed. Figure 10-14: FIFO 2 – Two More Messages Read C1FIFOUA2L = 0x41C MO0/MSG16 C1FIFOSTA2: FIFOCIx = 1 RFFIF = 0 RFHIF = 1 MO3/MSG3 RFNIF = 1 RXOVIF = 0 MO4/MSG4 MO15/MSG15  2018 Microchip Technology Inc. DS70005340A-page 97...
  • Page 98 TXQNIF = 1 C1TXQCONL: TXREQ = 0 Figure 10-18 illustrates the status of the TXQ after MSG1 is loaded and UINC is set. The user address now points to the next free message object: MO0.  2018 Microchip Technology Inc. DS70005340A-page 98...
  • Page 99 C1TEFCONL and C1TEFCONH are used to control the TEF. C1TEFSTA contains the status flags. C1TEFUAL and C1TEFUAH contain the user address of the next message object to read. The actual RAM address is calculated using Equation 7-1.  2018 Microchip Technology Inc. DS70005340A-page 99...
  • Page 100 MO1. The TEF is empty again. All flags are cleared. Figure 10-23: TEF – First ID Read C1TEFUAL = 0x00C C1TEFSTA: TEFFIF = 0 TEFHIF = 0 TEFNEIF = 0 TEFOVIF = 0 MO11  2018 Microchip Technology Inc. DS70005340A-page 100...
  • Page 101 TEF is full. The user address points to MO1. Figure 10-26: TEF – Full C1TEFUAL = 0x00C MO0/ID12 C1TEFSTA: MO1/ID1 TEFFIF = 1 TEFHIF = 1 MO2/ID2 TEFNEIF = 1 TEFOVIF = 0 MO11/ID11  2018 Microchip Technology Inc. DS70005340A-page 101...
  • Page 102 TEFFIF is clear because the TEF is not full anymore. The user address points to MO2. Figure 10-28: TEF – One More ID Read MO0/ID12 C1TEFUAL = 0x018 C1TEFSTA: MO2/ID2 TEFFIF = 0 TEFHIF = 1 MO3/ID3 TEFNEIF = 1 TEFOVIF = 0 MO11/ID11  2018 Microchip Technology Inc. DS70005340A-page 102...

  • Page 103: Timestamping

    No error till end of EOF No error till end of EOF Valid RX No error till the last, but one bit of No error till the last, but one bit of EOF  2018 Microchip Technology Inc. DS70005340A-page 103...

  • Page 104: Interrupts

    • Receive Interrupt • Transmit Interrupt • Information Interrupt All module interrupts are persistent, meaning the condition that caused the interrupt must be cleared within the module for the interrupt request to be removed.  2018 Microchip Technology Inc. DS70005340A-page 104...
  • Page 105 TEFIF (C1INTL) TEFFIE IVMIE (C1INTH) TEFFIF Info Interrupt TEFHIE IVMIF (C1INTL) TEFHIF WAKIE (C1INTH) TEFNEIE WAKIF (C1INTL) TEFNEIF CERRIE (C1INTH) CERRIF (C1INTL) MODIE (C1INTH) MODIF (C1INTL) TBCIE (C1INTH) TBCIF (C1INTL) SERRIE (C1INTH) SERRIF (C1INTL)  2018 Microchip Technology Inc. DS70005340A-page 105...
  • Page 106 TRANSMIT FIFO ATTEMPT INTERRUPT – TXATIF When the retransmission of a message fails due to an error, and all retransmission attempts are exhausted, the TXATIF flag is set. The flag must be cleared by the application.  2018 Microchip Technology Inc. DS70005340A-page 106...
  • Page 107 The flag will not be set if the ESI of a received message is set. 12.3.2 WAKE-UP INTERRUPT – WAKIF This bit is set if bus activity has been detected while the module is in Sleep mode. The flag must be cleared by the application.  2018 Microchip Technology Inc. DS70005340A-page 107...
  • Page 108 If the transmission is in progress, it will stop and the module will transition to either Restricted Operation or Listen Only mode, which is selectable using the SERRLOM bit (C1CONH<2>).  2018 Microchip Technology Inc. DS70005340A-page 108...
  • Page 109 • In the register map, the Interrupt Status registers are arranged in a single block: C1VECH/L, followed by C1INTH/L, C1RXIFH/L, C1TXIFH/L, C1RXOVIFH/L and C1TXATIFH/L. This arrangement allows all status registers to be read with a single read access.  2018 Microchip Technology Inc. DS70005340A-page 109...
  • Page 110 — System Error The flags will be cleared when the condition of the FIFO terminates, initiated by the Note 1: UINC bit (C1FIFOCONxL<8>. The flags need to be cleared in the preceding hierarchies.  2018 Microchip Technology Inc. DS70005340A-page 110...

  • Page 111: Error Handling

    ‘0’ to the register. The error-free message counter, together with the error counters and error flags, can be used to determine the quality of the bus.  2018 Microchip Technology Inc. DS70005340A-page 111...
  • Page 112 The module signals the exit from the bus off state with the CERRIF bit and by setting the TXBOERR bit (C1BDIAG1H<7>). Additionally, C1TREC will be reset.  2018 Microchip Technology Inc. DS70005340A-page 112...

  • Page 113: Related Application Notes

    CAN FD Protocol Module include the following: Title Application Note # No related application notes at this time. Please visit the Microchip web site (www.microchip.com) for additional application Note: notes and code examples for the dsPIC33/PIC24 family of devices.  2018 Microchip Technology Inc. DS70005340A-page 113...

  • Page 114: Revision History

    Family Reference Manual 15.0 REVISION HISTORY Revision A (February 2018) This is the initial version of this document.  2018 Microchip Technology Inc. DS70005340A-page 114...
  • Page 115 Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology and manufacture of development systems is ISO 9001:2000 certified. Inc., in other countries.
  • Page 116 New York, NY Tel: 46-31-704-60-40 Tel: 631-435-6000 Sweden - Stockholm San Jose, CA Tel: 46-8-5090-4654 Tel: 408-735-9110 UK - Wokingham Tel: 408-436-4270 Tel: 44-118-921-5800 Canada - Toronto Fax: 44-118-921-5820 Tel: 905-695-1980 Fax: 905-695-2078  2018 Microchip Technology Inc. DS70005340A-page 116 10/25/17...

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