Microchip Technology dsPIC33 Series Reference Manual
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Microchip Technology dsPIC33 Series Reference Manual

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Capture/Compare/PWM/Timer (MCCP and SCCP)
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0
2.0
3.0
4.0
8.0
9.0
5.0
10.0
10.0
10.0
11.0
12.0
13.0
 2013-2019 Microchip Technology Inc.
Introduction ...................................................................................................................... 2
Registers .......................................................................................................................... 3
Register Map.................................................................................................................... 4
Time Base Generator ..................................................................................................... 17
Module Sync Outputs..................................................................................................... 57
Sync and Triggered Operation ....................................................................................... 58
Timer Modes .................................................................................................................. 18
Operation During Sleep and Idle Modes ........................................................................ 64
Operation During Sleep and Idle Modes ........................................................................ 64
Operation During Sleep and Idle Modes ........................................................................ 64
Effects of a Reset........................................................................................................... 64
Related Application Notes.............................................................................................. 65
Revision History ............................................................................................................. 66
DS30003035B-page 1

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Summary of Contents for Microchip Technology dsPIC33 Series

  • Page 1: Table Of Contents

    Operation During Sleep and Idle Modes ................ 64 10.0 Operation During Sleep and Idle Modes ................ 64 11.0 Effects of a Reset......................64 12.0 Related Application Notes....................65 13.0 Revision History ......................66  2013-2019 Microchip Technology Inc. DS30003035B-page 1...

  • Page 2: Introduction

    • Brush DC Motor (Forward and Reverse) Modes • Half-Bridge with Dead-Time Delay • Push-Pull PWM Mode • Output Scan Mode • Auto-Shutdown with Programmable Source and Shutdown State • Programmable Output Polarity  2013-2019 Microchip Technology Inc. DS30003035B-page 2...

  • Page 3: Registers

    • CCPxRA is the 16-bit primary data buffer for Output Compare operations • CCPxRB is the 16-bit secondary data buffer for Output Compare operations • CCPxBUFH and CCPxBUFL are the 32-Bit Buffer register pair, which are used in Input Capture FIFO operations  2013-2019 Microchip Technology Inc. DS30003035B-page 3...

  • Page 4: Register Map

    REGISTER MAP A summary of the registers associated with the CCP modules (MCCP and SCCP) is shown in Table 3-1. This represents the superset MCCP module; registers and individual bits that are not implemented in the SCCP module are noted. Table 3-1: MCCP/SCCP Module Register Map Register...
  • Page 5 1 = Input Capture mode 0 = Output Compare/PWM or Timer mode (exact function selected by MOD[3:0] bits) Note 1: Refer to the device data sheet for available clock sources for a specific device family.  2013-2019 Microchip Technology Inc. DS30003035B-page 5...
  • Page 6 0001 = 16-Bit/32-Bit Single Edge mode: Drives output high on compare match 0000 = 16-Bit/32-Bit Timer mode: Output functions are disabled Note 1: Refer to the device data sheet for available clock sources for a specific device family.  2013-2019 Microchip Technology Inc. DS30003035B-page 6...
  • Page 7 Control bit has no function when TRIGEN = 0. Values greater than ‘0011’ will cause a FIFO buffer overflow in Input Capture mode. Refer to the device data sheet for Sync sources for a specific device family.  2013-2019 Microchip Technology Inc. DS30003035B-page 7...
  • Page 8 ASDG[7:0]: CCPx Auto-Shutdown/Gating Source Enable bits 1 = Auto-Shutdown/Gating Source n is enabled 0 = Auto-Shutdown/Gating Source n is disabled Note 1: Refer to the device data sheet for the specific gating sources implemented for a device family.  2013-2019 Microchip Technology Inc. DS30003035B-page 8...
  • Page 9 OCFEN through OCBEN (bits[13:9]) are implemented in MCCP modules only. Auxiliary output is not implemented in all devices. Refer to the device data sheet for details. Refer to the device data sheet for specific Input Capture sources.  2013-2019 Microchip Technology Inc. DS30003035B-page 9...
  • Page 10 000010 = Inserts 2 dead-time delay periods between complementary output signals 000001 = Inserts 1 dead-time delay period between complementary output signals 000000 = Dead-time logic is disabled Note 1: This register is implemented in MCCP modules only.  2013-2019 Microchip Technology Inc. DS30003035B-page 10...
  • Page 11 10 = Pins are driven inactive when a shutdown event occurs 0x = Pins are in high-impedance state when a shutdown event occurs Note 1: These bits are implemented in MCCP modules only.  2013-2019 Microchip Technology Inc. DS30003035B-page 11...
  • Page 12 0 = The Input Capture FIFO buffer has not overflowed bit 0 ICBNE: Input Capture Buffer Status bit 1 = Input Capture buffer has data available 0 = Input Capture buffer is empty  2013-2019 Microchip Technology Inc. DS30003035B-page 12...
  • Page 13 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 TMRH[31:16]: 16-Bit Time Base Value bits  2013-2019 Microchip Technology Inc. DS30003035B-page 13...
  • Page 14 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PRH[31:16]: Period Register bits  2013-2019 Microchip Technology Inc. DS30003035B-page 14...
  • Page 15 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CMP[15:0]: Compare Value bits The 16-bit value to be compared against the CCPx time base.  2013-2019 Microchip Technology Inc. DS30003035B-page 15...
  • Page 16 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 BUF[31:16]: Compare Buffer Value bits Indicates the oldest captured time base value in the FIFO.  2013-2019 Microchip Technology Inc. DS30003035B-page 16...

  • Page 17: Time Base Generator

    Regardless of the operating mode, interrupt events are not generated by the CCP module based on the status of the gating inputs. If an interrupt is required for a gating event, the gating source itself must be used to generate the interrupt.  2013-2019 Microchip Technology Inc. DS30003035B-page 17...

  • Page 18: Timer Modes

    CPU events. It does not generate an output trigger signal like the primary time base. Figure 5-1: 16-Bit Dual Timer Mode CCPxPRL Comparator Set CCTxIF Reset/ Trigger SYNC[4:0] CCPxTMRL Control Comparator Special Event Trigger Time Base Clock Generator Sources CCPxRB CCPxTMRH Set CCPxIF Comparator CCPxPRH  2013-2019 Microchip Technology Inc. DS30003035B-page 18...
  • Page 19 A/D conversions and trigger other peripheral events. The trigger period is set by the value of the CCPxRB register and must be less than the counter period, as defined by the CCPxPRL register.  2013-2019 Microchip Technology Inc. DS30003035B-page 19...
  • Page 20 This function provides a simple way to measure the time of an external event. Timer clock gating is enabled whenever one or more of the ASDG[7:0] bits (CCPxCON2L[7:0]) is set, or when the SSDG bit (CCPxCON2L[12]) is set.  2013-2019 Microchip Technology Inc. DS30003035B-page 20...
  • Page 21 Edge Detect Logic Event and Set CCPxIF Clock IC Clock Interrupt Sources Select Clock Synchronizer Logic Increment Reset CCPxTMRH/L 2/4-Level FIFO Buffer Trigger and Sync Logic Trigger and Sync Sources CCPxBUF System Bus  2013-2019 Microchip Technology Inc. DS30003035B-page 21...
  • Page 22 // Capture ever rising edge of the event CCP1CON2Hbits.ICSEL= 0; // Capture rising edge on the Pin CCP1CON1Hbits.IOPS=0; // Interrupt on every input capture event CCP1CON1Lbits.TMRPS=0; // Set the clock pre-scaler (1:1) CCP1CON1Lbits.CCPON=1; // Enable CCP/input capture  2013-2019 Microchip Technology Inc. DS30003035B-page 22...
  • Page 23 Figure 6-3. Figure 6-3: Input Capture Prescaler Input Capture Events Prescale 1:4 Prescaler (MOD[3:0] = 0100) 1:16 Prescaler (MOD[3:0] = 0101)  2013-2019 Microchip Technology Inc. DS30003035B-page 23...
  • Page 24 The FIFO Pointer is adjusted whenever the most significant word of the buffer result is read by the CPU. This allows the results of a 32-bit Input Capture to be read by the 16-bit CPU.  2013-2019 Microchip Technology Inc. DS30003035B-page 24...
  • Page 25 In either case, Input Capture input events will occur; however, a value of 0000h will always be captured in the FIFO. For these reasons, triggered operation and externally synchronized operation are not recommended.  2013-2019 Microchip Technology Inc. DS30003035B-page 25...
  • Page 26 MOD[3:0] and ICS[2:0] control bits. The module is now armed for a gate event. The next valid rising or falling input signal edge (depending on Capture mode), after ICDIS is cleared, will trigger a capture event.  2013-2019 Microchip Technology Inc. DS30003035B-page 26...
  • Page 27 Gating Resumes on Falling Edge, ICDIS Cleared by Hardware ICDIS Set by Hardware Note 1: Any device-defined hardware event when the corresponding ASDGx bit is set or when the SSDG bit is set.  2013-2019 Microchip Technology Inc. DS30003035B-page 27...
  • Page 28 Output Compare mode. Like many previous dsPIC33/PIC24 modules, Output Compare mode can function as a PWM generator. In MCCP modules, multiple PWM outputs can be used for power or motor control applications.  2013-2019 Microchip Technology Inc. DS30003035B-page 28...
  • Page 29 Rollover OCFA/OCFB Comparator Match Match Event Trigger and Event Fault Logic Trigger and Sync Logic Sync Sources CCPxRB Buffer Rollover/Reset CCPxRB Set CCPxIF Reset Note 1: Buffered Output Compare and PWM modes only.  2013-2019 Microchip Technology Inc. DS30003035B-page 29...
  • Page 30 0001 CCPxTMR SYNC[4:0] Input CCPxRA 3002 OCx Output Set CCPxIF Set CCTxIF SCEVT SCEVT Set by Hardware SCEVT Cleared in Software Note 1: SCEVT has to be cleared to enable the next capture.  2013-2019 Microchip Technology Inc. DS30003035B-page 30...
  • Page 31 0001 CCPxTMR SYNC[4:0] Input 3002 CCPxRA OCx Output Set CCPxIF Set CCTxIF SCEVT SCEVT Set by Hardware SCEVT Cleared in Software Note 1: SCEVT has to be cleared to enable the next capture.  2013-2019 Microchip Technology Inc. DS30003035B-page 31...
  • Page 32 0502 0600 0000 0001 0500 0501 0502 CCPxTMR SYNC[4:0] Input CCPxRA 0500 OCx Pin Output Set CCPxIF Set CCTxIF SCEVT SCEVT Set by Hardware SCEVT Cleared in Software (no effect on OCx pin)  2013-2019 Microchip Technology Inc. DS30003035B-page 32...
  • Page 33 Figure 7-5: Single Compare Mode, Toggle Output, Timer Period = CCPxRA CCP Clock 0500 0000 0001 0500 0000 0001 0500 0000 0001 CCPxTMR SYNC[4:0] Input CCPxRA 0500 OCx Pin Output Set CCPxIF Set CCTxIF  2013-2019 Microchip Technology Inc. DS30003035B-page 33...
  • Page 34 No period register is available to set the count period of CCPxTMR. If a count period less than FFFF FFFFh is desired, the module can be synchronized to an external source to set the count period.  2013-2019 Microchip Technology Inc. DS30003035B-page 34...
  • Page 35 Figure 7-6: Typical Dual Edge Compare Timing Sequence CCP Clock CCPxTMR 03FF 0400 0401 05FF 0600 0601 0800 0000 0001 CCPxRA 0400 0600 CCPxRB CCPxPR 0800 OCx Pin Output Set CCPxIF Set CCTxIF  2013-2019 Microchip Technology Inc. DS30003035B-page 35...
  • Page 36 CCP clock cycle wide is generated. 7.2.3 TIMER PERIOD < CCPxRA When the value of CCPxRA is greater than the timer period, no output pulses are generated.  2013-2019 Microchip Technology Inc. DS30003035B-page 36...
  • Page 37 Timing for Dual Edge Compare (CCPxPR < CCPxRB) CCP Clock 3000 3001 3002 3003 0000 3000 3001 3002 3003 0000 3000 CCPxTMR SYNC[4:0] Input CCPxRA 3000 3004 CCPxRB OCx Pin Set CCPxIF Set CCTxIF  2013-2019 Microchip Technology Inc. DS30003035B-page 37...
  • Page 38 Input CCPxRA 3003 3000 CCPxRB OCx Pin Set CCPxIF Set CCTxIF Note: When operating in Dual Compare mode, the CCTxIF signal is asserted on a match between the CCPxRB register value and CCPxTMRL.  2013-2019 Microchip Technology Inc. DS30003035B-page 38...
  • Page 39 CCP Clock SYNC[4:0] Input Write to CCPxRA CCPxRA Buffer YYYYh ZZZZh Data Written to Buffer CCPxRA YYYYh ZZZZh CCPxTMRL FFFEh FFFFh 000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h  2013-2019 Microchip Technology Inc. DS30003035B-page 39...
  • Page 40 PWM signal occurs. Note: Updates to the CCPxRA register are buffered and become active in the next PWM period. The comparison of CCPxPRL is always done with the buffered value of CCPxRA.  2013-2019 Microchip Technology Inc. DS30003035B-page 40...
  • Page 41 (CCPxPR + 1). Any applications should limit the maximum value written to the CCPxRA register, based on the value of CCPxPR. No pulses will be produced when CCPxRA is greater than (CCPxPR + 1).  2013-2019 Microchip Technology Inc. DS30003035B-page 41...
  • Page 42 The value of CCPxRB must be less than the period set by the CCPxPRL register or by events from the selected SYNC[4:0] input. The Special Event Trigger can be used to start an A/D conversion or trigger other peripheral events.  2013-2019 Microchip Technology Inc. DS30003035B-page 42...
  • Page 43  Figure 7-15: Timing for Variable Frequency Pulse-Width Mode CCP Clock 0000 5000 A000 F000 4000 9000 E000 3000 8000 D000 2000 7000 C000 CCPxTMR 5000 CCPxRA CCP Sync (Set CCTxIF) OCx Pin  2013-2019 Microchip Technology Inc. DS30003035B-page 43...
  • Page 44 For example, the Half-Bridge Output mode replicates the same pair of signals on the OCxA/OCxB, OCxC/OCxD and OCxE/OCxF pins. The user can enable any of these pin pairs using the OCxEN bits to move the signals to a convenient location.  2013-2019 Microchip Technology Inc. DS30003035B-page 44...
  • Page 45 The connections with the second pair of transistors are intentionally swapped so that each pair of diagonal transistors is on at the same time.  2013-2019 Microchip Technology Inc. DS30003035B-page 45...
  • Page 46 OCxB/D/F Set CCTxIF Set CCPxIF CCPxRA Value CCPxRA Change Changed Here to 2000h Takes Effect Figure 7-17: Typical Push-Pull Operation ® OCxA OCxB Figure 7-18: Typical Full-Bridge Operation ® OCxA OCxB OCxD OCxC  2013-2019 Microchip Technology Inc. DS30003035B-page 46...
  • Page 47 For more information on the dead-time generator, see Section 7.6.10 “Dead-Time Delay Generator”. Figure 7-19: Half-Bridge Outputs OCxA/C/E (active-high) OCxB/D/F (active-low) Dead Time Typical Half-Bridge Application Figure 7-20: ® Driver OCxA Load Driver OCxB  2013-2019 Microchip Technology Inc. DS30003035B-page 47...
  • Page 48 Brush DC Forward Mode (OUTM[2:0] = 101) ® Driver OCxA INACTIVE Driver OCxB INACTIVE Driver OCxC ACTIVE Driver OCxD Brush DC Reverse Mode (OUTM[2:0] = 100) ® INACTIVE Driver OCxA ACTIVE Driver OCxB OCxC Driver INACTIVE OCxD Driver  2013-2019 Microchip Technology Inc. DS30003035B-page 48...
  • Page 49 (02h). Figure 7-22: Direction Change in Brushed DC Mode (DT[5:0] = 02h) CCP Clock SYNC[4:0] Input OCxA Output Compare Signal OCxB Output Compare Signal OCxC OCxD Dead-Time Delay OUTM0 Toggled Direction Change Starts  2013-2019 Microchip Technology Inc. DS30003035B-page 49...
  • Page 50 Figure 7-23: Output Scan Mode (Double-Edge Compare) CCP Clock CCPxTMR 0001 0002 0003 0001 0002 0003 0000 0001 0002 CCPxRA 0001 CCPxRB 0002 CCPxPR 0100 OCxA Output OCxB Output OCxE Output  2013-2019 Microchip Technology Inc. DS30003035B-page 50...
  • Page 51 For all other settings of the OUTMx bits, all outputs enabled via the OCxEN control bits are driven active when the time base is triggered. Regardless of the mode, all enabled output pins are held in a high-impedance state when the timer is not triggered (CCPTRIG = 0).  2013-2019 Microchip Technology Inc. DS30003035B-page 51...
  • Page 52 A timing diagram for the dead-time generator’s output, showing the relationship between the true and complementary signals, is provided in Figure 7-25 Figure 7-25: Dead-Time Delay Generator Output (DT[5:0] = 01h) CCP Clock Output Compare Signal PWM True Output PWM Complementary Output Dead Time Dead Time  2013-2019 Microchip Technology Inc. DS30003035B-page 52...
  • Page 53 The output and port control signals for the OCxA/OCxB pin pair are replicated for the OCxC/ OCxD and OCxE/OCxF output pins in this Half-Bridge mode. This allows the user to relocate the complementary output signals to another pin pair using the OCxEN bits.  2013-2019 Microchip Technology Inc. DS30003035B-page 53...
  • Page 54 2: Any enabled shutdown source selected by the ASDGx bits and the SSDG software shutdown bit has priority over a software write to the ASEVT bit. The Fault condition cannot be exited unless all shutdown sources are inactive.  2013-2019 Microchip Technology Inc. DS30003035B-page 54...
  • Page 55 Output Output Resumes when ASEVT is Cleared ASEVT Bit Cleared in Software Note 1: Any device-defined hardware shutdown event when the corresponding ASDG bit is set, or when the SSDG bit is set.  2013-2019 Microchip Technology Inc. DS30003035B-page 55...
  • Page 56 The output polarity control is applied to the output signal after the dead-time control and auto- shutdown logic. The polarity control bits are effective for all Output Compare and PWM modes of the module.  2013-2019 Microchip Technology Inc. DS30003035B-page 56...

  • Page 57: Module Sync Outputs

    Time Base Period Reset or Rollover (Output Compare modes) Output Compare Event Signal Output Compare Signal Time Base Period Reset or Rollover xxxx (Input Capture modes) Reflects the Value of the ICDIS Bit Input Capture Event Signal  2013-2019 Microchip Technology Inc. DS30003035B-page 57...

  • Page 58: Sync And Triggered Operation

    The timer functions in Synchronized operation when TRIGEN (CCPxCON1H[7]) is cleared and the SYNC[4:0] bits have any value except ‘11111’. The CCPTRIG bit (CCPxSTATL[7]) has no function. Figure 9-1: Timer Synchronized Operation Time Base Clock SYNC[4:0] Input CCPxTMR 0010h 0011h 0012h 0000h 0001h 0002h  2013-2019 Microchip Technology Inc. DS30003035B-page 58...
  • Page 59 • When initializing synchronized modules, the module being used as the synchronization source should be enabled last. This ensures that the timers of all synchronized modules are maintained in a Reset condition until the last module is initialized.  2013-2019 Microchip Technology Inc. DS30003035B-page 59...
  • Page 60 MCCP1 Clock SYNC[4:0] Input (MCCP1) CCP1PRL 0012h CCP1TMRL 0010h 0011h 0012h 0000h 0001h 0002h MCCP1 Sync Out (to MCCP1 and MCCP2) MCCP2 Clock SYNC[4:0] Input (MCCP1) CCP2TMRL 0010h 0011h 0012h 0000h 0001h 0002h  2013-2019 Microchip Technology Inc. DS30003035B-page 60...
  • Page 61 Timing for Triggered Operation (Hardware/Software Operations) CCP Clock SYNC[4:0] Input CCPTRIG Set CCPTRIG Set CCPTRIG Cleared (TRSET = 1 ) by SYNC[4:0] (TRCLR = 1 ) CCPTRIG 0000h 0000h 0000h 0001h 0002h 0000h 0000h 0001h 0002h 0003h CCPxTMRL  2013-2019 Microchip Technology Inc. DS30003035B-page 61...
  • Page 62 When the time base clock source is asynchronous to the system clock, there will be a delay of up to two time base clock cycles before a trigger set or clear request from software affects the trigger state of the module.  2013-2019 Microchip Technology Inc. DS30003035B-page 62...
  • Page 63 SYNC[4:0] Input CCPTRIG Cleared CCPTRIG Set CCPTRIG Set by Hardware (TRSET = 1) by SYNC[4:0] CCPTRIG ONESHOT CCP Sync Output CCPxTMRL 0000h 0000h 0000h 0001h 0002h 0000h 0000h 0001h 0002h 0000h CCPxPR 0002h  2013-2019 Microchip Technology Inc. DS30003035B-page 63...

  • Page 64: Operation During Sleep And Idle Modes

    By default, the pin associated with OCxA (MCCP modules) or OCx (SCCP modules) resets with the Output Compare function in control of the pin; however, this has no effect when the module is disabled.  2013-2019 Microchip Technology Inc. DS30003035B-page 64...

  • Page 65: Related Application Notes

    Capture/Compare/PWM/Timer (MCCP and SCCP) are: Title Application Note # No related application notes at this time. Note: Please visit the Microchip website (www.microchip.com) for additional application notes and code examples for the dsPIC33/PIC24 families of devices.  2013-2019 Microchip Technology Inc. DS30003035B-page 65...

  • Page 66: Revision History

    Original version of this document. Revision B (February 2019) Updated Section 2.0 “Registers”. Added Register 3-8, Register 3-9, Register 3-10, Register 3-11, Register 3-12, Register 3-13, Register 3-14 Register 3-15. Re-ordered major chapters.  2013-2019 Microchip Technology Inc. DS30003035B-page 66...
  • Page 67 WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and the U.S.A.
  • Page 68 New York, NY Tel: 46-31-704-60-40 Tel: 631-435-6000 Sweden - Stockholm San Jose, CA Tel: 46-8-5090-4654 Tel: 408-735-9110 UK - Wokingham Tel: 408-436-4270 Tel: 44-118-921-5800 Canada - Toronto Fax: 44-118-921-5820 Tel: 905-695-1980 Fax: 905-695-2078  2013-2019 Microchip Technology Inc. DS30003035B-page 68 08/15/18...

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