Microchip Technology dsPIC33 Family Reference Manual
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Microchip Technology dsPIC33 Family Reference Manual

I/o ports with peripheral pin select (pps)
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I/O Ports with Peripheral Pin Select (PPS)
HIGHLIGHTS
This section of the manual contains the following topics:
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2.0
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 2006-2019 Microchip Technology Inc.
Introduction ...................................................................................................................... 2
I/O Port Control Registers ................................................................................................ 3
Peripheral Multiplexing..................................................................................................... 7
Peripheral Pin Select........................................................................................................ 9
Port Descriptions............................................................................................................ 19
Change Notification (CN) Pins ....................................................................................... 19
Register Maps ................................................................................................................ 21
Related Application Notes.............................................................................................. 22
Revision History ............................................................................................................. 23
DS30009711C-page 1

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Summary of Contents for Microchip Technology dsPIC33

  • Page 1: Table Of Contents

    I/O Port Control Registers ....................3 Peripheral Multiplexing..................... 7 Peripheral Pin Select......................9 Port Descriptions......................19 Change Notification (CN) Pins ..................19 Register Maps ........................ 21 Related Application Notes....................22 Revision History ......................23  2006-2019 Microchip Technology Inc. DS30009711C-page 1...

  • Page 2: Introduction

    In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Most of the dsPIC33/PIC24 devices support the Peripheral Pin Select (PPS) feature. The PPS constitutes pins which users can map to the input and/or output of some digital peripherals.

  • Page 3: I/O Port Control Registers

    I/O bits, 0 and 1 on PORTA, with two consecutive Read-Modify-Write instructions in the PORTA register. At high CPU speeds and high-capacitive loading on the I/O pins, the unintended result of the example code is that only I/O bit 1 is set high.  2006-2019 Microchip Technology Inc. DS30009711C-page 3...
  • Page 4 Family Reference Manual Figure 2-1: Example of Unintended I/O Behavior Example Code: BSET PORTA, #0 ; Set pin 0 on Port A to ‘1’ BSET PORTA, #1 ; Set pin 1 on Port A to ‘1’ I/O Pin 1 Voltage...
  • Page 5 15-0 PORTx<15:0>: I/O Portx bits 1 = The pin data are ‘1’ 0 = The pin data are ‘0’ Note 1: Refer to the specific device data sheet for the actual implementation.  2006-2019 Microchip Technology Inc. DS30009711C-page 5...
  • Page 6 Family Reference Manual Register 2-3: LATx: PORTx Data Latch Register R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LATx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LATx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’...

  • Page 7: Peripheral Multiplexing

    I/O pin to which they are connected. For some dsPIC33/PIC24 devices, multiple peripheral functions may be multiplexed on each I/O pin. The priority of the peripheral function depends on the order of the pin description in the pin diagram of the specific product data sheet.
  • Page 8 Family Reference Manual Multiplexing Digital Output Peripheral • Peripheral controls output data and PORTx register has no effect. • PORTx register can read pin value. • Pad output driver type is selected by peripheral (e.g., drive strength, slow rate, etc.).

  • Page 9: Peripheral Pin Select

    I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin.  2006-2019 Microchip Technology Inc. DS30009711C-page 9...
  • Page 10 Family Reference Manual Figure 4-1: Structure of Port Shared with PPS Peripherals Open-Drain Selection Peripheral Pin Select Output Multiplexers Output Function Select for the Pin Peripheral ‘n’ Output Enable Peripheral 2 Output Enable Peripheral 1 Output Enable I/O TRISx Enable Peripheral ‘n’...
  • Page 11 For example, assigning RPINR18<5:0> to 0x2 selects RP2 as the U1RX input. Figure 4-2 illustrates remappable pin selection for the U1RX input. Figure 4-2: Remappable Input for U1RX U1RXR<5:0> U1RX Input to Peripheral  2006-2019 Microchip Technology Inc. DS30009711C-page 11...
  • Page 12 Family Reference Manual Table 4-1: Selectable Input Sources (Maps Input to Function) Configuration Input Name Function Name Register Bits Bits External Interrupt 1 INT1 RPINR0<13:8> INT1R<5:0> External Interrupt 2 INT2 RPINR1<5:0> INT2R<5:0> External Interrupt 3 INT3 RPINR1<13:8> INT3R<5:0> External Interrupt 4 INT4 RPINR2<5:0>...
  • Page 13 Figure 4-3: Multiplexing of Remappable Output for RPn RPnR<5:0> I/O TRISx Setting U1TX Output Enable U1RTS Output Enable Output Enable OC5 Output Enable I/O LAT/PORT Content U1TX Output U1RTS Output Output Data OC5 Output  2006-2019 Microchip Technology Inc. DS30009711C-page 13...
  • Page 14 Family Reference Manual Table 4-1: Output Selection for Remappable Pin (RPn) Function RPnR<5:0> Output Name NULL The pin is an I/O Port pin. C1OUT RPn tied to Comparator 1 Output. C2OUT RPn tied to Comparator 2 Output. U1TX RPn tied to UART1 Transmit.
  • Page 15 Controlling Configuration Changes Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dsPIC33/PIC24 devices include three features to prevent alterations to the peripheral map: • Control register lock sequence •...
  • Page 16 Family Reference Manual Considerations for Peripheral Pin Selection The ability to control Peripheral Pin Selection introduces several considerations into application design that should be considered.This is particularly true for several common peripherals which are only available as remappable peripherals.
  • Page 17 \n” “push \n” "mov #OSCCON, w1 \n" "mov #0x46, w2 \n" "mov #0x57, w3 \n" "mov.b w2, [w1] \n" "mov.b w3, [w1] \n" "bset OSCCON, #6 \n" “pop \n” “pop \n” “pop w1”;  2006-2019 Microchip Technology Inc. DS30009711C-page 17...
  • Page 18 Family Reference Manual Peripheral Pin Select Registers These registers are used to configure input and output functionality of the dsPIC33/PIC24 device pins. • RPINRx: Peripheral Pin Select Input Register x • RPORy: Peripheral Pin Select Output Register y Register 4-3:...

  • Page 19: Port Descriptions

    The Change Notification (CN) pins provide dsPIC33/PIC24 devices the ability to generate inter- rupt requests to the processor in response to a Change-of-State (COS) on selected input pins. The total number of available CN inputs is dependent on the selected dsPIC33/PIC24 device. Refer to the specific device data sheet for further details.
  • Page 20 Family Reference Manual CN Configuration and Operation The CN pins are configured as follows: Ensure that the CN pin is configured as a digital input by setting the associated bit in the TRISx register. Enable interrupts for the selected CN pins by setting the appropriate bits in the CNENx registers.

  • Page 21: Register Maps

    REGISTER MAPS A summary of the registers associated with the dsPIC33/PIC24 I/O ports is provided in Table 7-1, Table 7-2 Table 7-3. Table 7-1: Special Function Registers Associated with I/O Ports Name Bit 15 Bit 14 Bit 13 Bit 12...

  • Page 22: Related Application Notes

    This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC33/PIC24 families of devices, but the concepts are pertinent and could be used with modification and possible limitations. The...

  • Page 23: Revision History

    Added PPS section, removed JTAG boundary scan section and added PPS SFR table. Revision C (March 2019) Updated the reference manual to the latest template format. Added a note to Section 2.1 “TRIS Registers”.  2006-2019 Microchip Technology Inc. DS30009711C-page 23...
  • Page 24 Family Reference Manual NOTES:  2006-2019 Microchip Technology Inc. DS30009711C-page 24...
  • Page 25 WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and the U.S.A.
  • Page 26 New York, NY Tel: 46-31-704-60-40 Tel: 631-435-6000 Sweden - Stockholm San Jose, CA Tel: 46-8-5090-4654 Tel: 408-735-9110 UK - Wokingham Tel: 408-436-4270 Tel: 44-118-921-5800 Canada - Toronto Fax: 44-118-921-5820 Tel: 905-695-1980 Fax: 905-695-2078  2006-2019 Microchip Technology Inc. DS30009711C-page 26 08/15/18...

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