Texas Instruments SimpleLink MSP432P401R Manual page 157

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6.12.14 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
Figure 6-10 shows the port diagram.
ADC Reference
To Comparator
From Comparator
CPD.q
PyREN.x
PyDIR.x 0 0
0 1
1 0
1 1
PyOUT.x 0 0
From module 0 1
DVSS
1 0
DVSS 1 1
PySEL1.x
PySEL0.x
PyIN.x
To module
Functional representation only.
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Table 6-75
Direction
0: Input
1: Output
EN
D
Figure 6-10. Py.x/Mod/VREF/VeREF/Cp.q Pin Diagram
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SLAS826F – MARCH 2015 – REVISED MARCH 2017
summarizes the selection of the pin functions.
DVSS
0
DVCC 1
Bus
Keeper
MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
Pad Logic
1
Py.x/Mod/VREF/VeREF/Cp.q
Detailed Description 157