TYAN Trinity ATX Motherboard S1598 User Manual page 53

IRQ-n Assigned to
When resources are controlled manually, assign each system interrupt as one
of the following types, depending on the type of device using the interrupt:
Legacy ISA: Devices compliant with the original PC AT bus
specification, requiring a specific interrupt (such as IRQ4 for serial
port 1).
PCI/ISA PnP: Devices compliant with the Plug and Play standard,
whether designed for PCI or ISA bus architecture.
DMA-n Assigned to
When resources are controlled manually, assign each system DMA channel as
one of the following types, depending on the type of device using the
interrupt:
Legacy ISA: Devices compliant with the original PC AT bus
specification, requiring a specific DMA channel
PCI/ISA PnP: Devices compliant with the Plug and Play standard,
whether designed for PCI or ISA bus architecture.
CPU to PCI Write Buffer
When this field is Enabled, writes from the CPU to the PCI bus are buffered, to
compensate for the speed differences between the CPU and the PCI bus.
When Disabled, the writes are not buffered and the CPU must wait until the
write is complete before starting another write cycle.
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Burstable
transactions then burst on the PCI bus; nonburstable transactions do not.
PCI Master 0 WS Write
When this field is Enabled, writes to the PCI bus are executed with zero wait
states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transaction cycles. Select Enabled to support compliance with PCI specifica-
tion version 2.1.
PCI#2 Access #1 Retry
Select Enabled to rotate priority of PCI masters.
S1598 Trinity ATX
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