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ARM Cortex NuMicro M452RD3AE
Nuvoton ARM Cortex NuMicro M452RD3AE Manuals
Manuals and User Guides for Nuvoton ARM Cortex NuMicro M452RD3AE. We have
1
Nuvoton ARM Cortex NuMicro M452RD3AE manual available for free PDF download: Technical Reference Manual
Nuvoton ARM Cortex NuMicro M452RD3AE Technical Reference Manual (1006 pages)
32-bit Microcontroller
Brand:
Nuvoton
| Category:
Microcontrollers
| Size: 10 MB
Table of Contents
Table of Contents
2
General Description
19
Table 1-1 Key Features Support Table
19
Features
21
Numicro ® M451 Features
21
Abbreviations
27
Table 3-1 List of Abbreviations
28
Parts Information List and Pin Configuration
29
Numicro M451 Selection Guide
29
Numicro ® M451 Naming Rule
29
Figure 4.1-1 Numicro M451 Selection Code
29
Numicro ® M451 Base Series Selection Guide
30
Numicro ® M451M Series (M051 Pin Compatible) Selection Guide
31
Numicro ® M452 USB Series Selection Guide
32
Numicro ® M453 CAN Series (CAN+USB) Selection Guide
33
Pin Configuration
34
Numicro ® M451 Base Series LQFP48 Pin Diagram
34
Figure 4.2-1 Numicro ® M451 Base Series LQFP 48-Pin Diagram
34
Numicro ® M451 Base Series LQFP64 Pin Diagram
35
Figure 4.2-2 Numicro M451 Base Series LQFP 64-Pin Diagram
35
Numicro ® M451 Base Series LQFP100 Pin Diagram
36
Figure 4.2-3 Numicro M451 Base Series LQFP 100-Pin Diagram
36
Numicro ® M451M Series (M051 Pin Compatible) LQFP48 Pin Diagram
37
Figure 4.2-4 Numicro ® M451M Base Series (Pin Compatible with M051) LQFP 48-Pin Diagram
37
Numicro ® M451M Series (M058S Pin Compatible) LQFP64 Pin Diagram
38
M451M Base Series (Pin Compatible with M058S) LQFP 64-Pin Diagram
38
Numicro ® M452 USB Series LQFP48 Pin Diagram
39
Figure 4.2-6 Numicro
39
M451 USB Series LQFP 48-Pin Diagram (M452LG/M452LE Device Only)
39
Figure 4.2-7 Numicro M451 USB Series LQFP 48-Pin Diagram (M452LD/M452LC Device Only)
40
Numicro ® M452 USB Series LQFP64 Pin Diagram
41
Figure 4.2-8 Numicro M451 USB Series LQFP 64-Pin Diagram (M452RG/M452RE Device Only)
41
Figure 4.2-9 Numicro ® M451 USB Series LQFP 64-Pin Diagram (M452RD Device Only)
42
Numicro ® M452 USB Series LQFP100 Pin Diagram
43
Figure 4.2-10 Numicro M451 USB Series LQFP 100-Pin Diagram (M452VG/M452VE Device Only)
43
Numicro ® M453 CAN Series (CAN+USB) LQFP48 Pin Diagram
44
Figure 4.2-11 Numicro M451 CAN Series (CAN+USB) LQFP 48-Pin Diagram (M453LG/M453LE Device Only)
44
Figure 4.2-12 Numicro M451 CAN Series (CAN+USB) LQFP 48-Pin Diagram (M453LD/M453LC Device Only)
45
Numicro ® M453 CAN Series (CAN+USB) LQFP64 Pin Diagram
46
Figure 4.2-13 Numicro M451 CAN Series (CAN+USB) LQFP 64-Pin Diagram (M453RG/M453RE Device Only)
46
Figure 4.2-14 Numicro M451 CAN Series (CAN+USB) LQFP 64-Pin Diagram (M453RD Device Only)
47
Numicro M453 CAN Series (CAN+USB) LQFP100 Pin Diagram
48
Figure 4.2-15 Numicro M451 CAN Series (CAN+USB) LQFP 100-Pin Diagram (M453VG/M453VE Device Only)
48
Figure 4.2-16 Numicro M451 CAN Series (CAN+USB) LQFP 100-Pin Diagram (M453VD Device Only)
49
Pin Description
50
M451 Base Series LQFP48 Pin Description
50
M451 Base Series LQFP64 Pin Description
58
M451 Base Series LQFP100 Pin Description
68
M451M Series (M051 Pin Compatible) LQFP48 Pin Description
81
M451M Series (M058S Pin Compatible) LQFP64 Pin Description
89
M452 USB Series LQFP48 Pin Description
98
M452 USB Series LQFP64 Pin Description
105
M452 USB Series LQFP100 Pin Description
114
M453 CAN Series(CAN+USB) LQFP48 Pin Description
127
M453 CAN Series(CAN+USB) LQFP64 Pin Description
135
M453 CAN Series(CAN+USB) LQFP100 Pin Description
144
GPIO Multi-Function Pin Summary
157
Table 4-1 M451 GPIO Multi-Function Table
166
Block Diagram
167
Numicro M451 Block Diagram
167
Figure 5.1-1 Numicro M45Xg/M45Xe Block Diagram
167
Figure 5.1-2 Numicro M45Xd/M45Xc Block Diagram
168
Functional Description
169
ARM ® Cortex ® -M4 Core
169
Figure 6.1-1 Cortex ® -M4 Block Diagram
169
System Manager
172
Overview
172
System Reset
172
Figure 6.2-1 System Reset Sources
173
Table 6-1 Reset Value of Registers
175
Figure 6.2-2 Nreset Reset Waveform
176
Figure 6.2-3 Power-On Reset (POR) Waveform
176
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
177
Figure 6.2-5 Brown-Out Detector (BOD) Waveform
178
Power Modes and Wake-Up Sources
179
Figure 6.2-6 Power Mode State Machine
179
Table 6-2 Power Mode Difference Table
179
System Power Distribution
181
Table 6-3 Clocks in Power Modes
181
Table 6-4 Condition of Entering Power-Down Mode Again
181
Figure 6.2-7 Numicro M451 Power Distribution Diagram
182
System Memory Map
183
Table 6-5 Address Space Assignments for On-Chip Controllers
185
SRAM Memory Organization
186
Figure 6.2-8 SRAM Block Diagram
186
Figure 6.2-9 SRAM Memory Organization (M45Xg/M45Xe)
187
Figure 6.2-10 SRAM Memory Organization (M45Xd/M45Xc)
188
Register Map
190
Register Description
192
System Timer (Systick)
231
Nested Vectored Interrupt Controller (NVIC)
235
Table 6-6 Exception Model
236
Table 6-7 Interrupt Number Table
238
System Control Register
258
Table 6-8 Priority Grouping
262
Clock Controller
267
Overview
267
Figure 6.3-1 Clock Generator Global View Diagram
268
Clock Generator
269
Figure 6.3-2 Clock Generator Block Diagram
269
System Clock and Systick Clock
270
Figure 6.3-3 System Clock Block Diagram
270
Peripherals Clock
271
Figure 6.3-4 HXT Stop Protect Procedure
271
Figure 6.3-5 Systick Clock Control Block Diagram
271
Power-Down Mode Clock
272
Clock Output
272
Figure 6.3-6 Clock Source of Clock Output
272
Figure 6.3-7 Clock Output Block Diagram
273
Register Map
274
Register Description
275
Table 6-9 Power-Down Mode Control Table
277
Flash Memeory Controller (FMC)
299
Overview
299
Features
299
Block Diagram
300
Figure 6.4-1 Flash Memory Controller Block Diagram
300
Functional Description
303
Figure 6.4-2 Data Flash Shared with APROM
303
Figure 6.4-3 Flash Memory Map
308
Figure 6.4-4 System Memory Map with IAP Mode
309
Figure 6.4-5 LDROM with IAP Mode
310
Figure 6.4-6 APROM with IAP Mode
310
Figure 6.4-7 System Memory Map Without IAP Mode
311
Figure 6.4-8 Boot Source Selection
312
Table 6-10 ISP Command List
314
Figure 6.4-9 ISP Procedure Example
315
Figure 6.4-10 ISP 32-Bit Programming Procedure
317
Figure 6.4-11 ISP 64-Bit Programming Procedure
317
Figure 6.4-12 Multi-Word Programming Time
318
Figure 6.4-13 Firmware in SRAM for Multi-Word Programming
319
Figure 6.4-14 Multi-Word Programming Flow
320
Figure 6.4-15 Fast Flash Programming Verification Flow
321
Figure 6.4-16 Verification Flow
322
Figure 6.4-17 Checksum for KB Calculation
322
Figure 6.4-18 Checksum Calculation Flow
324
Register Map
325
Register Description
326
External Bus Interface (EBI)
343
Overview
343
Features
343
Block Diagram
344
Basic Configuration
344
Functional Description
344
Figure 6.5-1 EBI Block Diagram
344
Figure 6.5-2 Connection of 16-Bit EBI Data Width with 16-Bit Device
345
Figure 6.5-3 Connection of 8-Bit EBI Data Width with 8-Bit Device
346
Figure 6.5-4 Timing Control Waveform for 16-Bit Data Width
348
Figure 6.5-5 Timing Control Waveform for 8-Bit Data Width
349
Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle
350
Register Map
351
Register Description
352
General Purpose I/O (GPIO)
356
Overview
356
Features
356
Block Diagram
357
Basic Configuration
357
Figure 6.6-1 GPIO Controller Block Diagram
357
Functional Description
358
Figure 6.6-2 Push-Pull Output
358
Figure 6.6-3 Open-Drain Output
358
Figure 6.6-4 Quasi-Bidirectional I/O Mode
359
Register Map
360
Register Description
363
PDMA Controller (PDMA)
378
Overview
378
Features
378
Block Diagram
378
Figure 6.7-1 PDMA Controller Block Diagram
378
Basic Configuration
379
Functional Description
379
Figure 6.7-2 Descriptor Table Entry Structure
379
Table 6-11 Channel Priority Table (M45Xg/M45Xe Only)
380
Table 6-12 Channel Priority Table (M45Xd/M45Xc Only)
380
Figure 6.7-3 Basic Mode Finite State Machine
381
Figure 6.7-4 Descriptor Table Link List Structure
382
Figure 6.7-5 Scatter-Gather Mode Finite State Machine
382
Figure 6.7-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode
384
Register Map
385
Register Description
387
Timer Controller (TMR)
416
Overview
416
Features
416
Block Diagram
417
Figure 6.8-1 Timer Controller Block Diagra
417
Basic Configuration
418
Functional Description
418
Figure 6.8-2 Clock Source of Timer Controller
418
Figure 6.8-3 Continuous Counting Mode
420
Register Map
423
Register Description
425
PWM Generator and Capture Timer (PWM)
435
Overview
435
Features
435
Block Diagram
437
Figure 6.9-1 PWM Generator Overview Block Diagram
437
Figure 6.9-2 PWM System Clock Source Control
437
Figure 6.9-3 PWM Clock Source Control
438
Table 6-13 PWM System Clock Source Control Registers Setting Table
438
Figure 6.9-4 PWM Independent Mode Architecture Diagram
439
Basic Configuration
440
Functional Description
440
Figure 6.9-5 PWM Complementary Mode Architecture Diagram
440
Figure 6.9-6 PWM_CH0 Prescaler Waveform
441
Figure 6.9-7 PWM up Counter Type
441
Figure 6.9-8 PWM down Counter Type
442
Figure 6.9-9 PWM Up-Down Counter Type
442
Figure 6.9-10 PWM CMPDAT Events in Up-Down Counter Type
443
Figure 6.9-11 PWM Double Buffering Illustration
444
Figure 6.9-12 Period Loading in Up-Count Mode
445
Figure 6.9-13 Immediately Loading in Up-Count Mode
446
Figure 6.9-14 Window Loading in Up-Count Mode
447
Figure 6.9-15 Center Loading in Up-Down-Count Mode
448
Figure 6.9-16 PWM One-Shot Mode Output Waveform
449
Figure 6.9-17 PWM Pulse Generation
450
Figure 6.9-18 PWM 0% to 100% Pulse Generation
450
Table 6-14 PWM Pulse Generation Event Priority for Up-Counter
450
Figure 6.9-19 PWM Independent Mode Waveform
451
Table 6-15 PWM Pulse Generation Event Priority for Down-Counter
451
Table 6-16 PWM Pulse Generation Event Priority for Up-Down-Counter
451
Figure 6.9-20 PWM Complementary Mode Waveform
452
Figure 6.9-21 PWM Group Function Waveform
453
Figure 6.9-22 PWM SYNC_IN Noise Filter Block Diagram
453
Figure 6.9-23 PWM Counter Synchronous Function Block Diagram
454
Figure 6.9-24 PWM Synchronous Function with SINSRC=0
455
Figure 6.9-25 PWM_CH0 Output Control in Independent Mode
455
Figure 6.9-26 PWM_CH0 and PWM_CH1 Output Control in Complementary Mode
456
Figure 6.9-27 Dead-Time Insertion
457
Figure 6.9-28 Illustration of Mask Control Waveform
457
Figure 6.9-29 Brake Noise Filter Block Diagram
458
Figure 6.9-30 Brake Block Diagram for PWM_CH0 and PWM_CH1 Pair
459
Figure 6.9-31 Edge Detector Waveform for PWM_CH0 and PWM_CH1 Pair
460
Figure 6.9-32 Level Detector Waveform for PWM_CH0 and PWM_CH1 Pair
460
Figure 6.9-33 Brake Source Block Diagram
461
Figure 6.9-34 Brake System Fail Block Diagram
461
Figure 6.9-35 Initial State and Polarity Control with Rising Edge Dead-Time Insertion
462
Figure 6.9-36 PWM_CH0 and PWM_CH1 Pair Accumulate Interrupt Waveform
463
Figure 6.9-37 PWM_CH0 and PWM_CH1 Pair Interrupt Architecture Diagram
464
Figure 6.9-38 PWM_CH0 and PWM_CH1 Pair Trigger EADC Block Diagram
465
Figure 6.9-39 PWM Trigger EADC in Up-Down Counter Type Timing Waveform
466
Figure 6.9-40 PWM_CH0 and PWM_CH1 Pair Trigger DAC Block Diagram
466
Figure 6.9-41 PWM_CH0 Capture Block Diagram
467
Figure 6.9-42 Capture Operation Waveform
468
Figure 6.9-43 Capture PDMA Operation Waveform of Channel 0
469
Register Map
470
Register Description
476
Watchdog Timer (WDT)
540
Overview
540
Features
540
Block Diagram
540
Clock Control
540
Figure 6.10-1 Watchdog Timer Block Diagram
540
Basic Configuration
541
Functional Description
541
Figure 6.10-2 Watchdog Timer Clock Control
541
Figure 6.10-3 Watchdog Timer Time-Out Interval and Reset Period Timing
542
Table 6-17 Watchdog Timer Time-Out Interval Period Selection
542
Register Map
543
Register Description
544
Window Watchdog Timer (WWDT)
547
Overview
547
Features
547
Block Diagram
547
Figure 6.11-1 WWDT Block Diagram
547
Clock Control
548
Basic Configuration
548
Functional Description
548
Figure 6.11-2 WWDT Clock Control
548
Figure 6.11-3 WWDT Reset and Reload Behavior
549
Table 6-18 WWDT Prescaler Value Selection
549
Table 6-19 CMPDAT Setting Limitation
550
Register Map
551
Register Description
552
Real Time Clock (RTC)
557
Overview
557
Features
557
Block Diagram
558
Basic Configuration
558
Functional Description
558
Figure 6.12-1 RTC Block Diagram
558
Table 6-20 RTC Control Registers Access Attribute
559
Figure 6.12-2 Backup I/O Control Diagram
564
Register Map
565
Register Description
567
UART Interface Controller (UART)
590
Overview
590
Features
590
Block Diagram
591
Table 6-21 Numicro M451 Series UART Feature
591
Figure 6.13-1 UART Clock Control Diagram
592
Figure 6.13-2 UART Block Diagram
593
Basic Configuration
594
Functional Description
594
Table 6-22 UART Interface Controller Pin
594
Table 6-23 UART Controller Baud Rate Equation Table
594
Table 6-24 UART Controller Baud Rate Parameter Setting Example Table
595
Figure 6.13-3 Auto-Baud Rate Measurement
596
Table 6-25 UART Controller Baud Rate Register Setting Example Table
596
Figure 6.13-4 Transmit Delay Time Operation
597
Figure 6.13-5 UART Ncts Wake-UP Case1
598
Figure 6.13-6 UART Ncts Wake-UP Case2
598
Figure 6.13-7 UART RX Data Wake-Up
598
Table 6-26 UART Controller Interrupt Source and Flag List
600
Table 6-27 UART Line Control of Word and Stop Length Setting
600
Table 6-28 UART Line Control of Parity Bit Setting
600
Figure 6.13-8 Auto-Flow Control Block Diagram
601
Figure 6.13-9 UART Ncts Auto-Flow Control Enabled
602
Figure 6.13-10 UART Nrts Auto-Flow Control Enabled
602
Figure 6.13-11 UART Nrts Auto-Flow with Software Control
603
Figure 6.13-12 Irda Control Block Diagram
603
Figure 6.13-13 Irda TX/RX Timing Diagram
604
Figure 6.13-14 Structure of LIN Frame
605
Figure 6.13-15 Structure of LIN Byte
605
Table 6-29 LIN Header Selection in Master Mode
606
Figure 6.13-16 Break Detection in LIN Mode
607
Figure 6.13-17 LIN Frame ID and Parity Format
608
Figure 6.13-18 LIN Sync Field Measurement
610
Figure 6.13-19 UART_BAUD Update Sequence in AR Mode if SLVDUEN Is 1
611
Figure 6.13-20 UART_BAUD Update Sequence in AR Mode if SLVDUEN Is 0
611
Figure 6.13-21 RS-485 Nrts Driving Level in Auto Direction Mode
615
Figure 6.13-22 RS-485 Nrts Driving Level with Software Control
615
Figure 6.13-23 Structure of RS-485 Frame
616
Register Map
617
Register Description
619
Smart Card Host Interface (SC)
646
Overview
646
Features
646
Block Diagram
646
Figure 6.14-1 SC Clock Control Diagram (4-Bit Pre-Scale Counter in Clock Controller)
647
Figure 6.14-2 SC Controller Block Diagram
647
Basic Configuration
648
Functional Description
648
Figure 6.14-3 SC Data Character
648
Table 6-30 SC Host Controller Pin Description
648
Table 6-31 UART Pin Description
648
Figure 6.14-4 SC Activation Sequence
649
Figure 6.14-5 SC Warm Reset Sequence
650
Figure 6.14-6 SC Deactivation Sequence
651
Figure 6.14-7 Basic Operation Flow
652
Figure 6.14-8 Initial Character TS
653
Figure 6.14-9 SC Error Signal
653
Figure 6.14-10 Transmit Direction Block Guard Time Operation
655
Table 6-32 Timer2/Timer1/Timer0 Operation Mode
655
Figure 6.14-11 Receive Direction Block Guard Time Operation
656
Figure 6.14-12 Extended Guard Time Operation
656
Register Map
657
Register Description
658
I 2 C Serial Interface Controller (I 2 C)
684
Overview
684
Features
684
Basic Configuration
684
Block Diagram
685
Functional Description
685
Figure 6.15-1 I 2 C Controller Block Diagram
685
Figure 6.15-2 I 2 C Bus Timing
685
Figure 6.15-3 I 2 C Protocol
686
Figure 6.15-4 START and STOP Conditions
688
Figure 6.15-5 Bit Transfer on the I 2 C Bus
690
Figure 6.15-6 Acknowledge on the I C Bus
690
Figure 6.15-7 Master Transmits Data to Slave
691
Figure 6.15-8 Master Reads Data from Slave
691
Figure 6.15-9 Control I
692
Status
692
Figure 6.15-10 Master Transmitter Mode Control Flow
693
Figure 6.15-11 Master Receiver Mode Control Flow
694
Figure 6.15-12 Save Mode Control Flow
695
Figure 6.15-13 GC Mode
697
Figure 6.15-14 Arbitration Lost
698
Table 6-33 Reserved Smbus Address
699
Figure 6.15-15 Bus Management Packet Protocol Diagram Element Key
700
Figure 6.15-167-Bit Addressable Device to Host Communication
701
Figure 6.15-177-Bit Addressable Device Responds to an ARA
701
Figure 6.15-18 Bus Management ALERT Function
702
Figure 6.15-19 SM Bus Time out Timing
703
Figure 6.15-20 I 2 C Data Shifting Direction
707
Table 6-34 I 2 C Status Code Description
709
Figure 6.15-21 I 2 C Time-Out Count Block Diagram
711
Figure 6.15-22 EEPROM Random Read
717
Figure 6.15-23 Protocol of EEPROM Random Read
718
Register Map
719
Register Description
720
Serial Peripheral Interface (SPI)
740
Overview
740
Features
740
Block Diagram
741
Figure 6.16-1 SPI Block Diagram (SPI0)
741
Figure 6.16-2 SPI Block Diagram (SPI1/2)
741
Basic Configuration
742
Functional Description
743
Figure 6.16-3 SPI Peripheral Clock
743
Table 6-35 SPI/I 2 S Interface Controller Pin
743
Figure 6.16-4 SPI Master Mode Application Block Diagram
744
Figure 6.16-5 SPI Slave Mode Application Block Diagram
744
Figure 6.16-632-Bit in One Transaction (Master Mode)
745
Figure 6.16-7 Automatic Slave Selection (SSACTPOL = 0, SPI_CYCLE > 0X2)
746
Figure 6.16-8 Automatic Selection (SSACTPOL = 0, SPI_CYCLE < 0X3)
746
Figure 6.16-9 Byte Reorder Function
747
Figure 6.16-10 Timing Waveform for Byte Suspend
747
Figure 6.16-11 Two-Bit Transfer Mode System Architecture
748
Figure 6.16-12 Two-Bit Transfer Mode Timing (Master Mode)
749
Figure 6.16-13 Bit Sequence of Dual Output Mode
750
Figure 6.16-14 Bit Sequence of Dual Input Mode
750
Figure 6.16-15 Bit Sequence of Quad Output Mode
751
Figure 6.16-16 Bit Sequence of Quad Input Mode
751
Figure 6.16-17 FIFO Threshold Comparator
752
Figure 6.16-18 Transmit FIFO Buffer Example
753
Figure 6.16-19 Receive FIFO Buffer Example
754
Figure 6.16-20 TX Underflow Event and Slave under Run Event (Slave 3-Wire Mode Disabled)
754
Figure 6.16-21 Two-Bit Transfer Mode FIFO Buffer Example
755
Figure 6.16-22 TX Underflow Event (Slave 3-Wire Mode Enabled)
755
Figure 6.16-23 Slave Mode Bit Count Error
756
Figure 6.16-24 Slave Time-Out Event
756
Figure 6.16-25 I 2 S Data Format Timing Diagram
758
Figure 6.16-26 MSB Justified Data Format Timing Diagram
759
Figure 6.16-27 PCM Mode a Timing Diagram
759
Figure 6.16-28 PCM Mode B Timing Diagram
759
Figure 6.16-29 FIFO Contents for Various I
760
Modes
760
Timing Diagram
761
Figure 6.16-30 SPI Timing in Master Mode
761
Figure 6.16-31 SPI Timing in Master Mode (Alternate Phase of Spin_Clk)
761
Figure 6.16-32 SPI Timing in Slave Mode
762
Figure 6.16-33 SPI Timing in Slave Mode (Alternate Phase of Spin_Clk)
762
Programming Examples
763
Register Map
765
Register Description
766
USB Device Controller (USBD)
785
Overview
785
Features
785
Block Diagram
786
Basic Configuration
786
Functional Description
786
Figure 6.17-1 USB Block Diagram
786
Figure 6.17-2 NEVWK Interrupt Operation Flow
787
Figure 6.17-3 Endpoint SRAM Structure
788
Figure 6.17-4 Setup Transaction Followed by Data in Transaction
789
Figure 6.17-5 Data out Transfer
789
Register Map
790
Register Description
792
USB 1.1 Host Controller (USBH)
808
Overview
808
Features
808
Block Diagram
809
Figure 6.18-1 USB 1.1 Host Controller Block Diagram
809
Basic Configuration
810
Functional Description
810
Register Map
812
Register Description
814
USB On-The-Go (OTG)
845
Overview
845
Features
845
Block Diagram
846
Basic Configuration
846
Functional Description
846
Figure 6.19-1 USB OTG Block Diagram
846
Figure 6.19-2 USB Device Mode
847
Figure 6.19-3 USB Host Mode
847
Register Map
849
Register Description
850
Controller Area Network (CAN)
858
Overview
858
Features
858
Basic Configuration
858
Block Diagram
858
Functional Description
859
Figure 6.20-1 CAN Peripheral Block Diagram
859
Test Mode
861
Figure 6.20-2 CAN Core in Silent Mode
861
Figure 6.20-3 CAN Core in Loop Back Mode
862
Figure 6.20-4 CAN Core in Loop Back Mode Combined with Silent Mode
862
CAN Communications
863
Figure 6.20-5 Data Transfer between Ifn Registers and Message
865
Table 6-36 Initialization of a Transmit Object
867
Table 6-37 Initialization of a Receive Object
868
Figure 6.20-6 Application Software Handling of a FIFO Buffer
870
Figure 6.20-7 Bit Timing
872
Table 6-38 CAN Bit Time Parameters
872
Figure 6.20-8 Propagation Time Segment
873
Figure 6.20-9 Synchronization on "Late" and "Early" Edges
875
Figure 6.20-10 Filtering of Short Dominant Spikes
876
Figure 6.20-11 Structure of the CAN Core's CAN Protocol Controller
877
Register Map
881
Table 6-39 CAN Register Map for each Bit Function
886
Register Description
887
Table 6-40 Last Error Code
891
Table 6-41 Source of Interrupts
894
Table 6-42 IF1 and IF2 Message Interface Register
897
Table 6-43 Structure of a Message Object in the Message Memory
911
CRC Controller (CRC)
922
Overview
922
Features
922
Block Diagram
922
Figure 6.21-1 CRC Generator Block Diagram
922
Basic Configuration
923
Functional Description
923
Register Map
924
Register Description
925
Enhanced 12-Bit Analog-To-Digital Converter (EADC)
930
Overview
930
Features
930
Block Diagram
931
Basic Configuration
931
Figure 6.22-1 ADC Converter Block Diagram
931
Operation Procedure
932
Figure 6.22-2 Sample Module 0~3 Block Diagram
932
Figure 6.22-3 Sample Module 4~15 Block Diagram
933
Figure 6.22-4 Sample Module 16~18 Block Diagram
933
Figure 6.22-5 EADC Clock Control
934
Figure 6.22-6 Example ADC Conversion Timing Diagram, N=0~18
935
Figure 6.22-7 Sample Module Conversion Priority Arbitrator Diagram
936
Figure 6.22-8 Specific Sample Module A/D EOC Signal for ADINT0~3 Interrupt
937
Figure 6.22-9 STADC De-Bounce Timing Diagram
938
Figure 6.22-10 PWM-Triggered ADC Start Conversion
938
Figure 6.22-11 External Triggered ADC Start Conversion
938
Figure 6.22-12 Conversion Start Delay Timing Diagram
939
Figure 6.22-13 A/D Extend Sampling Timing Diagram
940
Figure 6.22-14 A/D Conversion Result Monitor Logics Diagram
941
Table 6-44 EADC Differential Model Channel Table
941
Figure 6.22-15 A/D Controller Interrupts
942
Register Map
943
Register Description
946
Digital to Analog Converter (DAC)
973
Overview
973
Features
973
Block Diagram
973
Figure 6.23-1 Digital-To-Analog Converter Block Diagram
973
Basic Configuration
974
Functional Description
974
Figure 6.23-2 Data Holding Register Format
974
Figure 6.23-3 DAC Conversion Started by Software Write Trigger
975
Figure 6.23-4 DAC Conversion Started by Hardware Trigger Event
975
Figure 6.23-5 DAC PDMA Underrun Condition Example
976
Figure 6.23-6 DAC Continuous Conversion with Software PDMA Mode
977
Figure 6.23-7 DAC Interrupt Source
977
Register Map
978
Register Description
979
Analog Comparator Controller (ACMP)
986
Overview
986
Features
986
Block Diagram
987
Figure 6.24-1 Analog Comparator Block Diagram
987
Basic Configuration
988
Functional Description
988
Figure 6.24-2 Comparator Controller Interrupt Sources
988
Figure 6.24-3 Comparator Hysteresis Function
989
Figure 6.24-4 Comparator Reference Voltage Block Diagram
989
Register Map
990
Register Description
991
Application Circuit
998
Electrical Characteristics
999
Package Dimensions
1000
LQFP 100L (14X14X1.4 MM Footprint 2.0 MM)
1000
LQFP 64L (10X10X1.4 MM Footprint 2.0 MM)
1001
LQFP 64L (7X7X1.4 MM Footprint 2.0 MM)
1002
LQFP 48L (7X7X1.4Mm Footprint 2.0Mm)
1003
Revision History
1004
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