Displayport Interface Signals; Hdmi Interface Signals - DFI AL701 User Manual

LVDS_B_CLK+_R 120 O LVDS
(option eDP1_AUX+)
LVDS_B_CLK-_R 122
(option eDP1_AUX-)
LVDS_DDC_CLK_R 127 I/O OD CMOS 3.3V/3.3V
(option eDP1_DDC_CLK)
LVDS_DDC_DATA_R 125 I/O OD CMOS 3.3V/3.3V
(option eDP1_DDC_DAT)
DDI1_HPD#_C 128 I/O OD CMOS 3.3V/3.3V
eDP_HPD#_C 126 I/O OD CMOS 3.3V/3.3V

DisplayPort Interface Signals

Signal Pin# Pin Type
DDI0_3N 133 O PCIE
DDI0_3P 131
DDI0_2N 145 O PCIE
DDI0_2P 143
DDI0_1N 139 O PCIE
DDI0_1P 137
DDI0_0N 151 O PCIE
DDI0_0P 149
DPI0_AUX_C_N 140 I/O PCIE
DPI0_AUX_C_P 138
DDI0_DP_HPD 154 I CMOS

HDMI Interface Signals

Signal Pin# Pin Type
DDI0_3N 133 O TMDS
DDI0_3P 131
DDI0_2N 145 O TMDS
DDI0_2P 143
User's Manual | AL701
LVDS
PU 2.2K to 3.3V
PU 2.2K to 3.3V
NC
NC
Pwr Rail /Tolerance AL701
DP AC Coupling capacitor
DP AC Coupling capacitor
DP AC Coupling capacitor
DP AC Coupling capacitor
DP AC Coupling capacitor
3.3V/3.3V PU 10K to 3.3V
Pwr Rail /Tolerance AL701
TMDS AC coupled off Module
TMDS AC coupled off Module
Connect to LVDS connector
Connect to DDC clock of LVDS panel
Connect to DDC clock of LVDS panel
Carrier Board
Connect AC Coupling Capacitors 0.1uF to Device, PU
100K to 3.3V
Connect AC Coupling Capacitors 0.1uF to Device, PD
100K to GND
Carrier Board
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
HARDWARE INSTALLATION
LVDS secondary channel differential pair clock lines.
Display Port secondary auxiliary channel.
Primary functionality is DisplayID DDC clock line used for LVDS flat
panel detection. If primary functionality is not used it can be as General
Purpose I²C bus clock line.
Primary functionality DisplayID DDC data line used for LVDS flat panel
detection. If primary functionality is not used it can be as General
Purpose I²C bus data line.
Control clock signal for external SSC clock chip. If the primary
functionality is not used, it can be used as an embedded DisplayPort
secondary Hotplug detection.
Control data signal for external SSC clock chip. If the primary functionality
is not used, it can be used as an embedded DisplayPort primary Hotplug
detection.
Description
DisplayPort differential pair lines lane 3.
DisplayPort differential pair lines lane 2.
DisplayPort differential pair lines lane 1.
DisplayPort differential pair lines lane 0.
Auxiliary channel used for link management and device control.
Differential pair lines.
Hot plug detection signal that serves as an interrupt request.
Description
TMDS differential pair clock lines.
TMDS differential pair lines lane 0.
Chapter 2
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