Lpc Interface Signals; Spi Interface Signals - DFI AL701 User Manual

DDI0_1N 139 O TMDS
DDI0_1P 137
DDI0_0N 151 O TMDS
DDI0_0P 149
DDI0_DDC_SCL_C 152 I/O OD CMOS3.3V/3.3V
DDI0_DDC_SDA_C 150 I/O OD CMOS3.3V/3.3V
DDI0_HDMI_HPD 153 I CMOS

LPC Interface Signals

Signal Pin# Pin Type
LPC_AD[0..3] 185-188 I/O CMOS
LPC_FRAME- 190 I/O CMOS
NC 192 I/O CMOS
CLK1_25M_CB 189 I/O CMOS
LPC_SERIRQ 191 I/O CMOS

SPI Interface Signals

Signal Pin# Pin Type
SPI_MOSI_D0_3VSB 199 O CMOS
SPI_MISO_D1_3VSB 201 I CMOS
SPI_CLK_3VSB 203 O CMOS
SPI_CS0_CB 200 O CMOS
NC 202 O CMOS
User's Manual | AL701
TMDS AC coupled off Module
TMDS AC coupled off Module
PU 2.2K to 3.3V
PU 2.2K to 3.3V
3.3V/3.3V PU 10K to 3.3V
Pwr Rail /Tolerance AL701
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V NC
3.3V/3.3V
3.3V/3.3V
Pwr Rail /Tolerance AL701
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V
3.3V/3.3V NC
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
Connect AC Coupling Capacitors 0.1uF to Device
Carrier Board
Connect to LPC device
Connect to LPC device
Connect to LPC device
Connect to LPC device
Carrier Board
Connect a series resistor to Carrier Board SPI Device SI
pin
Connect a series resistor to Carrier Board SPI Device
SO pin
Connect a series resistor to Carrier Board SPI Device
SCK pin
Connect a series resistor to Carrier Board SPI Device
CS# pin
HARDWARE INSTALLATION
TMDS differential pair lines lane 1.
TMDS differential pair lines lane 2.
DDC based control signal (clock) for HDMI device.
Note: Level shifters must be implemented on the carrier board for this
signal in order to be compliant with the HDMI Specification.
DDC based control signal (data) for HDMI device.
Note: Level shifters must be implemented on the carrier board for this
signal in order to be compliant with the HDMI Specification
Hot plug detection signal that serves as an interrupt request.
Description
Multiplexed Command, Address and Data.
General purpose input/output [0..3]
LPC frame indicates the start of a new cycle or the termination of a
broken cycle.
General purpose input/output 5.
LPC DMA request.
General purpose input/output 7.
LPC clock.
General purpose input/output 4.
Serialized Interrupt.
General purpose input/output 6.
Description
Master serial output/Slave serial input signal. SPI serial output data from
Qseven module to the SPI device.
Master serial input/Slave serial output signal. SPI serial input data from
the SPI device to Qseven module.
SPI clock output.
SPI chip select 0 output.
SPI Chip Select 1 signal is used as the second chip select when two
devices are used. Do not use when only one SPI device is used.
Chapter 2
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