LG DRD-820B Manual page 24

Pin No. Pin Name
59 IO0
60 IO1
61 IO2
62 IO3
63 /DMOUT
64 /CKSE
65 /DACT
66 TESIN
67 TESIO1
68 VSS
69 PXI
70 PXO
71 VDD
72 XVSS
73 XI
74 XO
75 XVDD
76 DVDD
77 RO
78 DVSS
79 DVR
80 LO
81 DVDD
82 TEST1
83 TEST2
84 TEST3
85 BUSO
86 BUS1
87 BUS2
88 BUS3
89 VDD
90 VSS
91 BUCK
92 /CCE
93 TEST4
94 /TSMOD
I/O
I/O General I/O Port
Convertable to input port and output port by a command
In input port mode, readable the terminal condition(H/L) to read command
In output port mode, be able to control the terminal condition(H/L/Hi-Z) to command
I It selects the mode output 2 state PWM of disc EQ at IO 2,
Pin - and 2 state PWM of Feed EQ at IO 0, Pin - .
3
Active "L"
I X-TAL selet terminal
It is °∞H°± on 16.9344MHz, "L" on 33.8688MHz
I TEST terminal
Normally, it is opened.
I Test input, Normally, fixed "L"
I/O Test in/output, Normally, fixed "L"
- Digital GND
I Clock OSC circuit input for DSP
Normally, fixed "L"
O Clock oscillating circuit output for DSP
- Digital VDD
- System Clock oscillating circuit GND
I System Clock oscillating circuit input
O System Clock oscillating circuit output
- VDD for System Clock OSC
- VDD for D/A Convertor
O R-CH Data positive output
- GND for D/A Convertor
- D/A Convertor reference voltage
O L-CH DATA positive output
- VDD for D/A Convertor
I TEST terminal
Normally, It is opened.
I TEST terminal
Normally, It is opened.
I TEST terminal
Normally, It is opened.
I/O DATA in/output for µ-COM Interface
I/O
I/O
I/O
- Digital VDD
- Digital GND
I Clock Input for µ-COM Interface
I Chip Enable signal input for µ -COM Interface, 0~3 BUS is active in "L" mode
I TEST terminal
Normally, It is opened.
I Local Test Mode Select terminal
Description
1
Remark
Enhanced Pull-Up resistor
Enhanced Pull-Up resistor
Enhanced Pull-Up resistor
Analog Input
Analog Input
Enhanced Pull-Up resistor
Enhanced Pull-Up resistor
Enhanced Pull-Up resistor
Schmitt Input
CMOS Port
Schmitt Input
Schmitt Input
Enhanced Pull-Up resistor
Enhanced Pull-Up resistor
29