LG DRD-820B Manual page 27

IC401 (TC90A41AF)
Pin Description
Pin No. Pin Name
I/O
1 DPCKI IN
2 DVDD3
3 SVCKI
IN
4 SVCKO
OUT Servo reference clock output (oscillating circuit input)
5 DVSS
6 DVDD3
7 N.C.
8 HDWT
IN
9 HDRD IN
10 HCEN
IN
11 HD0
I/O
12 HD1
I/O
13 HD2 I/O
14 HD3
I/O
15 HD4
I/O
16 HD5
I/O
17 HD6
I/O
18 HD7 I/O
19 DVSS
20 DVDD5
21 HINT
OUT MPU interrupt signal ("L" is in the interrupt mode)
22 HA0 IN
23 HA1
IN
24 PLCK
I/O
25 ED0
26 ED1
27 ED2
28 ED3
29 ED4
30 ED5
31 ED6
32 ED7
33 TEST
IN
34 PDON
OUT PLL phase error signal output (-)
35 PDOP OUT PLL phase error signal output (+)
36 RLLD
OUT Output as a result of RLL detection
37 LPFN
IN
38 LPFO
OUT AMP output for PLL loop filter
39 VCOF
OUT VCO Filter terminal
40 SLCO
OUT Reference voltage output of Enhanced comparator
32
Signal management reference clock input
- Digital VDD3 (3.3V)
Servo reference clock input (oscillating circuit input)
- Digital GND (0V)
- Digital DV (3.3V)
DD3
- Not use.
MPU write signal
MPU read signal
MPU chip select
MPU Data BUS
MPU Data BUS
MPU Data BUS
MPU Data BUS
MPU Data BUS
MPU Data BUS
MPU Data BUS
MPU Data BUS
- Digital GND (0V)
- Digital DV (5V)
DD5
MPU Address
MPU Address
Read CH clock I/O port
- Not use.
-
-
-
-
-
-
-
For production adjustment
(-) Input of AMD for PLL loop filter
Description
Remarks
0.5~3.3Vpp
Enhanced feedback resistor
Logic cell
3.3V-I/F
Enhanced feedback resistor
For Logic cell
For Logic cell
open
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
For I/O cell
For I/O cell
OPEN DRAIN
TTL level
TTL level
OPEN
Set to "L"