LG DRD-820B Manual page 29

Pin No. Pin Name
82 SD4
83 DVSS
84 DVDD3
85 SD3
86 SD2
87 SD1
88 SD0
89 SERR OUT MPEG DATA Reliability Flag (Data Error= "L")
90 SBGN
91 SENB
92 SDCK
93 DVSS
94 SREQ
95 RSTN
96 DVDD3
97 STDA
98 STCK
99 UPWM
100 DVSS
* Digital IN/OUT terminal as not described in remarks is CMOS Level (5V).
34
I/O
OUT MPEG DATA output
- Digital GND (0V)
- DV , Digital (3.3V)
DD3
OUT MPEG DATA output
OUT MPEG DATA output
OUT MPEG DATA output
OUT MPEG DATA output
OUT MPEG output Sector Synchronizing signal (Sector top= "L" )
OUT MPEG DATA Active Flag (Active mode= "L")
OUT MPEG DATA Transfer Clock
- Digital GND (0V)
IN MPEG Data demand Flag (demand= "L" )
IN H/W Reset input (Reset= "L" )
- Digital DV (3.3V)
DD3
OUT Operating Condition Monitor Data (SDCK Synchronizing output)
OUT Operating Condition Monitor Synchronizing signal (Data Top Bit="L")
OUT Genearl purpose PWM output
- Digital GND (0V)
Description Remarks
For Logic cell
For Logic cell
For Logic cell
TTL level
For Logic cell
PWM Combination
PWM Combination
4mA, 5V-I/F
For Logic cell