LG DRD-820B Manual page 28

Pin No. Pin Name
I/O
41 AVSS
42 AVR
OUT Analog reference Voltage (1.65V) for non-PLL
43 VRC
44 PVR
OUT Analog reference voltage (1.65V) for PLL
45 AVDD
46 RVR2
47 RVDD
48 RFIN
IN
49 RVSS
50 RVR1
51 DVR
IN
52 DMO OUT Disc EQ output for DVD (3 state PWM+Hi-Z)
53 RASN
OUT External RAM column address selection (negative logic)
54 CASN
OUT External RAM rank address selection (negative logic)
55 MOEN
OUT External RAM output allowance signal
56 MWEN
OUT External RAM read/write select
57 DVSS
58 DVDD3
59 MA9
OUT External RAM Address
60 MA8
OUT External RAM Address
61 MA7
OUT External RAM Address
62 MA6
OUT External RAM Address
63 MA5 OUT External RAM Address
64 MA4
OUT External RAM Address
65 MA3
OUT External RAM Address
66 MA2
OUT External RAM Address
67 MA1
OUT External RAM Address
68 MA0
OUT External RAM Address
69 DVSS
70 DVDD5
71 MD7
I/O
72 MD6
I/O
73 MD5
I/O
74 MD4
I/O
75 MD3
I/O
76 MD2 I/O
77 MD1
I/O
78 MD0
I/O
79 SD7
OUT MPEG DATA output
80 SD6
OUT MPEG DATA output
81 SD5
OUT MPEG DATA output
- Analog GND (0V)
- Resistor divide point electrical potential (Analog reference electrical potential:1.65V)
- Analog AV (3.3V)
DD
- Secondary reference voltage (for condenser connection)
- Exclusive power supply terminal (3.3V)
RF signal input
- GND (0V)
- First reference voltage (for condenser connection)
DMO reference electrical potential (1.65V)
- Digital GND (0V)
- DV , Digital (3.3V)
DD3
- Digital GND (0V)
- DV , Digital (5V)
DD5
External RAM DATA Bus
External RAM DATA Bus
External RAM DATA Bus
External RAM DATA Bus
External RAM DATA Bus
External RAM DATA Bus
External RAM DATA Bus
External RAM DATA Bus
Description Remarks
For Logic cell
For Logic cell
For I/O cell
For I/O cell
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
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