Relay Control; Relay Power Control; Power-On Safeguard; Troubleshooting - Keithley 7011-S Instruction Manual

Servfce Information
5.5.3 Relay control
Card relays are controlled by serial data &nmnitted
via the relay DATA line. A total of five bytes for each
card are shifted in serial fashion into latches located in
the card relay driver ICs. The serial data is clocked in
by the CLK line. As data overflows one register, it is fed
out the Q'S line of the register down the chain.
Once all five bytes have shifted into the card, the
STROBE line is set high to latch the relay information
into the Q outputs of the relay drivers, and the appro-
priate relays are energized (assuming the driver out-
puts are enabled, as discussed below). Note that a relay
driver output goes low to energize the corresponding
Rhy.
5.5.4 Relay power control
A relay power control circuit, made up of U106, U107,
QlCO, QlOl, and associated components, keeps power
dissipated in relay coils at a minimum, thus reducing
possible problems caused by thermal EM%.
During steady-state operation, the relay supply~ volt-
age, +V, is regulated to +3.5V to minimize coil power
dissipation. When a relay is first closed, the STROBE
p&e applied to WC6 changes the parameters of there-
lay supply voltage regulator, QlOO, allowing the relay
supply voltage, +V, to rise to +5.7V for about lC0msec.
This brief voltage rise ensures that relays close as
quickly as possible. After the 1OOmsec period. has
elapsed, the relay supply voltage (+v) drops back
down to its nominal steady-state value of +3X
5.5.5 power-on safeguard
NOTE
The power-on safeguard circuit dis-
cussed below is actually located on the
digital board in the Model 7001 main-
frame.
A power-on safeguard &xit, made up of U114 (a D-
type tlip-flop) and associated components ensures that
relays do not randomly energize on power-up and
power-down. This circuit disables all relays (all relays
are open) during power-up and power-down periods.
The PRESET line on the D-type flip-flop is controlled
by the 68302 micmprocessor, while the CLK line of the
D-type tllp-flop is controlled by a VIA port line on the
68302
processor. The Q output of the flip-flop drive
each switch card relay driver IC enable pin (UlO&
u104, pin 8).
When the 68302 microprocessor is in the reset mode,
the flip-flop PRESET line is held low, and Q out imme-
diately goes high, disabling aU relays (relay driver IC
enable pins are high, disabling the relays). After the re
set condition elapses (=ZOOmec), PRESET goes high
while Q out stays high. When the first valid STROBE
pulse occurs, a low logic level is clocked into the D
type flip-flop, setting Q out low and enabling all relay
drivers simultaneously. Note that Q out stays low, (en-
abling relay drivers) until the 68302 processor goes into
a reset condition.
5.6 Troubleshooting
5.6.1 Troubleshooting equipment
Table 5-5 summarizes recommended equipment for
troubleshooting the Model 7011.
Tab/e 5-5
Recommended troubleshooting equipment
Manufacturer
Description
and model
Application
Multimeter Keithley 196
Measure DC voltages
oscilloscope TEK 2243
View logic waveforms
5-17