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5.5
Principles of operation
The following paragraphs discuss the basic operating
principles for the Model 7011, and can be used as an aid
in troubleshooting the card. The schematic drawing of
the card is shown on drawing number 7011-106, locat-
ed at the end of Section 6.
5.5.1 Block diagram
Figure 5-8 shows a simplilied block diagram of the
Model 7011. Key elements include the relay drivers
and relays, as well as the ROM, which contains card ID
and conQuration information. These various elements
are discussed in the following paragraphs.
5.5.2 ID data circuits
Upon power-up, card identification information
from
each card is read by the mainframe. This ID data in-
dudes such information as card ID, hardware settling
time, and relay con&uration
information.
ID data is contained within
an on-card EEPROM
W105). In order to read this information, the sequence
described below is performed on power-up.
1. The IDDATA line (pin 6 of U105) is set
from
high to
low while the IDCLK line (pin 5 of U105) is held
high. This action initiates a start command to the
ROM to kmsmit data serially to the mainframe
(Figure 5-9).
2. The mainframe sends the ROM address location to
be read over the IDDATA line. The ROM then
transmits an acknowledge signal back to the main-
frame, and it then transmits data at that location
back to the mainframe CFigure 5-10).
3.
The mainfkame then transmits an acknowledge
signal, indicating that it requires more data. The
ROM will then sequentially transmit data after
each acknowledge signal it receives.
4.
Once all data is received, the mainframe sends a
stop co mmand, which is a low-to-high transition
of the IDDATA line with the IDCLK line held high
(see Figure 5-9).
Relays
3.5V (Steady State)
I
15.7 (= 100 msec during
relay achration)
To Mainframe
ROM
u105
I User connections
4
Relay
Power
Control
0100, QlOl
U106, u107
+6V, +14.6V
Figure 5-8
Model 7011 block diagram
5-l 5
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Table of Contents
Troubleshooting
