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Optional Configurations
5
Optional Configurations
5.1
Mixer Outputs
The mixer outputs can be fed directly to the transformers and to ports J5 and J9. This can be useful for
measuring the RF performance of the mixer itself without the PGAs or filters. This feature is implemented
by toggling the BUF Pwd to Off.
5.2
Common-Mode Voltage
The common-mode voltage is set to a static 1.5 V by a resistor-divider network. Note, the common-mode
voltage is shifted if the input supply is not 5 V. Alternatively, this can be controlled via a potentiometer by:
•
Removing R17, R18
•
Placing 0-Ω jumper at R19
•
Adjusting potentiometer R20.
When cascading the device with an ADC it may be desirable to feed the common-mode voltage from the
ADC to the device. This can be accomplished by:
•
Removing shunt at W3
•
Placing ADC common-mode voltage at TP9
5.3
DC Offset Control
The easiest way to manage the dc offset control is to use the Auto Cal function. This is accomplished by
setting Auto Cal to Auto and toggling the Auto Cal En switch. Monitor the dc offset voltage at TP2 (IA) and
TP7 (IB) and between TP10 (QA) and TP12 (QB) and verify that the procedure worked sufficiently.
The detection filter is typically set to 1 kHz and the clock divider is set to 1024. With this configuration the
dc offset calibration is most accurate and can be enabled with the RF signal present. If the RF input signal
is disabled during the auto-cal procedure, then the detection filter bandwidth can be 10 MHz and the clock
divider reduced to a value of 16. Other combinations of detector filter and clock divider are possible,
depending on accuracy required and convergence time required.
Alternatively, this function can be accomplished by manually programming the I and Q DAC registers.
Toggle Auto Cal to Manual. Adjust the I and Q DAC registers on the GUI directly. Monitor the dc offset
values at TP2 (IA) and TP7 (IB) and between TP10 (QA) and TP12 (QB) until the dc offset is as close to 0
mV as possible.
5.4
Analog Gain Control
The device is equipped with three bits to control the PGA gain to facilitate an analog gain-control loop that
does not require the use of SPI. To use this function, set the EN_FastGain to ON. Then adjust for the gain
through the binary combination of bits B0, B1, B2 that can be toggled at DIP switch SW1. For example, if
the BB gain is set to 24 and the binary bits are set to b101, then the equivalent gain setting is 24 – 5 = 19.
If the GainSelect is set to 2×, then the equivalent gain setting for the previous example is
24 – 2 × 5 = 14.
5.5
Analog Device Disable
The TRF3711xx can be disabled by removing the jumper at W2.
6
Schematics
Schematics for the TRF3711xxEVM are appended to this document.
8
TRF3711xxEVM
Copyright © 2010, Texas Instruments Incorporated
SLWU069B – February 2010 – Revised November 2010
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