Digital Equipment Digital AlphaStation 200 Series Technical Information page 9

Instruction Translation Buffer IS (ITBIS) Register ....................................................... 11-3
Processor Status (PS) Register ...................................................................................... 11-4
Exception Summary (EXC_SUM) Register .................................................................. 11-4
PAL Base Address (PAL_BASE) Register ................................................................... 11-4
Hardware Interrupt Request Register (HIRR) ............................................................... 11-4
Software Interrupt Request Register (SIRR) ................................................................. 11-5
Asynchronous Trap Request Register (ASTRR) ........................................................... 11-5
Hardware Interrupt Enable Register (HIER) ................................................................. 11-5
Software Interrupt Enable Register (SIER) ................................................................... 11-6
AST Interrupt Enable Register (ASTER)...................................................................... 11-6
Serial Line Transmit Register (SL_XMIT) ................................................................... 11-6
Translation Buffer Control (TB_CTL) Register ............................................................ 11-6
Data Translation Buffer Page Table Entry Register (DTB_PTE) .................................. 11-7
Data Translation Buffer Page Table Entry Temporary (DTB_PTE_TEMP) Register .... 11-7
Memory Management Control and Status Register (MM_CSR).................................... 11-7
Virtual Address (VA) Register...................................................................................... 11-7
Data Translation Buffer ZAP (DTBZAP) Register........................................................ 11-7
Data Translation Buffer ASM (DTBASM) Register...................................................... 11-7
Data Translation Buffer Invalidate Single (DTBIS) Register ........................................ 11-7
Flush Instruction Cache (FLUSH_IC) Register............................................................. 11-7
Flush Instruction Cache ASM (FLUSH_IC_ASM) Register.......................................... 11-8
Abox Control Register.................................................................................................. 11-8
Alternate Processor Mode (ALT_MODE) Register....................................................... 11-8
Cycle Counter (CC) Register........................................................................................ 11-8
Cycle Counter Control (CC_CTL) Register .................................................................. 11-9
Bus Interface Unit Control (BIU_CTL) Register .......................................................... 11-9
Data Cache Status (DC_STAT) Register ...................................................................... 11-9
Cache Status (C_STAT) Register ................................................................................. 11-9
Bus Interface Unit Status (BIU_STAT) Register......................................................... 11-10
Bus Interface Unit Address (BIU_ADDR) Register .................................................... 11-10
Fill Address (FILL_ADDR) Register.......................................................................... 11-10
Fill Syndrome (FILL_SYNDROME) Register ............................................................ 11-10
Backup Cache Tag (BC_TAG) Register ..................................................................... 11-11
Cache and Memory Control CSRs..................................................................................... 11-11
General Control Register ............................................................................................ 11-12
Error and Diagnostic Status Register .......................................................................... 11-12
Tag Enable Register ................................................................................................... 11-13
Error Low Address Register ....................................................................................... 11-13
Error High Address Register....................................................................................... 11-13
LDxL Low Address Register ...................................................................................... 11-13
LDxL High Address Register ..................................................................................... 11-14
Bankset 0-8 Base Address Registers ........................................................................... 11-14
Bankset 0-7 Configuration Registers .......................................................................... 11-14
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