Digital Equipment Digital AlphaStation 200 Series Technical Information page 80

Addressing
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Read prefetching is allowed in this space; extra reads have no side effects. The CPU
does not specify a longword address on read transactions; it only specifies a quadword
address. Therefore, reads in this space are always done as a quadword read with a
burst length of two on the PCI.
Addresses are generated in dense space as follows:
CPU address A<31:5> is directly sent out on PCI address bits AD<31:5>.
On read transactions, PCI address AD<4:3> is generated from cpuCWMask<1:0>, PCI
address <2> is always 0.
On write transactions, PCI address <4:2> is generated from cpuCWMask<7:0>. If the
lower longword is to be written, PCI address <2> is 0; if the lower longword is masked out
and the upper longword is to be written, PCI address <2> is 1. The number of longwords
written on the PCI is directly obtained from cpuCWMask<7:0>. Any combination of
cpuCWMask<7:0> is allowed by the core logic chipset.
__________________________NOTE ____________________________
If the cache line written by the processor has holes, that is, if some of the
longwords have been masked out, the corresponding transfer is still performed
on the PCI with disabled byte enables. Downstream bridges must be able to
deal with completely disabled byte enables on the PCI during write transactions.
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