Digital Equipment Digital AlphaStation 200 Series Technical Information page 5

3 Addressing
Overview .............................................................................................................................. 3-1
Address Diagram................................................................................................................... 3-2
Cacheable Memory Space: 0 0000.0000-0 FFFF.FFFF.......................................................... 3-3
Noncacheable Memory Space:1 0000.0000-1 FFFF.FFFF ..................................................... 3-4
First Two GBytes of Noncacheable Space ...................................................................... 3-4
Cache/Memory Controller .............................................................................................. 3-5
PCI Bridge Registers ...................................................................................................... 3-7
PCI Sparse I/O Space ..................................................................................................... 3-8
Embedded ISA Device Addresses.......................................................................... 3-12
AlphaStation 200 Series System Sound Card ......................................................... 3-14
Configuration Cycles.................................................................................................... 3-15
PCI Sparse Memory Space .................................................................................................. 3-16
PCI Dense Memory Space................................................................................................... 3-19
I/O Device View of I/O Space............................................................................................. 3-21
4 I/O Programming
Overview .............................................................................................................................. 4-1
Accessing Flashbus Devices.................................................................................................. 4-1
Flashbus Offsets ............................................................................................................. 4-3
Access Procedure ........................................................................................................... 4-3
Keyboard and Mouse Controller............................................................................................ 4-4
TOY...................................................................................................................................... 4-5
Super I/O Chip ...................................................................................................................... 4-6
Disabling Interrupts............................................................................................................... 4-6
5 DMA
Overview .............................................................................................................................. 5-1
ISA DMA Channels .............................................................................................................. 5-1
6 Hardware Interrupts
Overview .............................................................................................................................. 6-1
Interrupts............................................................................................................................... 6-1
IRQ0: CPU Bus and Parity Errors................................................................................... 6-2
IRQ2: Device Interrupts ................................................................................................. 6-3
IRQ3: NMI (Nonmaskable Interrupt).............................................................................. 6-3
IRQ4: Interval Timer Interrupt ....................................................................................... 6-3
IRQ5: HALTREQ .......................................................................................................... 6-3
Interrupt Inputs............................................................................................................... 6-4
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