Texas Instruments TPS65917-Q1 Technical Reference Manual
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Texas Instruments TPS65917-Q1 Technical Reference Manual

Texas Instruments TPS65917-Q1 Technical Reference Manual

Integrated power-management integrated circuit
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TPS65917-Q1 Register Map
Technical Reference Manual
Literature Number: SLVUAH1C
June 2015 – Revised April 2017

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Summary of Contents for Texas Instruments TPS65917-Q1

  • Page 1 TPS65917-Q1 Register Map Technical Reference Manual Literature Number: SLVUAH1C June 2015 – Revised April 2017...
  • Page 2 Register Address Mapping This document describes the register mapping of the TPS65917-Q1 device. The operation of the IC is described in the device data sheet, TPS65917-Q1 Power Management Unit (PMU) for Processor.
  • Page 3 SLVUAH1C – June 2015 – Revised April 2017 Register Physical Address Register Module Base Address and Size Table 2-1 lists the base address and address space for the TPS65917-Q1 device functional register modules. Table 2-1. TPS65917-Q1 Function Register Module Name and Base Address Module Name...

  • Page 4: Table Of Contents

    Section 3.1.6 Voltage to apply to the resource when it is not a DVS force command (OTP_Config). RESET register domain: SWORST Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 5: Smps1_Force

    When 1: SMPS1_VOLTAGE.VSEL voltage is applied (default) CMD is effective if SMPS1_CTRL.ROOF_FLOOR_EN='0' VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register (page1). SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 6: Smps1_Voltage

    Note: For Dual-phase mode, RANGE=1 (1V to 3.3V) is not supported. VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register (page1). Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 7: Smps2_Force

    When 1: SMPS2_VOLTAGE.VSEL voltage is applied (default) CMD is effective if SMPS2_CTRL.ROOF_FLOOR_EN='0' VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register. SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 8: Smps2_Voltage

    Note:RANGE bit is RO when SMPS2 is ON, RANGE bit is RW when SMPS2 is OFF VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register. Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 9: Smps3_Force

    When 1: SMPS3_VOLTAGE.VSEL voltage is applied (default) CMD is effective if SMPS3_CTRL.ROOF_FLOOR_EN='0' VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register (page1). SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 10: Voltage To Apply To The Resource When It Is Not A Dvs Force Command (Otp_Config)

    Note:RANGE bit is RO when SMPS3 is ON, RANGE bit is RW when SMPS3 is OFF VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register (page1). Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 11 These registers will retain their content as long as VRTC is active. RESET register domain: POR SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 12 RESET register domain: POR Figure 3-7. BACKUP0 Register BACKUP R/W-0h Table 3-9. BACKUP0 Register Field Descriptions Field Type Reset Description BACKUP Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 13 RESET register domain: POR Figure 3-8. BACKUP1 Register BACKUP R/W-0h Table 3-10. BACKUP1 Register Field Descriptions Field Type Reset Description BACKUP SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 14 RESET register domain: POR Figure 3-9. BACKUP2 Register BACKUP R/W-0h Table 3-11. BACKUP2 Register Field Descriptions Field Type Reset Description BACKUP Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 15 RESET register domain: POR Figure 3-10. BACKUP3 Register BACKUP R/W-0h Table 3-12. BACKUP3 Register Field Descriptions Field Type Reset Description BACKUP SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 16 RESET register domain: POR Figure 3-11. BACKUP4 Register BACKUP R/W-0h Table 3-13. BACKUP4 Register Field Descriptions Field Type Reset Description BACKUP Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 17 RESET register domain: POR Figure 3-12. BACKUP5 Register BACKUP R/W-0h Table 3-14. BACKUP5 Register Field Descriptions Field Type Reset Description BACKUP SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 18 RESET register domain: POR Figure 3-13. BACKUP6 Register BACKUP R/W-0h Table 3-15. BACKUP6 Register Field Descriptions Field Type Reset Description BACKUP Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 19 RESET register domain: POR Figure 3-14. BACKUP7 Register BACKUP R/W-0h Table 3-16. BACKUP7 Register Field Descriptions Field Type Reset Description BACKUP SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 20: Reset Register Domain: Sworst

    Section 3.3.9 Voltage to apply to the resource when it is not a DVS force command (OTP_Config). RESET register domain: SWORST Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 21 RESET register domain: POR (excepted POWERGOOD_TYPE_SELECT which is under HWRST) 14Dh SMPS_PLL_CTRL SMPS PLL control register. Section 3.3.22 RESET register domain: HWRST SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 22: Reset Register Domain: Sworst

    MODE_ACTIVE SMPS1 (or SMPS12 in case of dual-phase) ACTIVE Mode 00: OFF (default) 01: Forced PWM 10: ECO 11: Forced PWM Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 23: Smps1_Force

    When 1: SMPS1_VOLTAGE.VSEL voltage is applied (default) CMD is effective if SMPS1_CTRL.ROOF_FLOOR_EN='0' VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 24: Smps1_Voltage

    ON, RANGE bit is RW when SMPS1 (or SMPS12 in case of dual-phase) is OFF Note: For Dual-phase mode, RANGE=1 (1V to 3.3V) is not supported. Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 25 0101011 = 0.87V/1.74V 1101011 = 1.51V/3.02V 0101100 = 0.88V/1.76V 1101100 = 1.52V/3.04V 0101101 = 0.89V/1.78V 1101101 = 1.53V/3.06V 0101110 = 0.9V/1.8V 1101110 = 1.54V/3.08V SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 26 0111100 = 1.04V/2.08V 1111100 = 1.65V/3.3V 0111101 = 1.05V/2.1V 1111101 = 1.65V/3.3V 0111110 = 1.06V/2.12V 1111110 = 1.65V/3.3V 0111111 = 1.07V/2.14V 1111111 = 1.65V/3.3V Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 27: Smps2_Ctrl

    01: Forced PWM 10: ECO 11: Forced PWM MODE_ACTIVE SMPS2 ACTIVE Mode 00: OFF (default) 01: Forced PWM 10: ECO 11: Forced PWM SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 28: Smps2_Force

    When 1: SMPS2_VOLTAGE.VSEL voltage is applied (default) CMD is effective if SMPS2_CTRL.ROOF_FLOOR_EN='0' VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register. Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 29: Smps2_Voltage

    Note:RANGE bit is RO when SMPS2 is ON, RANGE bit is RW when SMPS2 is OFF VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register. SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 30: Smps3_Ctrl

    01: Forced PWM 10: ECO 11: Forced PWM MODE_ACTIVE SMPS3 ACTIVE Mode 00: OFF (default) 01: Forced PWM 10: ECO 11: Forced PWM Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 31: Smps3_Force

    When 1: SMPS3_VOLTAGE.VSEL voltage is applied (default) CMD is effective if SMPS3_CTRL.ROOF_FLOOR_EN='0' VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register. SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 32: Voltage To Apply To The Resource When It Is Not A Dvs Force Command (Otp_Config)

    Note:RANGE bit is RO when SMPS3 is ON, RANGE bit is RW when SMPS3 is OFF VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register. Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 33: Reset Register Domain: Sworst

    01: Forced PWM 10: ECO 11: Forced PWM MODE_ACTIVE SMPS4 ACTIVE Mode 00: OFF (default) 01: Forced PWM 10: ECO 11: Forced PWM SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 34 Note:RANGE bit is RO when SMPS4 is ON, RANGE bit is RW when SMPS4 is OFF VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register. Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 35 01: Forced PWM 10: ECO 11: Forced PWM MODE_ACTIVE SMPS5 ACTIVE Mode 00: OFF (default) 01: Forced PWM 10: ECO 11: Forced PWM SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 36 Note:RANGE bit is RO when SMPS5 is ON, RANGE bit is RW when SMPS5 is OFF VSEL See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register. Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 37 01: Force Single Phase mode (for SMPS1 and SMPS2) 10: Force Multi Phase mode (for SMPS1 and SMPS2) - Prohibited under no-load condition SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 38 1: Pull-down is enabled when SPMS2 is in OFF state (default) SMPS1 0: Pull-down is disabled 1: Pull-down is enabled when SPMS1 is in OFF state (default) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 39 0: SMPS12 Thermal feature is not enabled 1: SMPS12 Thermal feature is enabled (default) Note: A unique Thermal Sensor is protecting SMPS1 and SMPS2 SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 40 0: SMPS12 Thermal measurement is below the limit (SMPS is functional) 1: SMPS12 Thermal measurement is over the limit (see specification) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 41 0: SMPS1 (or SMPS12 in Dual phase mode) is functional . No short detected (default) 1: SMPS1 (or SMPS12 in Dual phase mode) output is shorted SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 42 SMPS1 0: SMPS1 Negative Current comparator for measurement is not enabled 1: SMPS1 Negative Current comparator for measurement is enabled (default) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 43 0: SMPS1 line is enabled. The SMPS1 state is generated on POWERGOOD line (default) 1: SMPS1 line is masked. No SMPS1 state is generated on POWERGOOD line SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 44 POWERGOOD line 1: OVC_ALARM line is masked. No OVC_ALARM state is generated on POWERGOOD line (default) RESERVED RESERVED RESERVED RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 45 1: Bypass is enabled PLL_BYPASS_CLK Allow to bypass the 6x frequency clock 0: No Bypass (default) 1: Bypass is enabled RESERVED RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

  • Page 46: Reset Register Domain: Sworst

    Resources SLEEP/ACTIVE assignments table in the Data Manual for details). 163h LDO5_VOLTAGE LDO5 Voltage selection (OTP_Config) Section 3.4.10 RESET register domain: SWORST Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 47 17Eh LDO_SHORT_STATUS3 LDO short circuit status register #3 Section 3.4.16 RESET register domain: POR SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 48 0: OFF 1: ON RESERVED MODE_ACTIVE LDO1 ACTIVE Mode 0: OFF 1: ON This bit can be updated by power-up sequencer Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 49 011010 2,15V 111010 3,3V 011011 2,2V 111011 3,3V 011100 2,25V 111100 3,3V 011101 2,3V 111101 3,3V 011110 2,35V 111110 3,3V 011111 2,4V 111111 3,3V SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 50 0: OFF 1: ON RESERVED MODE_SLEEP LDO2 SLEEP Mode 0: OFF 1: ON RESERVED MODE_ACTIVE LDO2 ACTIVE Mode 0: OFF 1: ON Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 51 R/W-X Table 3-44. LDO2_VOLTAGE Register Field Descriptions Field Type Reset Description RESERVED VSEL See VSEL cross table showed in LDO1_VOLTAGE.VSEL register. SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 52 0: OFF 1: ON RESERVED MODE_SLEEP LDO3 SLEEP Mode 0: OFF 1: ON RESERVED MODE_ACTIVE LDO3 ACTIVE Mode 0: OFF 1: ON Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 53 R/W-X Table 3-46. LDO3_VOLTAGE Register Field Descriptions Field Type Reset Description RESERVED VSEL See VSEL cross table showed in LDO1_VOLTAGE.VSEL register. SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 54 0: OFF 1: ON RESERVED MODE_SLEEP LDO4 SLEEP Mode 0: OFF 1: ON RESERVED MODE_ACTIVE LDO4 ACTIVE Mode 0: OFF 1: ON Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 55 R/W-X Table 3-48. LDO4_VOLTAGE Register Field Descriptions Field Type Reset Description RESERVED VSEL See VSEL cross table showed in LDO1_VOLTAGE.VSEL register. SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 56 0: OFF 1: ON RESERVED MODE_SLEEP LDO5 SLEEP Mode 0: OFF 1: ON RESERVED MODE_ACTIVE LDO5 ACTIVE Mode 0: OFF 1: ON Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 57 R/W-X Table 3-50. LDO5_VOLTAGE Register Field Descriptions Field Type Reset Description RESERVED VSEL See VSEL cross table showed in LDO1_VOLTAGE.VSEL register. SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 58 1: Pull-Down is enabled when LDO2 is in OFF state LDO1 0: Pull-Down is disable 1: Pull-Down is enabled when LDO1 is in OFF state Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 59 1: Pull-Down is enabled when LDOUSB is in OFF state LDO5 0: Pull-Down is disable 1: Pull-Down is enabled when LDOLN is in OFF state RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 60 1: LDO2 output is short detected LDO1 0: LDO1 is functional. No short detected (default) 1: LDO1 output is short detected Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 61 1: LDOUSB output is short detected LDO5 0: LDOLN is functional. No short detected (default) 1: LDOLN output is short detected RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 62 Field Type Reset Description LDOVANA 0: Pull-Down is disable 1: Pull-Down is enabled when LDOVANA is in OFF state RESERVED RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 63 LDOVANA (internal LDO - reserved) 0: LDOVANA is functional. No short detected (default) 1: LDOVANA output is short detected RESERVED RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 64 Register Name Section 17Fh SPI_PAGE_CTRL SPI Page Control register (used only when SPI interface Section 3.5.1 is used). RESET register domain: SWORST Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 65 Description RESERVED SPI_PAGE_ACCESS Page selection for SPI interface only 0: page1 (ID1=48) and page2 (ID2=49) 1: page1 (ID1=48) and page3 (ID2=4A) SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 66 SMPS DVFS maximum voltage register Section 3.6.2 RESET register domain: HWRST 182h SMPS_DVFS_STATUS SMPS DVFS status register Section 3.6.3 RESET register domain: HWRST Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 67 0: DVFS is not enabled (default) 1: DVFS is enabled (Control of SMPS12) DVFS function in link to I2C2_SCL and I2C2_SDA. SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 68 VOLTAGE_MAX See VSEL cross table showed in SMPS12_VOLTAGE.VSEL register with RANGE[0]=0 (x1 multiplier) and VSEL range from OFF, 0.5 to 1.65V Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 69 SMPS_DVFS_CTRL.DVFS1_OFFSET_STEP=0 (x1 multiplier, 10mv per step)/ 1(x2 multiplier), 20mV per step) 000000: no offset 000001: 10mV/20mV 000010: 20mV/40mV 100000: 320mV/640mV 100001: reserved/reserved 111111: reserved/reserved SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 70 Configuration and status of the Secondary Interrupt Section 3.7.16 Handler (Register2) RESET register domain: HWRST 1C3h BOOT_STATUS Boot Status Register Section 3.7.17 RESET register domain: POR Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 71 DEV_ON Device ON enable 1: will maintain the device in ACTIVE mode 0: allow the device to go in OFF mode SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 72 0: NSLEEP is not masked (allow control of the resource with NSLEEP pin) 1: NSLEEP is masked (does not affect resource control) (default) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 73 10011 = 2.950 V 10100 = 3.000 V 10101 = 3.050 V 10110 = 3.100V 10111 = Reserved 11111 = Reserved SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 74 Description ENABLE Enable VSYS monitoring (only in ACTIVE /SLEEP) 0: VSYS monitoring is not enabled 1: VSYS monitoring is enabled RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 75 011101 = 3.45 V 111101 = 4.60 V 011110 = 3.50 V 111110 = 4.60 V 011111 = 3.55 V 111111 = 4.60 V SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 76 TIMER Timer delay selection: 000: 1s 001: 2s 010: 4s 011: 8s 100: 16s 101: 32s 110: 64s 111: 128s (default) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 77 0: VRTC is configured in a low-power mode configuration. 1: VRTC is configured in the standard power mode configuration (default) RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 78 RESERVED RESERVED LPK_TIME Long press key duration 00: 6 second 01: 8 second 10: 10 second 11: 4 second (default) RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 79 00: 117 / 108 deg. 01: 121 / 112 deg. 10: 125 / 116 deg. 11: 130 / 120 deg. (default) RESERVED RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 80 1: Not masked (Hardware reset) VSYS_LO 0: Masked (Switchoff reset) 1: Not masked (Hardware reset) GPADC_SHUTDOWN 0: Masked (Switchoff reset) 1: Not masked (Hardware reset) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 81 1: Not masked (Cold restart) VSYS_LO 0: Masked (Shutdown) 1: Not masked (Cold restart) GPADC_SHUTDOWN 0: Masked (Shutdown) 1: Not masked (Cold restart) SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 82 Reset Description PWRON_LPK PWRDOWN TSHUT RESET_IN SW_RST VSYS_LO GPADC_SHUTDOWN 0: no GPADC_SHUTDOWN 1: GPADC_SHUTDOWN occured since last read of this register Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 83 11: 4 second window (+/- 250ms) RESERVED AUTODEVON Selection of the feature Auto Device ON 0: Feature is inactive 1: Feature is active SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 84 TSHUT_FASTOFF 0: TSHUT event triggers normal switch off sequence 1: TSHUT event triggers fast switch off sequence (all resources disabeld together) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 85 RESERVED RESERVED RESERVED FSD_MASK Secondary level of mask for FSD_BB interrupt line. First Supply Detection (FSD) Mask. 0: Un-masked 1: Masked SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 86 Table 3-78. SW_REVISION Register Field Descriptions Field Type Reset Description SW_REVISION Software (SW) revision register - This revision will be representative of the OTP version. Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 87 RESERVED DVFS_MASK Secondary level of mask for DVFS interrupt line. Voltage plus offset over voltage max mask. 0: Un-masked 1: Masked SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 88 Field Type Reset Description RESERVED BOOT_MODE BOOT mode selection 0: BOOT pin is pulled low 1: BOOT pin is pulled high Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 89 REGEN2_CTRL REGEN2 control register Section 3.8.15 RESET register domain: SWORST 1E7h REGEN3_CTRL REGEN3 control register Section 3.8.16 RESET register domain: SWORST SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 90 1: ON RESERVED MODE_SLEEP REGEN1 SLEEP Mode 0: OFF 1: ON RESERVED MODE_ACTIVE REGEN1 ACTIVE Mode (OTP-Sequencer) 0: OFF 1: ON Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 91 1: ON RESERVED MODE_SLEEP PLLEN SLEEP Mode 0: OFF 1: ON RESERVED MODE_ACTIVE PLLEN ACTIVE Mode (OTP-Sequencer) 0: OFF 1: ON SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 92 0: NSLEEP has no effect on REGEN2 1: REGEN2 is controlled by NSLEEP REGEN1 0: NSLEEP has no effect on REGEN1 1: REGEN1 is controlled by NSLEEP Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 93 0: NSLEEP has no effect on SMPS1 (or SMPS12 is dual phase selected) 1: SMPS1 (or SMPS12 is dual phase selected) is controlled by NSLEEP) SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 94 0: NSLEEP has no effect on LDO2 1: LDO2 is controlled by NSLEEP LDO1 0: NSLEEP has no effect on LDO1 1: LDO1 is controlled by NSLEEP Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 95 1: LDO3 is controlled by NSLEEP LDO5 0: NSLEEP has no effect on LDO5 1: LDO5 is controlled by NSLEEP RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 96 0: ENABLE1 has no effect on REGEN2 1: REGEN2 is controlled by ENABLE1 REGEN1 0: ENABLE1 has no effect on REGEN1 1: REGEN1 is controlled by ENABLE1 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 97 0: ENABLE1 has no effect on SMPS1(or SMPS12 is dual phase selected) 1: SMPS1 (or SMPS12 is dual phase selected) is controlled by ENABLE1 SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 98 0: ENABLE1 has no effect on LDO2 1: LDO2 is controlled by ENABLE1 LDO1 0: ENABLE1 has no effect on LDO1 1: LDO1 is controlled by ENABLE1 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 99 1: LDO3 is controlled by ENABLE1 LDO5 0: ENABLE1 has no effect on LDO5 1: LDO5 is controlled by ENABLE1 RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 100 0: ENABLE2 has no effect on REGEN2 1: REGEN2 is controlled by ENABLE2 REGEN1 0: ENABLE2 has no effect on REGEN1 1: REGEN1 is controlled by ENABLE2 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 101 0: ENABLE2 has no effect on SMPS1 (or SMPS12 is dual phase selected) 1: SMPS1 (or SMPS12 is dual phase selected) is controlled by ENABLE2 SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 102 0: ENABLE2 has no effect on LDO2 1: LDO2 is controlled by ENABLE2 LDO1 0: ENABLE2 has no effect on LDO1 1: LDO1 is controlled by ENABLE2 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 103 1: LDO3 is controlled by ENABLE2 LDO5 0: ENABLE2 has no effect on LDO5 1: LDO5 is controlled by ENABLE2 RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 104 1: ON RESERVED MODE_SLEEP REGEN2 SLEEP Mode 0: OFF 1: ON RESERVED MODE_ACTIVE REGEN2 ACTIVE Mode (OTP-Sequencer) 0: OFF 1: ON Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 105 1: ON RESERVED MODE_SLEEP REGEN3 SLEEP Mode 0: OFF 1: ON RESERVED MODE_ACTIVE REGEN3 ACTIVE Mode (OTP-Sequencer) 0: OFF 1: ON SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 106 PAD/PIN function register (Primary vs. Section 3.9.8 Secondary) #2 RESET register domain: HWRST 1FCh I2C_SPI Validity memory Section 3.9.9 RESET register domain: HWRST Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 107 1: open drain enable (Push-Pull not enable) RESERVED RESERVED REGEN2_OD 0: open drain not enable (Push-Pull enabled) 1: open drain enable (Push-Pull not enable) RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 108 RESERVED PWRDOWN_PD 0: Pull-down not enabled 1: Pull-down enabled RESERVED NRESWARM_PD 0: Pull-down not enabled 1: Pull-down enabled (default for non-reset) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 109 1: Pull-down enabled (default) NSLEEP_PU 0: Pull-up not enabled 1: Pull-up enabled (default) NSLEEP_PD 0: Pull-down not enabled (default) 1: Pull-down enabled SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 110 1: Pull-down enabled RESERVED RESERVED RESERVED POWERHOLD_PD Secondary function of GPIO_5 0: Pull-down not enabled 1: Pull-down enabled (default) RESERVED RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 111 RESERVED RESERVED INT_OD 0: open drain not enable (Push-Pull enabled) (default) 1: open drain enable (Push-Pull not enable) RESERVED RESERVED RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 112 In case ENABLE1 input line is selected as secondary function: 0: Resources will be enable when ENABLE1 is high (default) 1: Resources will be enable when ENABLE1 is low Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 113 In case POWERDOWN input line is selected as secondary function: 0: Inversion is not enabled - active high (default) 1: Inversion is enabled - active low SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 114 00: Primary function is selected (GPIO_0) 01: Secondary function is selected (PWRDOWN) 10: Secondary function is selected (ENABLE2) 11: Secondary function is selected (REGEN1) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 115 00: Primary function is selected (GPIO_4) 01: Reserved 10: Secondary function is selected (REGEN2) 11: Secondary function is selected (I2C2_SCL_SCE) SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 116 I2C_1 address for page accesses versus initial address (0H48, 0H49, 0H4A, 0H4B (OTP)) I2C_1[0]=0: 0H48 I2C_1[0]=1: 0H58 I2C_1[1]=0: 0H49 I2C_1[1]=1: 0H59 I2C_1[2]=0: 0H4A I2C_1[2]=1: 0H5A I2C_1[3]=0: 0H4B I2C_1[3]=1: 0H5B Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 117 Interrupt control register Section 3.10.15 RESET register domain: HWRST 225h OTP_CRC_RESULTS OTP CRC Checker reuslt register Section 3.10.16 RESET register domain: HWRST SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 118 1: Falling edge is detected PWRON PWRON status bit register associated to PWRON pin 0: no detection 1: Falling edge is detected RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 119 0: PWRON line is enabled. An interrupt is generated on INT line 1: PWRON line is masked. No interrupt is generated on INT line RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 120 1: LONG_PRESS_KEY line is equal to 1 PWRON PWRON line state register 0: PWRON line is equal to 0 1: PWRON line is equal to 1 RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 121 1: Rising edge is detected OTP_ERROR OTP_ERROR status bit register (internal event) 0: no detection 1: Rising edge is detected RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 122 0: OTP_ERROR line is enabled. An interrupt is generated on INT line 1: OTP_ERROR line is masked. No interrupt is generated on INT line RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 123 1: WDT line is equal to 1 OTP_ERROR OTP_ERROR line state register 0: OTP_ERROR line is equal to 0 1: OTP_ERROR line is equal to 1 RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 124 0: no detection 1: Rising edge is detected GPADC_AUTO_0 GPADC_AUTO_0 status bit register (Internal event) 0: no detection 1: Rising edge is detected Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 125 0: GPADC_AUTO_0 line is enabled. An interrupt is generated on INT line 1: GPADC_AUTO_0 line is masked. No interrupt is generated on INT line SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 126 GPADC_AUTO_0 GPADC_AUTO_0 line state register (Internal event) 0: GPADC_AUTO_0 line is equal to 0 1: GPADC_AUTO_0 line is equal to 1 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 127 1: Rising or Falling edge are detected GPIO_0 GPIO_0 status bit register associated to GPIO_0 pin 0: no detection 1: Rising or Falling edge are detected SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 128 0: GPIO_0 line is enabled. An interrupt is generated on INT line 1: GPIO_0 line is masked. No interrupt is generated on INT line Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 129 1: GPIO_1 line is equal to 1 GPIO_0 GPIO_0 line state register 0: GPIO_0 line is equal to 0 1: GPIO_0 line is equal to 1 SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 130 0: Rising edge detection not enabled 1: Rising edge detection enable (default) GPIO_0_FALLING 0: Falling edge detection not enabled 1: Falling edge detection enable (default) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 131 0: Rising edge detection not enabled 1: Rising edge detection enable (default) GPIO_4_FALLING 0: Falling edge detection not enabled 1: Falling edge detection enable (default) SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 132 0: Clear-on-Write - Interrupts cleared by writing 1. This method is bit based (default) 1: Clear-on-Read - Interrupts cleared on read Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 133 CRC result from Power Sequence OTP registers: 0: Good 1: Error CRC_RESULTS_TRIM CRC result from Trim data OTP registers: 0: Good 1: Error SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 134 Product ID Register (LSB) Section 3.11.3 RESET register domain: HWRST 252h PRODUCT_ID_MSB Product ID Register (MSB) Section 3.11.4 RESET register domain: HWRST Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 135 Table 3-126. VENDOR_ID_LSB Register Field Descriptions Field Type Reset Description VENDOR_ID Texas Instruments USB Vendor ID (8 LSBs) - Default value: 0x51 SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 136 Table 3-127. VENDOR_ID_MSB Register Field Descriptions Field Type Reset Description VENDOR_ID Texas Instruments USB Vendor ID (8 MSBs) - Default value: 0x04 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 137 Table 3-128. PRODUCT_ID_LSB Register Field Descriptions Field Type Reset Description PRODUCT_ID Texas Instruments Product ID (8 LSBs) - Default value: 0x35 SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 138 Table 3-129. PRODUCT_ID_MSB Register Field Descriptions Field Type Reset Description PRODUCT_ID Texas Instruments Product ID (8 MSBs) - Default value: 0xC0 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 139 Note: It is user responsibility to take care about the GPIO direction and type (Open drain / Push-Pull) versus the pull-up/pull-down selections SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 140 Data read value (in) of the GPIO_2 GPIO_1_IN Data read value (in) of the GPIO_1 GPIO_0_IN Data read value (in) of the GPIO_0 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 141 0: buffer in input configuration (default) 1: buffer in output configuration GPIO_0_DIR 0: buffer in input configuration (default) 1: buffer in output configuration SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 142 Data write value (out) of the GPIO_2 GPIO_1_OUT Data write value (out) of the GPIO_1 GPIO_0_OUT Data write value (out) of the GPIO_0 Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 143 1: Debounce enabled GPIO_1_DEBOUNCE_EN R/W 0: No debounce (default) 1: Debounce enabled GPIO_0_DEBOUNCE_EN R/W 0: No debounce (default) 1: Debounce enabled SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 144 0: no action on GPIO_1 bit 1: CLEAR GPIO_1 bit GPIO_0_CLEAR_DATA_ 0: no action on GPIO_0 bit 1: CLEAR GPIO_0 bit Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 145 0: no action on GPIO_1 bit 1: SET GPIO_1 bit GPIO_0_SET_DATA_OU 0: no action on GPIO_0 bit 1: SET GPIO_0 bit SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 146 1: Pull-down enabled (default) RESERVED GPIO_1_PD 0: Pull-down not enabled 1: Pull-down enabled (default) RESERVED GPIO_0_PD 0: Pull-down not enabled 1: Pull-down enabled (default) Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 147 1: Pull-down enabled (default) GPIO_4_PU 0: Pull-up not enabled (default) 1: Pull-up enabled GPIO_4_PD 0: Pull-down not enabled 1: Pull-down enabled (default) SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 148 1: open drain enable (Push-Pull not enable) RESERVED GPIO_2_OD 0: open drain not enable (Push-Pull enabled) (default) 1: open drain enable (Push-Pull not enable) RESERVED RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 149 RESET register domain: HWRST 2D3h GPADC_THRES_CONV1_MSB MSB of Threshold reference to be compared to the Section 3.13.18 Conversion 1 results RESET register domain: HWRST SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 150 Section 3.13.19 RESET register domain: HWRST 2D5h GPADC_SMPS_VSEL_MONITORING GPADC SMPS voltage monitoring related to Section 3.13.20 ILMONITORING measurement RESET register domain: HWRST Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 151 0: GPADC OFF. The GPADC is controlled by conversion request in all modes (default) 1: GPADC ON (Always ON - will allow conversion latency) SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 152 Flush the conversion result of the GPADC when it is stuck in a busy state. This bit can be toggled to 1 and back to 0 to recover the GPADC operation. Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 153 Time slot between conversions (RT and SW modes) or two consecutive conversions (Auto mode) 0000: 1/32s (default) 0001: 1/16s 0010: 1/8s ..1110: 512s 1111: 1024s SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 154 Reset Description RESERVED GPADC_AVAILABLE GPADC availability status 0: Conversions not completed. GPADC not available (busy) 1: Conversions completed. GPADC available RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 155 GPADC Flush Enable 0: The Flush operation of GPADC is locked (default) 1: The Flush operation of GPADC is enabled RESERVED RESERVED SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 156 0: GPADC is not stuck in a busy state 1: GPADC is stuck in a busy state. Flushing the GPADC is necessary to return it to normal operation RESERVED Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 157 Channel selection for Conversion 0 in Automatic mode 0000: GPADC Channel 0 0001: GPADC Channel 1 ..0110: GPADC Channel 6 0111: GPADC Channel 7 others: Reserved SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 158 Figure 3-135. GPADC_AUTO_CONV0_LSB Register AUTO_CONV0_LSB R-0h Table 3-148. GPADC_AUTO_CONV0_LSB Register Field Descriptions Field Type Reset Description AUTO_CONV0_LSB AUTO Conversion 0 data result (LSB) <7:0> Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 159 R-0h R-0h Table 3-149. GPADC_AUTO_CONV0_MSB Register Field Descriptions Field Type Reset Description RESERVED AUTO_CONV0_MSB AUTO Conversion 0 data result (MSB) <11:8> SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 160 Figure 3-137. GPADC_AUTO_CONV1_LSB Register AUTO_CONV1_LSB R-0h Table 3-150. GPADC_AUTO_CONV1_LSB Register Field Descriptions Field Type Reset Description AUTO_CONV1_LSB AUTO Conversion 1 data result (LSB) <7:0> Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 161 R-0h R-0h Table 3-151. GPADC_AUTO_CONV1_MSB Register Field Descriptions Field Type Reset Description RESERVED AUTO_CONV1_MSB AUTO Conversion 1 data result (MSB) <11:8> SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 162 Channel selection for Conversion 0 in SW mode 0000: GPADC Channel 0 0001: GPADC Channel 1 ..0110: GPADC Channel 6 0111: GPADC Channel 7 others: Reserved Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 163 Figure 3-140. GPADC_SW_CONV0_LSB Register SW_CONV0_LSB R-0h Table 3-153. GPADC_SW_CONV0_LSB Register Field Descriptions Field Type Reset Description SW_CONV0_LSB SW Conversion 0 data result (LSB) <7:0> SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 164 R-0h R-0h Table 3-154. GPADC_SW_CONV0_MSB Register Field Descriptions Field Type Reset Description RESERVED SW_CONV0_MSB SW Conversion 0 data result (MSB) <11:8> Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 165 Figure 3-142. GPADC_THRES_CONV0_LSB Register THRES_CONV0_LSB R/W-0h Table 3-155. GPADC_THRES_CONV0_LSB Register Field Descriptions Field Type Reset Description THRES_CONV0_LSB Threshold value for Conversion 0 (LSB) <7:0> SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 166 0: Interrupt generated if Conversion0 result is above threshold 1: Interrupt generated if Conversion0 result is below threshold RESERVED THRES_CONV0_MSB Threshold value for Conversion 0 (MSB) <11:8> Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 167 Figure 3-144. GPADC_THRES_CONV1_LSB Register THRES_CONV1_LSB R/W-0h Table 3-157. GPADC_THRES_CONV1_LSB Register Field Descriptions Field Type Reset Description THRES_CONV1_LSB Threshold value for Conversion 1 (LSB) <7:0> SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 168 0: Interrupt generated if Conversion0 result is above threshold 1: Interrupt generated if Conversion0 result is below threshold RESERVED THRES_CONV1_MSB Threshold value for Conversion 1 (MSB) <11:8> Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 169 Others: Reserved 0000b = SMPS1 / SMPS12 0001b = SMPS2 0010b = Reserved 0011b = SMPS3 0100b = Reserved 0101b = SMPS5 SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 170 Specify the number of active phases during measurements 0: One phase 1: Multi-phases (more than one) SMPS_VSEL_MONITORI See VSEL cross table showed in SMPS1_VOLTAGE.VSEL register Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 171 Table 3-161. FUNC_DESIGNREV Registers Address Acronym Register Name Section 357h DESIGNREV Silicon version number register Section 3.14.1 RESET register domain: POR SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 172 Reset Description RESERVED DESIGNREV Value depending on silicon version number (From metal bits) 0000 - CS1.0 Revision 0001 - CS1.1 Revision Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 173 RESET register domain: POR Section 3.15.4 3E4h GPADC_TRIM5 RESET register domain: POR Section 3.15.5 3B8h GPADC_TRIM6 RESET register domain: POR Section 3.15.6 SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 174 GPADC Input Channels 0 and 1 Calibration Value D1 GPADC_IN0_IN1_D1_SI Sign bit of the GPADC Input Channels 0 and 1 Calibration Value D1 0: Positive 1: Negative Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 175 GPADC Input Channels 0 and 1 Calibration Value D2 GPADC_IN0_IN1_D2_SI Sign bit of the GPADC Input Channels 0 and 1 Calibration Value D2 0: Positive 1: Negative SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 176 GPADC Input Channel 3 Calibration Value D1 when HIGH_VCC_SENSE=0 VCC_D1_SIGN Sign bit of the GPADC Input Channel 3 Calibration Value D1 when HIGH_VCC_SENSE=0 0: Positive 1: Negative Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 177 GPADC Input Channel 3 Calibration Value D2 when HIGH_VCC_SENSE=0 VCC_D2_SIGN Sign bit of the GPADC Input Channel 3 Calibration Value D2 when HIGH_VCC_SENSE=0 0: Positive 1: Negative SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 178 GPADC Input Channel 3 Calibration Value D1 when HIGH_VCC_SENSE=1 VCC_D1_SIGN Sign bit of the GPADC Input Channel 3 Calibration Value D1 when HIGH_VCC_SENSE=1 0: Positive 1: Negative Register Descriptions SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 179 GPADC Input Channel 3 Calibration Value D2 when HIGH_VCC_SENSE=1 VCC_D2_SIGN Sign bit of the GPADC Input Channel 3 Calibration Value D2 when HIGH_VCC_SENSE=1 0: Positive 1: Negative SLVUAH1C – June 2015 – Revised April 2017 Register Descriptions Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 180 Updated GPADC_TRIM3 and GPADC_TRIM4 registers to HIGH_VCC_SENSE = 0 ................• Added the GPADC_TRIM5 and GPADC_TRIM6 registers ....................• Added the BOOT_STATUS register Revision History SLVUAH1C – June 2015 – Revised April 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
  • Page 181 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products;...

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