Furuno FELCOM 12 Service Manual page 51

CPU block
CPU board consists of a pair of CPU1 and CPU 2 a demodulator, and a Viterbi
decoder. Functions of each circuit are summarized as follows.
CPU1:
• Data entry of a receiving symbol every RX CLK
• Synchronous detection by unique words
• Receiving data processing before Viterbi decoding
• Frequency adjustment control
• Synchronization control of TX CLK
• TX start timing control
CPU2:
• Receiving data processing after Viterbi decoding
• Transmitting data processing
• Transmitting control
• Slot number control
• Synthesizer control
• Measurement of TX/RX level
• RF block monitoring
• Alarm processing
• Releasing alarm sound
• Clock control
• Data interfacing with terminals (DTE1, 2) and its data processing
• Data interfacing with DATA (PC) and its data processing
• Data interfacing with navigation devices (including internal GPS) and its data
processing
• Input/output control of distress alert unit (DMC1, 2) and received call unit
• Polling and data-reporting
• Forward and return ID handling
Demodulator:
• Regenerates RCV CLK from receiving IF signal (50 kHz, BPSK signal), and
demodulates to 3-bit quantized data.
Viterbi Decoder:
• Decodes 3-bit quantized data which is supplied from the demodulator through
CPU1.
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