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National Instruments DAQ-STC Series Technical Reference Manual

System timing controller for data acquisition

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System Timing Controller for Data Acquisition

DAQ-STC Technical Reference Manual

January 1999 Edition

Part Number 340934B-01

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Page 1 ™ DAQ-STC Technical Reference Manual System Timing Controller for Data Acquisition DAQ-STC Technical Reference Manual January 1999 Edition Part Number 340934B-01...
Page 2 Singapore 2265886, Spain 91 640 0085, Sweden 08 730 49 70, Switzerland 056 200 51 51, Taiwan 02 377 1200, United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, Texas 78730-5039 USA Tel: 512 794 0100 © Copyright 1995, 1998 National Instruments Corporation. All rights reserved.
Page 3 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period.
Page 4: Table Of Contents
Contents About This Manual Organization of This Manual ..................xxiii Conventions Used in This Manual.................xxv National Instruments Documentation ................xxvi Related Documentation....................xxvi Customer Communication .....................xxvii Chapter 1 Introduction DAQ-STC Applications ..................1-2 1.1.1 Analog Input Application ..............1-2 1.1.2 Analog Output Application ..............1-3 DAQ-STC Block Diagram .................1-4...
Page 5 Maximum Rate Analog Input ............2-91 2.7.6 External CONVERT Source .............. 2-92 2.7.7 External Triggers................2-93 2.7.8 Trigger Output..................2-97 2.7.8.1 START1 and START2 Triggers ........2-97 2.7.8.2 START Trigger and SCAN_IN_PROG Assertion..2-100 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 6 Simplified Model....................3-4 Analog Output Functions ...................3-5 3.4.1 Primary Group Analog Output Modes ..........3-5 3.4.1.1 DAQ-STC-Driven Analog Output........3-6 3.4.1.2 CPU-Driven Analog Output .........3-6 3.4.1.3 DAQ-STC and CPU Conflict ........3-7 3.4.2 DAC Interface ..................3-8 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 7 Programming for a Secondary Analog Output Group Operation ..3-38 3.6.6.1 Overview ..............3-38 3.6.6.2 Resetting ............... 3-38 3.6.6.3 Board Power-up Initialization ........3-39 3.6.6.4 Hardware Gate Programming........3-39 3.6.6.5 Software Gate Operation ..........3-40 DAQ-STC Technical Reference Manual viii © National Instruments Corporation...
Page 8 Using Synchronization..........3-116 3.8.2.3 Trigger Signals..............3-116 3.8.3 Analog Output Counters..............3-117 3.8.3.1 UI Counter ..............3-117 3.8.3.2 UI Control ..............3-118 3.8.3.3 UC Counter ..............3-118 3.8.3.4 UC Control..............3-119 3.8.3.5 BC Counter ..............3-120 3.8.3.6 BC Control ..............3-120 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 9 Continuous Pulse-Train Generation ......4-12 4.4.4.2 Buffered Static Pulse-Train Generation ....... 4-13 4.4.4.3 Buffered Pulse-Train Generation ......... 4-14 4.4.4.4 Frequency Shift Keying (FSK)........4-14 4.4.4.5 Pulse Generation for ETS..........4-15 Pin Interface ....................... 4-16 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 10 Save on G_GATE ............4-68 4.8.7.3 Reload on G_CONTROL ..........4-68 4.8.7.4 UP/DOWN on G_CONTROL ........4-69 4.8.7.5 Generate Interrupt on G_GATE........4-69 4.8.7.6 Change Output Polarity on G_GATE ......4-69 4.8.7.7 Select Load Register on G_CONTROL .......4-69 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 11 Pin Interface ....................... 5-2 Programming Information ................. 5-5 5.4.1 Programming the PFI Pins ..............5-5 5.4.2 Bitfield Descriptions ................5-6 Detailed Description ..................5-7 Chapter 6 RTSI Trigger Overview......................6-1 Features ......................6-1 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 12 Serial Input Timing................7-15 7.7.2 Serial Output Timing................7-16 Detailed Description...................7-17 Chapter 8 Interrupt Control Overview ......................8-1 Features ......................8-1 Pin Interface .......................8-2 Programming Information..................8-3 8.4.1 Programming the Interrupt Interface ..........8-3 8.4.1.1 Interrupt Output Polarity..........8-3 © National Instruments Corporation xiii DAQ-STC Technical Reference Manual...
Page 13 Programming Information ................. 10-10 10.8.1 Programming Clock Distribution............10-10 10.8.2 Programming FOUT ................10-12 10.8.3 Programming Analog Trigger ............10-12 10.8.4 Bitfield Descriptions ................10-12 Appendix A Specifications Appendix B Register Information DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 14 Data FIFO Timing .................2-88 Figure 2-18. Configuration Memory Timing .............2-89 Figure 2-19. Maximum Rate Analog Input Timing ...........2-92 Figure 2-20. External CONVERT_SRC Timing ............2-93 Figure 2-21. External Trigger Timing, Asynchronous Level ........2-94 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 15 CPU-Driven Analog Output ..............3-7 Figure 3-4. DAQ-STC and CPU Conflict..............3-7 Figure 3-5. FIFO Data Interface ................3-9 Figure 3-6. Local Buffer Mode................3-10 Figure 3-7. Serial Link Data Interface ..............3-10 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 16 Buffered Noncumulative Event Counting ..........4-5 Figure 4-5. Cumulative Event Counting ..............4-5 Figure 4-6. Relative Position Sensing..............4-6 Figure 4-7. Single-Period Measurement ..............4-7 Figure 4-8. Single-Pulsewidth Measurement............4-7 Figure 4-9. Buffered Period Measurement...............4-8 Figure 4-10. Buffered Semiperiod Measurement............4-8 © National Instruments Corporation xvii DAQ-STC Technical Reference Manual...
Page 17 Pulse Generation for ETS ..............4-87 Figure 7-1. DIO Simplified Model ................7-2 Figure 7-2. Parallel Input ..................7-3 Figure 7-3. Parallel Output ..................7-3 Figure 7-4. DIO Serial Input..................7-4 DAQ-STC Technical Reference Manual xviii © National Instruments Corporation...
Page 18 DAQ-STC-Driven Analog Output Timing ...........3-87 Table 3-5. External Trigger Timing................3-104 Table 3-6. Internal Signals ..................3-109 Table 3-7. PFI Selectors ..................3-115 Table 3-8. Analog Output Interrupts ..............3-122 Table 3-9. Analog Output Nominal Signal Widths ..........3-124 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 19 Intel Bus Interface Timing ..............9-6 Table 9-3. Intel Bus Interface Timing ..............9-8 Table 10-1. Timebases Derived from IN_TIMEBASE ........... 10-2 Table 10-2. Test Mode Input Pin Pairs ..............10-8 Table 10-3. Pin Interface ..................10-9 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 20 Table B-1. DAQ-STC Registers ................B-1 Table B-2. Registers in Order of Address* ............B-5 Table B-3. Bitfield Description Guide ..............B-9 Table C-1. DAQ-STC Pins in Alphabetical Order ..........C-1 Table C-2. Summary of Buffer Types..............C-7 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 21: About This Manual
Chapter 1, Introduction, describes the data acquisition system timing controller (DAQ-STC), an application-specific integrated circuit (ASIC) for the system timing requirements of a general-purpose A/D and D/A system, such as a system containing the National Instruments multifunction I/O boards. •...
Page 22 DAQ-STC. • Appendix E, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products and manuals. • Glossary contains an alphabetical list and description of terms used in this manual, including abbreviations, acronyms, metric prefixes, mnemonics, and symbols.
Page 23: Conventions Used In This Manual
This font is also used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, operations, variables, filenames and extensions, and for statements and comments taken from programs. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 24: National Instruments Documentation
SCXI chassis manuals—If you are using SCXI, read these manuals for maintenance information on the chassis and installation instructions. Related Documentation The following National Instruments documents contain general information and operating instructions for the DAQ-STC: • The AT E Series Register-Level Programmer Manual •...
Page 25: Customer Communication
80x86-Based Computers Customer Communication National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete.
Page 26: Introduction
This chapter describes the data acquisition system timing controller (DAQ-STC), an application-specific integrated circuit (ASIC) for the system timing requirements of a general-purpose A/D and D/A system, such as a system containing the National Instruments multifunction I/O (MIO) boards. The DAQ-STC contains nine modules, or function groups. These function groups include the...
Page 27: Daq-Stc Applications
The analog channels enter the board through the I/O connector, as shown at the left of the figure. The DAQ-STC supplies a hold command to latch the analog values at the sample/hold device. On boards with multiple-input channels, a multiplexer selects each channel, one at a DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 28: Analog Output Application
D/A converters (DACs) subsequently convert the digital data to an analog form. Output Data Analog Channels Data DACs DAC Write FIFO DAC Address Status Retransmit Update CPU Request DAQ-STC Analog Output Timing/Control Channel Ready Timing/Trigger Timing/Trigger RTSI Connector Figure 1-2. Analog Output Application © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 29: Daq-Stc Block Diagram
UPDATE, UPDATE2, AOFFRT DACWR<0..1>, LDAC<0..1>, AOFREQ Digital I/O STATUS<0..3> BC_TC, UC_TC CONTROL<0..7> EXTSTROBE/SDCLK G_UP_DOWN<0..1> General-Purpose OSC, TEST_IN Counter/Timer ANALOG_TRIG_IN_LO G_OUT0/RTSI_IO Miscellaneous ANALOG_TRIG_IN_HI Functions OUTBRD_OSC, FOUT G_OUT1/DIV_TC_OUT ANALOG_TRIG_DRIVE TEST_OUT Figure 1-3. DAQ-STC Block Diagram DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 30: Analog Input Timing/Control
2.7, Timing Diagrams. You will also need to consult the register-level programmer manual for the hardware containing the DAQ-STC. If you need additional help programming the AITM, read section 2.8, Detailed Description. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 31: Features
Ability to change the scan rate during an acquisition, in combination with the GPCT module or directly in software • Scan count – 24-bit scan down counter – Trigger up to 2 scans or generate scans continuously DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 32 16-bit counter can generate internal multiplexer clock by dividing down the external multiplexer clock – Provides a clock for the external multiplexer – Simultaneous sample and hold – Generates the track-and hold-signal © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 33: Simplified Model
The AITM contains the hardware necessary to generate timing and control signals for the ADC and the associated circuitry on a National Instruments DAQ board, such as an MIO board. Figure 2-1 shows the timing and control signals used in a typical analog input operation.
Page 34: Figure 2-2. Aitm Simplified Model
The SHIFTIN signals (AI_FIFO_SHIFTIN and SHIFTIN), which pulse after the ADC has completed a conversion, move the data into the analog input data FIFO. The AIFREQ (AI data FIFO request) signal generates a DMA request based on the analog input © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 35: Analog Input Functions
CONVERT and the signals derived from CONVERT—the ADC, the data FIFO, and the configuration FIFO and external multiplexer. CONVERT timing is affected by your selection of internal or external CONVERT mode. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 36: Adc Control
The DAQ-STC fully supports a FIFO-based configuration memory that can update on every CONVERT pulse. Typically, the configuration FIFO contains one data word for each input channel included in the scan. At the © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 37: Figure 2-4. Configuration Fifo Control
CONVERT, but the LOCALMUX_CLK signal pulses only when the DIV counter reaches state 0. Figure 2-5 shows the operation of these signals during a scan where four external channels are multiplexed onto each of two input channels. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 38: Convert Timing
The first parameter, A, gives the delay from START to the first CONVERT. The second parameter, B, gives the delay between CONVERT pulses. The SI2 reload mode setting allows the SI2 counter to alternate load registers on every STOP, thus providing the dual timing feature. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 39: Figure 2-6. Internal Convert Timing
Figure 2-7 shows two scans with four externally timed CONVERT pulses each and indicates how the delay from START to the first CONVERT can vary. The SCAN_IN_PROG output asserts on the recognition of START and deasserts on STOP. DAQ-STC Technical Reference Manual 2-10 © National Instruments Corporation...
Page 40: Scan-Level Timing And Control
The SI counter has dual-load registers that allow for two timing parameters at the START timing level. The first parameter (A) gives the delay from START1 to the first START. The second parameter (B) gives the delay between START pulses. © National Instruments Corporation 2-11 DAQ-STC Technical Reference Manual...
Page 41: External Start Mode
START pulses. The delay from START1 to the first START depends on the relationship between the START1 trigger and the external START and can vary. DAQ-STC Technical Reference Manual 2-12 © National Instruments Corporation...
Page 42: Figure 2-9. External Start
External START pulses are not recognized until the SI_TC. This feature gives the user greater control over the external START timing. External START START1 SI_TC START Figure 2-10. SI Special Trigger Delay © National Instruments Corporation 2-13 DAQ-STC Technical Reference Manual...
Page 43: Acquisition-Level Timing And Control
START2 can be recognized. The second parameter gives the posttrigger count requirement; that is, the number of scans that will occur after START2 is recognized. DAQ-STC Technical Reference Manual 2-14 © National Instruments Corporation...
Page 44: Continuous Acquisition Mode
AI_End_On_End_Of_Scan command terminates the scan sequence at the end of the next scan. The AI_End_On_SC_TC command terminates the scan sequence at the next SC_TC (SC counter TC). The software reset command terminates the scan sequence immediately. © National Instruments Corporation 2-15 DAQ-STC Technical Reference Manual...
Page 45: Staged Acquisition
When the START signal is externally generated, only free-run gating is available. In all modes, the conversion signal CONVERT is gated on a scan basis; that is, entire scans are gated on or off. DAQ-STC Technical Reference Manual 2-16 © National Instruments Corporation...
Page 46: Free-Run Gating Mode
SI counter pauses so that no START pulses are generated. When the external gate asserts, the START occurs immediately (with jitter of up to one SI source clock period). The external gate works as a pseudotrigger for a scan in this mode. © National Instruments Corporation 2-17 DAQ-STC Technical Reference Manual...
Page 47: Single-Wire Mode
CONVERT. Interval-scan timing is still permitted, although the number of timing parameters is quite limited. Figure 2-15 shows an example of three scans of four CONVERT pulses each in single-wire mode. Single Wire START1 START STOP CONVERT Figure 2-15. Single-Wire Mode DAQ-STC Technical Reference Manual 2-18 © National Instruments Corporation...
Page 48: Pin Locator Interface
AI_FIFO_SHIFTIN pulse is inhibited for the conversions that occur when the GHOST signal is active. Output polarity is selectable. Destination: AI data FIFO. Options: Active Low, Active High. Related bitfields: AI_SHIFTIN_Polarity, AI_SHIFTIN_Pulse_Width. © National Instruments Corporation 2-19 DAQ-STC Technical Reference Manual...
Page 49 Destination: ADC. Options: Active Low, Active High, Ground, High Z. Related bitfields: AI_CONVERT_Output_Select, AI_CONVERT_Pulse, AI_CONVERT_Original_Pulse, AI_CONVERT_Pulse_Timebase, AI_CONVERT_Pulse_Width. DIV_TC O4TU DIV Counter TC Signal—Output polarity is active high. Related bitfields: Misc_Counter_TCs_Output_Enable. DAQ-STC Technical Reference Manual 2-20 © National Instruments Corporation...
Page 50 Ghost Input—This active high input masks the AI_FIFO_SHIFTIN pulses associated with specific channels to allow multirate scanning. The GHOST signal is produced by the configuration FIFO containing the scan list. Source: Configuration FIFO. © National Instruments Corporation 2-21 DAQ-STC Technical Reference Manual...
Page 51 Configuration FIFO Empty Flag—This input indicates that the configuration FIFO is empty. The MUXFEF signal is used to generate the configuration FIFO retransmit signal (LOCALMUX_FFRT). The input polarity is selectable. Source: Configuration FIFO. Related bitfields: AI_FIFO_Flags_Polarity. DAQ-STC Technical Reference Manual 2-22 © National Instruments Corporation...
Page 52 SCAN_IN_PROG signal (when STOP is asserted). The input polarity is selectable, and the input state can be directly observed in one of the status registers. Source: ADC. Related bitfields: AI_SOC_Polarity, AI_SOC_St. © National Instruments Corporation 2-23 DAQ-STC Technical Reference Manual...
Page 53: Programming Information
If the bitfield is not cleared automatically, update the software copy by replacing it with secondary copy. Bitfields that get cleared automatically are called strobe bits. To change the state of a bitfield that spans over two registers, you need to write to both registers. DAQ-STC Technical Reference Manual 2-24 © National Instruments Corporation...
Page 54: Windowing Registers
Other programming constructs, such as if-then, should be executed in the order shown. © National Instruments Corporation 2-25 DAQ-STC Technical Reference Manual...
Page 55: Resetting
AI_STOP_Interrupt_Enable = 0; AI_Error_Interrupt_Enable = 0; AI_FIFO_Interrupt_Enable = 0; ∑ AI_SC_TC_Error_Confirm = 1; AI_SC_TC_Interrupt_Ack = 1; AI_START1_Interrupt_Ack = 1; AI_START2_Interrupt_Ack = 1; AI_START_Interrupt_Ack = 1; AI_STOP_Interrupt_Ack = 1; AI_Error_Interrupt_Ack = 1; ∑ DAQ-STC Technical Reference Manual 2-26 © National Instruments Corporation...
Page 56: Board Power-Up Initialization
1 (AI_IN_TIMEBASE1 is IN_TIMEBASE divided by two); AI_Output_Divide_By_2 = 0 (AI_OUT_TIMEBASE equals IN_TIMEBASE) or 1 (AI_OUT_TIMEBASE is IN_TIMEBASE divided by two); AI_CONVERT_Pulse_Timebase = 0 (pulsewidth is selected by AI_CONVERT_Pulse_Width) or 1 (pulse width is selected by AI_CONVERT_Original_Pulse); © National Instruments Corporation 2-27 DAQ-STC Technical Reference Manual...
Page 57: Initialize Configuration Memory Output
Use this function to generate a LOCALMUX_CLK pulse that accesses the first value in the configuration FIFO. Function AI_Initialize_Configuration_Memory_Output Begin critical section; AI_Configuration_Start = 1; If (an external MUX is present) then AI_External_MUX_Present = 0; DAQ-STC Technical Reference Manual 2-28 © National Instruments Corporation...
Page 58: Board Environment Setup
If (more than one external MUX channel corresponds to each internal channel) then AI_External_MUX_Present = 1; ∑ AI_DIV_Load_A = number of external channels corresponding to each internal channel - 1; ∑ AI_DIV_Load = 1; Else AI_External_MUX_Present = 0; © National Instruments Corporation 2-29 DAQ-STC Technical Reference Manual...
Page 59: Fifo Request
Function AI_Hardware_Gating Begin critical section; ∑ AI_Configuration_Start = 1; If (external gating is desired) then DAQ-STC Technical Reference Manual 2-30 © National Instruments Corporation...
Page 60: Software Gate Operation
Software and hardware gating can be used simultaneously without any special setup. The analog input operation proceeds when neither hardware nor software gate is in the pause state. © National Instruments Corporation 2-31 DAQ-STC Technical Reference Manual...
Page 61: Trigger Signals
AI_START2_Polarity = 0; AI_START2_Edge = 1; AI_START2_Sync = 1; Else AI_START2_Polarity = 0 (active high or rising edge) or 1 (active low or falling edge); AI_START2_Edge = 1; AI_START2_Sync = 1; DAQ-STC Technical Reference Manual 2-32 © National Instruments Corporation...
Page 62: Number Of Scans
Function AI_Number_Of_Scans Begin critical section; AI_Configuration_Start = 1; ∑ If (continuous acquisition) then AI_Continuous = 1; /*Infinite number of scans*/ Else AI_Continuous = 0; If (pretriggered acquisition) then AI_Pre_Trigger = 1; © National Instruments Corporation 2-33 DAQ-STC Technical Reference Manual...
Page 63: Start Of Scan
( ) and AI_Scan_Rate_Change staged acquisition ( AI_Staged_ISR Function AI_Scan_Start Begin critical section; Declare variable si_last_load_register AI_Configuration_Start = 1; ∑ DAQ-STC Technical Reference Manual 2-34 © National Instruments Corporation...
Page 64 AI_SI_Reload_Mode = 6 (alternate first period on every SC_TC); Else /*Interval from the START1 trigger to the first start of scan is equal to the scan interval*/ AI_SI_Load_A = number of clocks between each START - 1; © National Instruments Corporation 2-35 DAQ-STC Technical Reference Manual...
Page 65 If (SI Special Trigger Delay is used) then AI_SI_Special_Trigger_Delay = 1; AI_SI_Write_Switch = 0; If (an internal timebase is used) then AI_SI_Source_Select = 0 (AI_IN_TIMEBASE1) or 19 (IN_TIMEBASE2); AI_SI_Source_Polarity = 0; DAQ-STC Technical Reference Manual 2-36 © National Instruments Corporation...
Page 66: End Of Scan
Function AI_Scan_End Begin critical section; AI_Configuration_Start = 1; ∑ If (the end of scan is coming from the outside, either PFI or Configuration FIFO) then © National Instruments Corporation 2-37 DAQ-STC Technical Reference Manual...
Page 67: Convert Signal
Use this function to select the CONVERT signal. You can specify the channel rate by choosing an internally generated periodic event. Function AI_CONVERT_Signal Begin critical section; AI_Configuration_Start = 1; ∑ If (internal CONVERT mode is selected) then DAQ-STC Technical Reference Manual 2-38 © National Instruments Corporation...
Page 68 AI_SI2_Load_B = number of clocks between two CONVERT signals within a scan - 1; AI_SI2_Reload_Mode = 1 (alternate first period on every STOP); ∑ AI_SI2_Load = 1; ∑ AI_SI2_Initial_Load_Source = 1; © National Instruments Corporation 2-39 DAQ-STC Technical Reference Manual...
Page 69: Enable Interrupts
AI_STOP_Interrupt_Enable = 0 (disabled); AI_SC_TC_Interrupt_Enable = 0 (disabled) or 1 (enabled); AI_START1_Interrupt_Enable = 0 (disabled) or 1 (enabled); AI_START2_Interrupt_Enable = 0 (disabled) or 1 (enabled); AI_Error_Interrupt_Enable = 0 (disabled) or 1 (enabled); DAQ-STC Technical Reference Manual 2-40 © National Instruments Corporation...
Page 70: Arming
(for pretriggered operation) or software posttrigger (for non-pretriggered operation). This function does not do anything unless you have selected software pretrigger or posttrigger. Function AI_Start_The_Acquisition If (acquisition is pretriggered) then If (software pretrigger) then AI_START1_Pulse = 1; Else © National Instruments Corporation 2-41 DAQ-STC Technical Reference Manual...
Page 71: Analog Input Program
To acquire exactly one scan of input, a special programming sequence is required, as follows. Use the programming sequence from section 2.6.3.16, Analog Input Program. In the function , set AI_Scan_Start AI_START_Select = 31 (ground); AI_START_Polarity = 0; DAQ-STC Technical Reference Manual 2-42 © National Instruments Corporation...
Page 72: Change Scan Rate During An Acquisition
Else If (AI_SI_Next_Load_Source_St is 1) then AI_SI_Load_A = ] - 1; si_ticks si_ticks_pointer + = 1; si_ticks_pointer = 0; si_last_load_register If (switch SI load registers on TC) then AI_SI_Switch_Load_On_TC = 1; © National Instruments Corporation 2-43 DAQ-STC Technical Reference Manual...
Page 73: Staged Acquisition
/*rate. Otherwise, you cannot change the rate*/ If ( is 0) then si_last_load_register AI_SI_Load_B = ] - 1; si_ticks si_ticks_pointer If ( ] is 0) then sc_ticks sc_ticks_pointer AI_End_On_SC_TC = 1; AI_SC_TC_Interrupt_Enable = 0; Else DAQ-STC Technical Reference Manual 2-44 © National Instruments Corporation...
Page 74: Master/Slave Operation Considerations
DAQ-STC to the slave DAQ-STCs. You may use the RTSI connector to do this. Note You must perform the programming sequence described in section 10.8.1, Programming Clock Distribution, before you execute the sequence given here. © National Instruments Corporation 2-45 DAQ-STC Technical Reference Manual...
Page 75: Analog Input-Related Interrupts
Instruments Application Note 010: Programming Interrupts for Data Acquisition on 80x86-Based Computers. Interrupts related to analog input can be generated on the following analog input conditions: • Error (overrun or overflow) • START • STOP • START1 • START2 DAQ-STC Technical Reference Manual 2-46 © National Instruments Corporation...
Page 76 To acknowledge (and clear): AI_START2_Interrupt_Ack SC_TC To enable: AI_SC_TC_Interrupt_Enable To recognize: AI_SC_TC_St To acknowledge (and clear): AI_SC_TC_Interrupt_Ack FIFO Condition To enable: AI_FIFO_Interrupt_Enable To select condition use: AI_FIFO_Mode To recognize: AI_FIFO_Full_St, AI_FIFO_Half_Full_St, and AI_FIFO_Empty_St © National Instruments Corporation 2-47 DAQ-STC Technical Reference Manual...
Page 77: Bitfield Descriptions
Before setting this bit to 1, make sure that the analog trigger is not being used by any other part of the DAQ-STC. You should not set this bit to 1 in any other case. This bit is cleared automatically. DAQ-STC Technical Reference Manual 2-48 © National Instruments Corporation...
Page 78 You can use AI_End_On_End_Of_Scan and AI_End_On_SC_TC to stop an analog input operation in the continuous acquisition mode. Related bitfields: AI_End_On_End_Of_Scan, AI_End_On_SC_TC, AI_Pre_Trigger. © National Instruments Corporation 2-49 DAQ-STC Technical Reference Manual...
Page 79 Write in: AI_Personal_Register address: 77 This bit determines how the pulsewidths of the CONVERT and PFI2/CONV signals are selected: 0: Selected by AI_CONVERT_Pulse_Width. 1: Selected by AI_CONVERT_Original_Pulse. Related bitfields: AI_CONVERT_Pulse_Width, AI_CONVERT_Original_Pulse. DAQ-STC Technical Reference Manual 2-50 © National Instruments Corporation...
Page 80 Set this bit to 1 in the master ASIC during master/slave trigger. The slave ASIC(s) can then synchronize to the same clock as the master by triggering on the START1 signal that is output from the master. © National Instruments Corporation 2-51 DAQ-STC Technical Reference Manual...
Page 81 This bit arms the DIV counter. The counter remains armed (and the bit remains set) until it is disarmed, either by hardware or by setting AI_Disarm to 1. Related bitfields: AI_DIV_Armed_St, AI_Disarm. DAQ-STC Technical Reference Manual 2-52 © National Instruments Corporation...
Page 82 Setting this bit to 1 disarms the SC, SI, SI2, and DIV counters at the next STOP. You can use this bit to stop the acquisition in continuous acquisition mode. This bit is cleared automatically. Related bitfields: AI_Continuous. © National Instruments Corporation 2-53 DAQ-STC Technical Reference Manual...
Page 83 74 This bit enables the Error interrupt in the secondary interrupt bank: 0: Disabled. 1: Enabled. The Error interrupt is generated on the detection of an overrun or overflow error condition. DAQ-STC Technical Reference Manual 2-54 © National Instruments Corporation...
Page 84 This bit indicates whether the external gate and the software gate are set to enable analog input operation: 0: Pause analog input operation. 1: Enable analog input operation. Related bitfields: AI_External_Gate_Select, AI_Software_Gate. © National Instruments Corporation 2-55 DAQ-STC Technical Reference Manual...
Page 85 LOCALMUX_CLK pulse by 0.5–1.5 AI_OUT_TIMEBASE periods. 1: Pulsewidth is equal to the pulsewidth of the LOCALMUX_CLK read pulse selected by AI_LOCALMUX_CLK_Pulse_Width. EXTMUX_CLK and LOCALMUX_CLK are asserted at the same time. Related bitfields: AI_LOCALMUX_CLK_Pulse_Width. DAQ-STC Technical Reference Manual 2-56 © National Instruments Corporation...
Page 86 This bit reflects the state of the AIFHF pin (after the polarity selection), which indicates the AI data FIFO status: 0: Half-full or less. 1: More than half-full. Related bitfields: AI_FIFO_Flags_Polarity. © National Instruments Corporation 2-57 DAQ-STC Technical Reference Manual...
Page 87 This bit indicates the status of the DMA request (output pin AIFREQ) and the FIFO interrupt: 0: Not asserted. 1: Asserted. AI_FIFO_Mode selects the condition on which to generate the DMA request and FIFO interrupt. Related bitfields: AI_FIFO_Mode. DAQ-STC Technical Reference Manual 2-58 © National Instruments Corporation...
Page 88 Write in: AI_Personal_Register address: 77 This bit selects the pulsewidth of the LOCALMUX_FFRT output signal and the minimum pulsewidth of the LOCALMUX_CLK output signal: 0: LOCALMUX_FFRT is 0.5–1 AI_OUT_TIMEBASE periods and © National Instruments Corporation 2-59 DAQ-STC Technical Reference Manual...
Page 89 1: Error. The overrun error indicates that the ADC interval is not long enough to complete a conversion. This bit can be cleared by setting AI_Error_Interrupt_Ack to 1. Related bitfields: AI_Overrun_Mode, AI_Error_Interrupt_Ack. DAQ-STC Technical Reference Manual 2-60 © National Instruments Corporation...
Page 90 Write in: AI_Output_Control_Register address: 60 This bitfield enables and selects the polarity of the SCAN_IN_PROG output signal: 0: High Z. 1: Ground. 2: Enable, active low. 3: Enable, active high. © National Instruments Corporation 2-61 DAQ-STC Technical Reference Manual...
Page 91 This bit indicates the status of the SC gate if the SC gate is enabled. 0: SC gate blocks external CONVERTs 1: SC gate allows external CONVERTs to pass Related bitfields: AI_SC_Gate_Enable. DAQ-STC Technical Reference Manual 2-62 © National Instruments Corporation...
Page 92 Related Bitfields: AI_SC_Next_Load_Source_St, AI_SC_Load. AI_SC_Next_Load_Source_St bit: 1 type: Read in: AI_Status_2_Register address: 5 This bit indicates the next load source of the SC counter: 0: Load register A. 1: Load register B. © National Instruments Corporation 2-63 DAQ-STC Technical Reference Manual...
Page 93 AI_SC_Save_Trace to 1, this bitfield synchronously latches the contents of the SC counter using the SC source. The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address. Related bitfields: AI_SC_Save_Trace. DAQ-STC Technical Reference Manual 2-64 © National Instruments Corporation...
Page 94 SC_TC interrupts are generated on every SC_TC falling edge unless the pretrigger acquisition mode is selected. In the pretrigger acquisition mode, the first SC_TC falling edge does not generate an interrupt, but subsequent SC_TC falling edges do. © National Instruments Corporation 2-65 DAQ-STC Technical Reference Manual...
Page 95 This bit enables the write switch feature of the SC load registers. Writes to SC load register A are: 0: Unconditionally directed to SC load register A. 1: Directed to the inactive SC load register. DAQ-STC Technical Reference Manual 2-66 © National Instruments Corporation...
Page 96 If the SI counter is armed, this bit indicates whether the SI counter is enabled to count: 0: No. 1: Yes. If the SI counter is disarmed, this bit should be ignored. © National Instruments Corporation 2-67 DAQ-STC Technical Reference Manual...
Page 97 Related Bitfields: AI_SI_Next_Load_Source_St, AI_SI_Load. AI_SI_Next_Load_Source_St bit: 6 type: Read in: AI_Status_2_Register address: 5 This bit indicates the next load source of the SI counter: 0: Load register A. 1: Load register B. DAQ-STC Technical Reference Manual 2-68 © National Instruments Corporation...
Page 98 This bit selects the active edge of the SI source (the signal that is selected by AI_SI_Source_Select): 0: Rising edge. 1: Falling edge. Set this bit to 0 if an internal timebase is used. Related bitfields: AI_SI_Source_Select. © National Instruments Corporation 2-69 DAQ-STC Technical Reference Manual...
Page 99 Setting this bit to 1 causes the SI counter to switch load registers at its next TC. This action is internally synchronized to the falling edge of the internal signal SI_CLK. You can use this bit for scan rate change during an acquisition. This bit is cleared automatically. DAQ-STC Technical Reference Manual 2-70 © National Instruments Corporation...
Page 100 This bitfield is load register A for the SI2 counter. If load register A is the selected SI2 load register, the SI2 counter loads the value contained in this bitfield on AI_SI2_Load and on SI2_TC. Related Bitfields: AI_SI2_Next_Load_Source_St, AI_SI2_Load. © National Instruments Corporation 2-71 DAQ-STC Technical Reference Manual...
Page 101 Read in: AI_SI2_Save_Register address: 25 This bitfield reflects the contents of the SI2 counter. Reading from this bitfield while the SI2 counter is counting may result in an erroneous value. DAQ-STC Technical Reference Manual 2-72 © National Instruments Corporation...
Page 102 Related bitfields: AI_External_Gate_Mode. AI_Source_Divide_By_2 bit: 6 type: Write in: Clock_and_FOUT_Register address: 56 This bit determines the frequency of the internal timebase AI_IN_TIMEBASE1: 0: Same as IN_TIMEBASE. 1: IN_TIMEBASE divided by two. © National Instruments Corporation 2-73 DAQ-STC Technical Reference Manual...
Page 103 Related bitfields: BD_7_Pin_Dir, AI_Trigger_Length. AI_START_Polarity bit: 15 type: Write in: AI_START_STOP_Select_Register address: 62 This bit determines the polarity of START trigger: 0: Active high or rising edge. 1: Active low or falling edge. DAQ-STC Technical Reference Manual 2-74 © National Instruments Corporation...
Page 104 A valid START trigger is one that is received while the SC counter is enabled to count. You can clear this bit by setting AI_START_Interrupt_Ack to 1. Refer to Table 8-2, Interrupt Condition Summary, for more information. © National Instruments Corporation 2-75 DAQ-STC Technical Reference Manual...
Page 105 Use this bit if you want the same START1 trigger to start several activities. First, disable START1 by setting this bit to 1, do the necessary programming on all DAQ-STCs, and then enable START1 by setting this bit to 0. DAQ-STC Technical Reference Manual 2-76 © National Instruments Corporation...
Page 106 Setting this bit to 1 sends a START1 trigger to the counters if the START1 software strobe is selected (AI_START1_Select is set to 0). This bit is cleared automatically. Related bitfields: AI_START1_Select. © National Instruments Corporation 2-77 DAQ-STC Technical Reference Manual...
Page 107 CONVERT source). You must set this bit to 1 if AI_START1_Select is set to 0. You should set this bit to 0 if the ASIC is a START1 slave to another DAQ-STC. Related bitfields: AI_START1_Select. DAQ-STC Technical Reference Manual 2-78 © National Instruments Corporation...
Page 108 Setting this bit to 1 sends a START2 trigger to the SC counter if the START2 software strobe is selected (AI_START2_Select is set to 0). This bit is cleared automatically. Related bitfields: AI_START2_Select. © National Instruments Corporation 2-79 DAQ-STC Technical Reference Manual...
Page 109 CONVERT source). You must set this bit to 1 if AI_START2_Select is set to 0. You should set this bit to 0 if the ASIC is a START2 slave to another DAQ-STC. Related bitfields: AI_START2_Select. DAQ-STC Technical Reference Manual 2-80 © National Instruments Corporation...
Page 110 Setting this bit to 1 sends a STOP trigger to the counters if the STOP software strobe is selected (AI_STOP_Select is set to 0). This bit is cleared automatically. Related bitfields: AI_STOP_Select. © National Instruments Corporation 2-81 DAQ-STC Technical Reference Manual...
Page 111 A valid STOP trigger is one that is received while the SC counter is enabled to count yet after a valid START. This bit is cleared by setting AI_STOP_Interrupt_Ack to 1. Related bitfields: AI_STOP_Interrupt_Ack. Refer to Table 8-2, Interrupt Condition Summary, for more information. DAQ-STC Technical Reference Manual 2-82 © National Instruments Corporation...
Page 112 Set this bit to 1 only if AI_Continuous is set to 0. Set this bit to 0 for a single-finite-pretrigger-infinite-posttrigger analog input operation. Related bitfields: AI_Continuous. Note If the operation is halted by AI_End_On_End_Of_Scan or AI_End_On_SC_TC, the counters are disarmed regardless of the state of this bit. © National Instruments Corporation 2-83 DAQ-STC Technical Reference Manual...
Page 113: Timing Diagrams
AI_SI2_Source_Select is 0, the reference pin is determined by AI_SI_Source_Select. If AI_SI2_Source_Select is 1, the reference pin is OSC or RTSI_OSC, depending on which clock mode you choose in RTSI_Clock_Mode. 1–10 PFI<0..9> DAQ-STC Technical Reference Manual 2-84 © National Instruments Corporation...
Page 114: Out_Clk
RTSI_OSC input, respectively, depending on which clock mode you choose in RTSI_Clock_Mode. If the output clock is set for divide-by-two operation, each edge of OUT_CLK represents a rising edge of OSC (or RTSI_OSC). Otherwise, OUT_CLK and OSC (or RTSI_OSC) are identical. © National Instruments Corporation 2-85 DAQ-STC Technical Reference Manual...
Page 115: Basic Analog Input Timing
(external convert) Tcconvd OUT_CLK to CONVERT deasserted Toconv (0.5, 1.5) (1, 2) CONVERT width Tsoc — SOC pulsewidth Tsoceoc — SOC precedes EOC Teoc — EOC pulsewidth Teocshft EOC to SHIFTIN asserted DAQ-STC Technical Reference Manual 2-86 © National Instruments Corporation...
Page 116 SHIFTIN, which is asserted on the active edge of EOC. SHIFTIN is held for a falling clock edge and then one or two rising edges (refer to AI_SHIFTIN_Pulse_Width). © National Instruments Corporation 2-87 DAQ-STC Technical Reference Manual...
Page 117: Data Fifos
Tflgreq FIFO flag change to AIFREQ change Teodreq End of acquisition to AIFREQ change Tshft — Last SC_TC to SHIFTIN All timing values are in nanoseconds. Figure 2-17. Data FIFO Timing DAQ-STC Technical Reference Manual 2-88 © National Instruments Corporation...
Page 118: Configuration Memory
The EXTMUX_CLK increments the external multiplexer and is generated once for every CONVERT pulse. The DIV counter is used to count the CONVERT pulses and allows the LOCALMUX_CLK signal to be generated during the DIV TC. © National Instruments Corporation 2-89 DAQ-STC Technical Reference Manual...
Page 119: Table 2-4. Configuration Memory Timing
LOCALMUX_CLK signal is asserted by the leading edge of CONVERT and is held for either two or four output clock edges, regardless of polarity, and then until the active edge of SOC DAQ-STC Technical Reference Manual 2-90 © National Instruments Corporation...
Page 120: Maximum Rate Analog Input
Up to 10 MS/s is achievable with a 20 MHz oscillator, and up to 5 MS/s is achievable with a 10 MHz oscillator. © National Instruments Corporation 2-91 DAQ-STC Technical Reference Manual...
Page 121: External Convert Source
CONVERT_SRC is equal to OSC (or RTSI_OSC). In the external CONVERT mode, CONVERT_SRC is selected to be one of the PFI<0..9> or RTSI_TRIGGER<0..6> inputs. The timing for CONVERT_SRC in the external CONVERT mode is shown in Figure 2-20. DAQ-STC Technical Reference Manual 2-92 © National Instruments Corporation...
Page 122: External Triggers
CONVERT or external CONVERT. In the internal CONVERT mode, the external signal synchronizes to the inactive edge of the SI2 source. In the external CONVERT mode, the external signal synchronizes to the active edge of CONVERT_SRC. © National Instruments Corporation 2-93 DAQ-STC Technical Reference Manual...
Page 123: Figure 2-21. External Trigger Timing, Asynchronous Level
START1 START2 START STOP Figure 2-21. External Trigger Timing, Asynchronous Level Ts_stop Ts_strt1 Ts_strt2 Ts_strt CONVERT_SRC Tstrt1 START1 Tstrt2 START2 Tstrt START Tstop STOP Figure 2-22. External Trigger Timing, Asynchronous Edge DAQ-STC Technical Reference Manual 2-94 © National Instruments Corporation...
Page 124: Figure 2-23. External Trigger Timing, Synchronous Level Internal Convert Mode
Figure 2-23. External Trigger Timing, Synchronous Level, Internal CONVERT Mode Ts_stop Ts_strt1 Ts_strt2 Ts_strt SI2 Source Th_strt1 START1 Th_strt2 START2 Th_strt START Th_stop STOP Figure 2-24. External Trigger Timing, Synchronous Edge, Internal CONVERT Mode © National Instruments Corporation 2-95 DAQ-STC Technical Reference Manual...
Page 125: Table 2-5. External Analog Input Timing
(level mode) Ts_strt2 31 (34) — START2 setup to CONVERT_SRC Tstrt2 — START2 pulsewidth (edge mode) START2 hold from CONVERT_SRC Th_strt2 — (level mode) Ts_strt 29 (32) — START setup to CONVERT_SRC DAQ-STC Technical Reference Manual 2-96 © National Instruments Corporation...
Page 126: Trigger Output
In the internal CONVERT mode, the inactive edge of the SI2 source that recognizes the external trigger generates the output. Figure 2-27 shows the propagation delays for START1. Figure 2-28 shows the propagation delays for START2. © National Instruments Corporation 2-97 DAQ-STC Technical Reference Manual...
Page 127: Figure 2-27. Start1 Delays, Synchronous Mode, Internal Convert
Figure 2-29 shows the propagation delays for START1. Figure 2-30 shows the propagation delays for START2. START1 CONVERT_SRC Tpfi PFI0/AI_START1 Trtsi RTSI_TRIGGER<0..6> Tbrd RTSI_BRD<0..3> Figure 2-29. START1 Delays, Synchronous Mode, External CONVERT DAQ-STC Technical Reference Manual 2-98 © National Instruments Corporation...
Page 128: Table 2-6. Start1 And Start2 Timing, Synchronous Mode
Figure 2-31 shows the propagation delays for START1. Figure 2-32 shows the propagation delays for START2. START1 Tpfi PFI0/AI_START1 Trtsi RTSI_TRIGGER<0..6> Tbrd RTSI_BRD<0..3> Figure 2-31. START1 Delays, Asynchronous Mode © National Instruments Corporation 2-99 DAQ-STC Technical Reference Manual...
Page 129: Start Trigger And Scan_In_Prog Assertion
PFI7/AI_START, or on the RTSI_BRD<2..3> outputs. The timing for START and SCAN_IN_PROG depends on whether you select internal CONVERT or external CONVERT, using AI_CONVERT_Source_Select. This section assumes AI_Delay_Start is set to 0. DAQ-STC Technical Reference Manual 2-100 © National Instruments Corporation...
Page 130: Figure 2-33. Start Delays, Internal Convert
Tscan SI2 Source to SCAN_IN_PROG SI2 Source to PFI output Tspfi (SCAN_IN_PROG) SI2 Source to BRD output Tsbrd (SCAN_IN_PROG) All timing values are in nanoseconds. Figure 2-33. START Delays, Internal CONVERT © National Instruments Corporation 2-101 DAQ-STC Technical Reference Manual...
Page 131: Figure 2-34. Start Delays, External Convert
CONVERT_SRC to BRD output (START) Tscan CONVERT_SRC to SCAN_IN_PROG CONVERT_SRC to PFI output Tspfi (SCAN_IN_PROG) CONVERT_SRC to BRD output Tsbrd (SCAN_IN_PROG) All timing values are in nanoseconds. Figure 2-34. START Delays, External CONVERT DAQ-STC Technical Reference Manual 2-102 © National Instruments Corporation...
Page 132: Scan_In_Prog Deassertion
You can output the STOP trigger on the dedicated output AI_STOP_OUT or on the RTSI_BRD<0..1> pins. The timing for STOP depends on whether you select synchronous mode or asynchronous mode, using AI_STOP_Sync. © National Instruments Corporation 2-103 DAQ-STC Technical Reference Manual...
Page 133: Figure 2-36. Stop Delay, Synchronous Mode
Tstst Tstst AI_STOP_OUT Tbrd Tbrd RTSI_BRD<0..1> Name Description Minimum Maximum Tstst STOP to AI_STOP_OUT Tbrd STOP to BRD output All timing values are in nanoseconds. Figure 2-37. STOP Delay, Asynchronous Mode DAQ-STC Technical Reference Manual 2-104 © National Instruments Corporation...
Page 134: Counter Outputs
Figure 2-39 shows the delays associated with the SI_TC signal. SI Source SI_TC Name Description Minimum Maximum SI Source to SI_TC All timing values are in nanoseconds. Figure 2-39. SI_TC Delay © National Instruments Corporation 2-105 DAQ-STC Technical Reference Manual...
Page 135: Div_Tc
The timing for this mode is shown in Figure 2-41. Tst1st START1 Ttcst2 START2 Tstc Tstpst Tstst START Tstpc Tst2stp STOP CONVERT SC_TC Figure 2-41. Interval Scanning Mode Timing DAQ-STC Technical Reference Manual 2-106 © National Instruments Corporation...
Page 136: Table 2-8. Interval Scanning Mode Timing
The external signal must meet the setup and pulsewidth requirements that are indicated in section 2.7.7, External Triggers, in order to guarantee recognition by the AITM. The external signal can be passed through the © National Instruments Corporation 2-107 DAQ-STC Technical Reference Manual...
Page 137 STOP trigger. Otherwise, the following scan will be the first posttrigger point. Therefore, all of the scans in the pretrigger buffer will have completed before the assertion of the START2 signal. DAQ-STC Technical Reference Manual 2-108 © National Instruments Corporation...
Page 138: External Gating
Maximum Tgtclki — External gate to SI2_Source setup internal External gate to CONVERT_SRC setup Tgtclke — external All timing values are in nanoseconds. Figure 2-42. Free-Run Gating Mode Timing, Internal CONVERT © National Instruments Corporation 2-109 DAQ-STC Technical Reference Manual...
Page 139: Figure 2-43. Free-Run Gating Mode Timing, External Convert
The shaded areas in Figures 2-42 and 2-43 indicate where those signals would be asserted had they not been gated off. The recognition of the external gate signal in the free-run gating mode is relative to the START signal. DAQ-STC Technical Reference Manual 2-110 © National Instruments Corporation...
Page 140: Figure 2-44. Halt-Gating Mode Timing, Internal Convert
START signal, which begins the next scan. The timing for the halt-gating mode with an external CONVERT or with SI2 source and SI source as different signals is more complicated and is, therefore, omitted. © National Instruments Corporation 2-111 DAQ-STC Technical Reference Manual...
Page 141: Detailed Description
SI2 Load B SI2 Load A SC_TC LOCALMUX_CLK SI2_LOAD_SRC Output START1 SI2_CE EXTMUX_CLK Control START SI2_LOAD SCAN_IN_PROG SI2_TC SI2_CLK SI2 Counter STOP Control SI2_TC Logic SC_TC SI_SRC Figure 2-45. AITM Block Diagram DAQ-STC Technical Reference Manual 2-112 © National Instruments Corporation...
Page 142: Internal Signals And Operation
AI FIFO Request— This signal generates AIFREQ. AI_IN_TIMEBASE1 Internal Timebase for the Analog Input Module—This signal can be selected to be the same as IN_TIMEBASE, or it can be IN_TIMEBASE divided by two. Related bitfields: AI_Source_Divide_By_2. © National Instruments Corporation 2-113 DAQ-STC Technical Reference Manual...
Page 143 Related bitfields: AI_External_Gate_Mode, AI_External_Gate_Select, AI_External_Gate_St, AI_Software_Gate. FSCLK Fast Sample Clock—This signal is the output of the CONVERT selector, after polarity selection. Related bitfields: AI_CONVERT_Source_Select, AI_CONVERT_Polarity_Select. DAQ-STC Technical Reference Manual 2-114 © National Instruments Corporation...
Page 144 The delay gate is provided so that signals synchronized to FSCLK have sufficient time to settle to a known state before being used by SCLK. © National Instruments Corporation 2-115 DAQ-STC Technical Reference Manual...
Page 145 SI2_CLK is the same as SI2_SRC. Related bitfields: AI_SI2_Load. SI2_LOAD SI2 Load—This signal pulses to load the value from the selected SI2 load register into the SI2 counter. Related bitfields: AI_SI2_Load. DAQ-STC Technical Reference Manual 2-116 © National Instruments Corporation...
Page 146 START1 Synchronized to SI_SRC—This signal is generated by the hardware by passing the output of the AI_START1 selector through polarity selection, edge detection, and synchronization (synchronized to the falling edge of SI_SRC). © National Instruments Corporation 2-117 DAQ-STC Technical Reference Manual...
Page 147 It can be programmed to be edge or level sensitive and can be synchronized to FSC_SRC. START2 is selected using AI_START2_Select. Related bitfields: AI_START2_Select, AI_START2_Pulse, AI_START2_Edge, AI_START2_Sync. DAQ-STC Technical Reference Manual 2-118 © National Instruments Corporation...
Page 148: Trigger Selection And Conditioning
SI_SRC and SCLK signals is a 20-to-1 multiplexer followed by an exclusive OR gate for polarity selection. The routing logic for the trigger signals START and STOP has additional controls for edge detection and synchronization as shown in Figure 2-46. © National Instruments Corporation 2-119 DAQ-STC Technical Reference Manual...
Page 149: Figure 2-46. Start And Stop Routing Logic
PFI<0..9> EDGE 20 to 1 MOUT* RTSI_TRIGGER<0..6> POLARITY INT_CLK* SEL<0..4> 2STAGE EXT_CLK EXT_TIMING INT_CLK DELAY_EXT_CLK NOTE: Does not show all possible selections. DELAY EXT_TIMING Figure 2-47. START1 and START2 Routing Logic DAQ-STC Technical Reference Manual 2-120 © National Instruments Corporation...
Page 150: Table 2-10. Pfi Selectors
— PFI<0..9> RTSI<0..6> — — Key: AI_STP The input AI_STOP_IN AI_TB1 The internal analog input signal AI_IN_TIMEBASE1 GOUT0 The G_OUT signal from general-purpose counter 0 Software strobe The internal signal IN_TIMEBASE2 © National Instruments Corporation 2-121 DAQ-STC Technical Reference Manual...
Page 151: Using Edge Detection
DAQ-STC operating from the same source clock and timing can be guaranteed. START is used by the SC counter and is, therefore, synchronized to SC_SRC. DAQ-STC Technical Reference Manual 2-122 © National Instruments Corporation...
Page 152: Analog Input Counters
The state diagrams for the control circuits are discussed below. © National Instruments Corporation 2-123 DAQ-STC Technical Reference Manual...
Page 153: Sc Counter
SC source (AI_CONVERT_Source_Select is set to 0), SCKG becomes the sample interval counter TC signal (SI2_TC). If a different source is selected for the SC counter (AI_CONVERT_Source_Select is not set to 0) SCKG = 1. DAQ-STC Technical Reference Manual 2-124 © National Instruments Corporation...
Page 154: Figure 2-49. Sc Control Circuit State Transitions
SC_LOAD = GL + AI_SC_Load SC_CE = BL (EXT_GATE) (PCNT(n) + CNT(n) + PCNT(n+1) + CNT(n+1)) SC_DISARM = CNT(n) WAIT(n+1) (H + I + N) Figure 2-49. SC Control Circuit State Transitions © National Instruments Corporation 2-125 DAQ-STC Technical Reference Manual...
Page 155: Si Counter
The SI disarm signal (SI_DISARM) clears the AI_SI_Arm bit in the register map. SI_DISARM asserts on the transition from the CNT1 to the WAIT1 state when AI_End_On_End_Of_Scan, AI_End_On_SC_TC, or AI_Trigger_Once is high. DAQ-STC Technical Reference Manual 2-126 © National Instruments Corporation...
Page 156: Si2 Counter
START to be asserted. Once START is received, the counter transitions to state CNT and begins counting. When STOP is received, the counter returns to the WAIT2 state to wait for another START. © National Instruments Corporation 2-127 DAQ-STC Technical Reference Manual...
Page 157: Div Counter
During normal operation, the DIV counter will synchronously reload from the load register following DIV_TC. The DIV control circuit generates the count enable signals. DAQ-STC Technical Reference Manual 2-128 © National Instruments Corporation...
Page 158: Div Control
The DIV disarm signal (DIV_DISARM) clears the AI_DIV_Arm bit in the register map. DIV_DISARM asserts on the transition from the CNT state to the WAIT state when AI_End_On_End_Of_Scan, AI_End_On_SC_TC, or AI_Trigger_Once is high. © National Instruments Corporation 2-129 DAQ-STC Technical Reference Manual...
Page 159: Interrupt Control
SC_TC falling edges that occur after the pretrigger count requirement has been satisfied. That is, in the pretrigger acquisition mode, the first SC_TC does not generate an interrupt. DAQ-STC Technical Reference Manual 2-130 © National Instruments Corporation...
Page 160: Table 2-11. Analog Input Interrupts
In the pretrigger acquisition mode, the first SC_TC falling edge does not generate an interrupt, but subsequent SC_TC falling edges do. FIFO interrupt Interrupt generated on the FIFO condition indicated by AI_FIFO_Mode. © National Instruments Corporation 2-131 DAQ-STC Technical Reference Manual...
Page 161: Error Detection
The error-detection circuit is armed on each SC_TC. If a software clear (AI_SC_TC_Interrupt_Ack) does not occur before the next SC_TC, the error-detection circuit latches an error condition. DAQ-STC Technical Reference Manual 2-132 © National Instruments Corporation...
Page 162: Nominal Signal Pulsewidths
(1 or 2) to SOC EXTMUX_CLK — LocalMuxClk or 5 SCAN_IN_PROG From START to last SOC — EXTSTROBE Eight cyles of 1.2 µs or 10 µs, — software toggle LOCALMUX_FFRT — © National Instruments Corporation 2-133 DAQ-STC Technical Reference Manual...
Page 163: Analog Output Timing/Control
10 PFI signals, seven RTSI trigger signals, or other internal signals. For more information about devices with which the AOTM can work, read section 1.1.2, Analog Output Application in Chapter 1, Introduction. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 164: Programming The Aotm
Input clock sources and triggers from PFI<0..9> and RTSI_TRIGGER<0..6> – Output the internally generated update and trigger signals to the board • Programmable polarities for external UPDATE and external START1 input • Synchronously change the update interval DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 165 Interrupts based on update, triggers, error conditions, and FIFO flags – FIFO-flag-based request signal to simplify DMA or interrupt request logic – Bus cycle extension for D/A bus contention case and slow DAC write case © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 166: Simplified Model
DAC) are associated with CPU-driven analog output. The CPU asserts CPUDACREQ to request a write to one of the output channels, and CPUDACWR is the actual write signal. AOFFRT (AO data FIFO retransmit) retransmits the analog output FIFO DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 167: Analog Output Functions
UPDATE mode, the rate at which to output the points. In the CPU-driven mode, the CPU alone determines when the points are output. In some cases, DAQ-STC-driven and CPU-driven analog output may occur simultaneously on different channels, in which case arbitration is provided by the DAQ-STC. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 168: Daq-Stc-Driven Analog Output
In the slow interface mode, CHRDY_OUT deasserts until the write to the DAC is complete. In the fast interface mode, CHRDY_OUT deasserts only until the write to the DAC is initiated, maximizing bus bandwidth. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 169: Daq-Stc And Cpu Conflict
Figure 3-4 shows a DAQ-STC-driven analog output sequence on a board configured with eight channels, interrupted by a CPU-driven analog output to DAC number 9. UPDATE TMRDACWR AO_ADDR<3..0> CPUDACREQ CHRDY_OUT CPUDACWR Figure 3-4. DAQ-STC and CPU Conflict © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 170: Dac Interface
DMA request or FIFO interrupt on one of four different FIFO flag conditions, including assert on FIFO empty, assert on FIFO less than half-full, assert on FIFO not full, and assert on FIFO less than half-full and deassert on FIFO full. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 171: Figure 3-5. Fifo Data Interface
Figure 3-6, the UC_TC (UC counter TC) signal pulses at the end of each buffer. The relationship between the UPDATE pulses and the UC counter is discussed in section 3.4.5, Buffer Timing and Control for Primary Analog Output. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 172: Serial Link Data Interface
Once the serial link data transfer completes, AOFEF is released, allowing the write to occur. UPDATE AOFEF TMRDACREQ TMRDACWR Figure 3-7. Serial Link Data Interface DAQ-STC Technical Reference Manual 3-10 © National Instruments Corporation...
Page 173: Unbuffered Data Interface
(A) gives the delay from START1 to the first UPDATE. The second parameter (B) gives the delay between UPDATE pulses. Figure 3-9 shows a sequence of UPDATE pulses and indicates the timing parameters that are available. © National Instruments Corporation 3-11 DAQ-STC Technical Reference Manual...
Page 174: External Update
MISBs. The DAQ-STC provides direct hardware support for the output of a single MISB, output of one MISB followed immediately by a second MISB, and output of two MISBs which alternate. The DAQ-STC can generate even more complex waveforms DAQ-STC Technical Reference Manual 3-12 © National Instruments Corporation...
Page 175: Single-Buffer Mode
MISB to terminate at the next UC_TC, corresponding to the end of the current buffer. The End_On_BC_TC command causes the MISB to terminate at the next BC_TC. The AO_Reset causes the MISB to terminate immediately. © National Instruments Corporation 3-13 DAQ-STC Technical Reference Manual...
Page 176: Waveform Staging
MISB, that is, at BC_TC. This arrangement allows the software a maximum latency of up to the duration of the MISB in progress to finish loading the parameters for the next MISB into the alternate load register set. DAQ-STC Technical Reference Manual 3-14 © National Instruments Corporation...
Page 177: Mute Buffers
The master ASIC delays recognition of the START1 trigger by one source period to allow the slave ASICs adequate time to receive the trigger. On the © National Instruments Corporation 3-15 DAQ-STC Technical Reference Manual...
Page 178: Secondary Analog Output
AO data FIFO is empty. The input polarity is selectable, and the input state can be directly observed in one of the status registers. Source: AO data FIFO. Related bitfields: AO_FIFO_Flags_Polarity, AO_FIFO_Empty_St. DAQ-STC Technical Reference Manual 3-16 © National Instruments Corporation...
Page 179 FIFO, deassert on full FIFO. Output polarity is selectable. Destination: DMA Controller or CPU. Related bitfields: AO_AOFREQ_Polarity, AO_AOFREQ_Enable, AO_FIFO_Mode. BC_TC O4TU The BC Counter Terminal Count Signal—Output polarity is active high. Related bitfields: Misc_Counter_TCs_Output_Enable. © National Instruments Corporation 3-17 DAQ-STC Technical Reference Manual...
Page 180 LDAC<0..1> are programmed to output either UPDATE or UPDATE2. In the immediate update mode, LDAC<0..1> are inverted versions of the DAC write signals TMRDACWR and CPUDACWR. Output polarity is active low. Destination: DACs. Related bitfields: AO_LDACi_Source_Select, AO_DACi_Update_Mode. DAQ-STC Technical Reference Manual 3-18 © National Instruments Corporation...
Page 181 Destination: DACs. Related bitfields: AO_DMA_PIO_Control, AO_FIFO_Enable, AO_Not_An_UPDATE, AO_TMRDACWR_Pulse_Width, AO_TMRDACWRs_In_Progress_St. UC_TC P4TU The UC Counter Terminal Count Signal—Output polarity is active high. Related bitfields: Misc_Counter_TCs_Output_Enable. © National Instruments Corporation 3-19 DAQ-STC Technical Reference Manual...
Page 182: Programming Information
For example, in the following pseudocode, the first bitfield assignment must be performed first; the second and third assignments may then be executed in any order; but the fourth bitfield assignment must be executed after the second and third DAQ-STC Technical Reference Manual 3-20 © National Instruments Corporation...
Page 183: Overview
Assume the primary analog output section of the DAQ-STC was set up to perform an unknown operation. The object is to stop any activities in progress. Function AO_Reset_All Begin critical section; AO_Configuration_Start = 1; ∑ AO_Disarm = 1; ∑ AO_Personal_Register = 0; AO_Command_1_Register = 0; © National Instruments Corporation 3-21 DAQ-STC Technical Reference Manual...
Page 184: Board Power-Up Initialization
DAQ-STC. If you are programming a DAQ-STC that is a part of a data acquisition system, the document describing the register-level programming for that system should contain information about the proper selections to make in this function. DAQ-STC Technical Reference Manual 3-22 © National Instruments Corporation...
Page 185: Trigger Signals
AO_Configuration_Start = 1; If (local buffer mode with pauses) OR (continuous mode) OR (waveform staging) then AO_Trigger_Once = 0; Else AO_Trigger_Once = 1; If (software triggered) then AO_START1_Select = 0; AO_START1_Polarity = 0; © National Instruments Corporation 3-23 DAQ-STC Technical Reference Manual...
Page 186: Number Of Buffers
/*contains the number of updates in each buffer of the MISB*/ new_mute_flag /*indicates whether the MISB will be muted (1 indicates muting)*/ Function AO_Counting Begin critical section; AO_Configuration_Start = 1; Declare variables DAQ-STC Technical Reference Manual 3-24 © National Instruments Corporation...
Page 187 AO_UC_Load_A = number of updates in each buffer - 1; AO_BC_Load_B = number of buffer repetitions in pause MISB - 1; AO_UC_Load_B = number of updates in each buffer of pause MISB - 1; AO_BC_Reload_Mode = 1; AO_UC_Switch_Load_Every_BC_TC = 1; © National Instruments Corporation 3-25 DAQ-STC Technical Reference Manual...
Page 188: Update Selection
If (internal UPDATE mode) then AO_BC_Gate_Enable = 0; AO_UPDATE_Source_Select = 0; AO_UPDATE_Source_Polarity = 0; If (UI source is AO_IN_TIMEBASE1) then AO_UI_Source_Select = 0; AO_UI_Source_Polarity = 0; Else if (UI source is IN_TIMEBASE2) then DAQ-STC Technical Reference Manual 3-26 © National Instruments Corporation...
Page 189 If (local buffer mode with pauses) then AO_UI_Load_B = number of clocks between each update in the mute MISB - 1; AO_UI_Reload_Mode = 7; Else if (UPDATE source is the GOUT1 signal from general-purpose counter 1) then © National Instruments Corporation 3-27 DAQ-STC Technical Reference Manual...
Page 190: Channel Select
AO_Configuration_Start = 1; If (single channel) then AO_Multiple_Channels = 0; AO_Number_Of_Channels = output channel number; Else AO_Multiple_Channels = 1; AO_Number_Of_Channels = number of output channels - 1; AO_Configuration_End = 1; End critical section; DAQ-STC Technical Reference Manual 3-28 © National Instruments Corporation...
Page 191: Ldac Source And Update Mode
Use this function to select the data FIFO condition on which interrupt or DMA requests will be generated, if you want the DAQ-STC to generate them. You can also use this function to program FIFO control for local buffer mode, with or without pauses. © National Instruments Corporation 3-29 DAQ-STC Technical Reference Manual...
Page 192: Enable Interrupts
Interrupts. 3.6.1.12 Arming Use this function to arm the analog output counters and to preload the DACs with the first analog output value. Function AO_Arming Begin critical section; AO_Not_An_UPDATE = 1; DAQ-STC Technical Reference Manual 3-30 © National Instruments Corporation...
Page 193: Starting The Waveform
/*Refer to section 10.8.1, Programming Clock Distribution, to set up your timebase*/ Call AO_Reset_All Call AO_Board_Personalize Call AO_Hardware_Gating Call AO_Triggering Call AO_Counting Call AO_Updating Call AO_Channels Call AO_LDAC_Source_And_Update_Mode Call AO_Errors_To_Stop_On Call AO_FIFO Call AO_Interrupt_Install © National Instruments Corporation 3-31 DAQ-STC Technical Reference Manual...
Page 194: Waveform Staging For Primary Analog Output
These variables were first introduced in the AO_Counting function. Function AO_Staged_ISR Declare variables /*number of buffer iterations*/ new_bc_ticks /*number of updates in each buffer*/ new_uc_ticks DAQ-STC Technical Reference Manual 3-32 © National Instruments Corporation...
Page 195 AO_BC_Load_A = - 1; new_bc_ticks AO_UC_Load_A = - 1; new_uc_ticks AO_UI_Load_A = - 1; new_ui_ticks AO_Mute_A = new_mute If ( is 2) then ao_shut_down_isr AO_UC_Load_B = - 1; old_stage_uc_ticks = A; ao_last_load_register © National Instruments Corporation 3-33 DAQ-STC Technical Reference Manual...
Page 196: Changing Update Rate During An Output Operation For Primary Analog Output Group
Else if (change update rate at the end of the current MISB) then AO_UI_Switch_Load_On_BC_TC = 1; = B; ao_last_load_register Else Inform user that rate change is impossible at this time; Else DAQ-STC Technical Reference Manual 3-34 © National Instruments Corporation...
Page 197: Master/Slave Operation Considerations For Primary Analog
The DAQ-STC is designed to be used primarily with a system that supports interrupts. This section contains instructions on programming the DAQ-STC when it is used in an environment that supports interrupts. © National Instruments Corporation 3-35 DAQ-STC Technical Reference Manual...
Page 198 However, your system will be devoted entirely to one application. Information on interrupts and polling can be found in the National Instruments Application Note 010: Programming Interrupts for Data Acquisition on 80x86-Based Computers.
Page 199 The documentation concerning these interrupts can be ignored. To select interrupt output polarity, use Interrupt_Output_Polarity. This selection depends on the board hardware design. Pass_Through_1_Interrupt is also in interrupt group B. © National Instruments Corporation 3-37 DAQ-STC Technical Reference Manual...
Page 200: Programming For A Secondary Analog Output Group Operation
AO2_Board_Personalize secondary analog output module of the DAQ-STC into a known state. You can then program the secondary analog output module for any desired operation. DAQ-STC Technical Reference Manual 3-38 © National Instruments Corporation...
Page 201: Board Power-Up Initialization
AO_UI2_External_Gate_Select = 1 through 10 (PFI<0..9>) or 11 through 17 (RTSI_TRIGGER<0..6>); AO_UI2_External_Gate_Polarity = 0 (active high; high enables operation) or 1 (active low; low enables operation); Else AO_UI2_External_Gate_Enable = 0; End critical section; © National Instruments Corporation 3-39 DAQ-STC Technical Reference Manual...
Page 202: Software Gate Operation
/*Contains the number of clocks between updates*/ ui2_ticks The variable introduced in this function will be used later in the ao2_last_load_register waveform staging ( ) and change update rate during an output operation AO2_Staged_ISR AO2_Rate_Change DAQ-STC Technical Reference Manual 3-40 © National Instruments Corporation...
Page 203: Arming
3.6.6.9 Secondary Analog Output Program Use this sequence of functions to program the AOTM for any secondary analog output operation. /*Refer to section 10.8.1, Programming Clock Distribution, to set up your timebase*/ Call AO2_Reset_All © National Instruments Corporation 3-41 DAQ-STC Technical Reference Manual...
Page 204: Waveform Staging For Secondary Analog Output
These variables were first introduced in the AO2_Counting functions. AO2_Updating Function AO2_Staged_ISR Declare variable DAQ-STC Technical Reference Manual 3-42 © National Instruments Corporation...
Page 205 Σ AO_UI2_Switch_Load_Next_TC = 1; = B; ao2_last_load_register Else If ( is not 0) then new_ticks AO_UI2_Load_A - 1; new_ticks Σ AO_UI2_Switch_Load_Next_TC = 1; Else AO_UI2_Load_A = 0xFFFF; Σ AO_UI2_Switch_Load_Next_TC = 1; © National Instruments Corporation 3-43 DAQ-STC Technical Reference Manual...
Page 206: Changing Update Rate During An Output Operation For Secondary Analog Output
If (AO2_UI_Next_Load_Source_St is 1) then AO_UI2_Load_A = number of clocks between updates - 1; Σ AO_UI2_Switch_Load_Next_TC = 1; = A; ao2_last_load_register Else Inform user that rate change is impossible at this time; DAQ-STC Technical Reference Manual 3-44 © National Instruments Corporation...
Page 207: Master/Slave Operation Considerations For Secondary Analog Output
Before setting this bit to 1, make sure that the analog trigger is not being used by some other part of the DAQ-STC. This bit should not be set to 1 in any other case. This bit is cleared automatically. © National Instruments Corporation 3-45 DAQ-STC Technical Reference Manual...
Page 208 Enabling the BC_GATE allows external UPDATE pulses to pass only when the BC counter is enabled to count. You should set this bit to 0 in the internal UPDATE mode (AO_UPDATE_Source_Select is set to 0) and to 1 otherwise. Related bitfields: AO_UPDATE_Source_Select. DAQ-STC Technical Reference Manual 3-46 © National Instruments Corporation...
Page 209 BC counter loads the value contained in this bitfield on AO_BC_Load and on BC_TC. The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address. Related Bitfields: AO_BC_Next_Load_Source_St, AO_BC_Load. © National Instruments Corporation 3-47 DAQ-STC Technical Reference Manual...
Page 210 Setting this bit to 1 causes the BC save register to latch the BC counter value at the next BC_CLK falling edge. Setting this bit to 0 causes the BC save register to trace the BC counter. DAQ-STC Technical Reference Manual 3-48 © National Instruments Corporation...
Page 211 A BC_TC error occurs if AO_BC_TC_Interrupt_Ack is not set between two BC TCs. This allows you to detect large interrupt latencies and potential problems associated with them. To clear this bit, set AO_BC_TC_Error_Confirm to 1. Related bitfields: AO_BC_TC_Interrupt_Ack, AO_BC_TC_Error_Confirm. © National Instruments Corporation 3-49 DAQ-STC Technical Reference Manual...
Page 212 Table 8-2, Interrupt Condition Summary, for more information. AO_BC_TC_Trigger_Error_Confirm bit: 3 type: Strobe in: Interrupt_B_Ack_Register address: 3 Setting this bit to 1 clears AO_BC_TC_Trigger_Error_St. This bit is cleared automatically. Related bitfields: AO_BC_TC_Trigger_Error_St. DAQ-STC Technical Reference Manual 3-50 © National Instruments Corporation...
Page 213 If you do not set this bit to 1, the DAQ-STC may behave erroneously. You can clear this bit by setting AO_Configuration_End to 1. Related bitfields: AO_Configuration_End. © National Instruments Corporation 3-51 DAQ-STC Technical Reference Manual...
Page 214 Setting this bit to 1 asynchronously disarms the BC, UC, and UI counters. This command should be used only to disarm idle counters. To disarm non-idle counters, use AO_Software_Reset. This bit is cleared automatically. DAQ-STC Technical Reference Manual 3-52 © National Instruments Corporation...
Page 215 5 type: Write in: Interrupt_B_Enable_Register address: 75 This bit enables the Error interrupt: 0: Disabled. 1: Enabled. The Error interrupt is generated on the detection of an overrun error condition. © National Instruments Corporation 3-53 DAQ-STC Technical Reference Manual...
Page 216 31: Logic low. This bit is not supported on the first revision of the DAQ-STC, and must be set to 0. See Appendix D, DAQ-STC Revision History, for DAQ-STC revision information. DAQ-STC Technical Reference Manual 3-54 © National Instruments Corporation...
Page 217 1: Enabled. You should set this bit to 0 if there is no data FIFO on your board. In this case, you can use TMRDACWR as a DMA request. Related bitfields: AO_DMA_PIO_Control. © National Instruments Corporation 3-55 DAQ-STC Technical Reference Manual...
Page 218 Write in: Interrupt_B_Enable_Register address: 75 This bit enables the FIFO interrupt: 0: Disabled. 1: Enabled. The FIFO interrupt is generated on the FIFO condition indicated by AO_FIFO_Mode. Related bitfields: AO_FIFO_Mode. DAQ-STC Technical Reference Manual 3-56 © National Instruments Corporation...
Page 219 76 This bit enables the FIFO interrupt in the secondary interrupt bank: 0: Disabled. 1: Enabled. The FIFO interrupt is generated on the FIFO condition indicated by AO_FIFO_Mode. Related bitfields: AO_FIFO_Mode. © National Instruments Corporation 3-57 DAQ-STC Technical Reference Manual...
Page 220 You can use the mute operation to obtain a pause between two real waveforms. You must set the AO_Mute_A bit to the correct value before the BC counter begins using load register A. DAQ-STC Technical Reference Manual 3-58 © National Instruments Corporation...
Page 221 If AO_Multiple_Channels is set to 0, this bitfield determines the number of the single analog output channel that will be written: 0–15: Output channel 0-15 will be written. Related bitfields: AO_Multiple_Channels. © National Instruments Corporation 3-59 DAQ-STC Technical Reference Manual...
Page 222 AO_Reset bit: 1 type: Strobe in: Joint_Reset_Register address: 72 Setting this bit to 1 resets the following registers to their power-on state: AO_Command_1_Register AO_Command_2_Register AO_Interrupt_Control_Register AO_Mode_1_Register AO_Mode_2_Register DAQ-STC Technical Reference Manual 3-60 © National Instruments Corporation...
Page 223 Setting this bit to 1 clears AO_START_St and acknowledges the START interrupt (in either interrupt bank) if the START interrupt is enabled. This bit is cleared automatically. This bitfield is not currently supported. © National Instruments Corporation 3-61 DAQ-STC Technical Reference Manual...
Page 224 This bitfield selects the START trigger: 0: Bitfield AO_START_Pulse or alternate UC_TC. 1–10: PFI<0..9>. 11–17: RTSI_TRIGGER<0..6>. 31: Logic low. This bitfield is currently not supported, and it must be set to 0. DAQ-STC Technical Reference Manual 3-62 © National Instruments Corporation...
Page 225 You should use this bit if you want the same START1 trigger to start several activities. First, disable START1 by setting this bit to 1; do the necessary programming on all DAQ-STCs, then enable START1 by setting this bit to 0. © National Instruments Corporation 3-63 DAQ-STC Technical Reference Manual...
Page 226 Setting this bit to 1 sends a START1 trigger to the BC, UC, and UI counters if the START1 software strobe is selected (AO_START1_Select is set to 0). This bit is cleared automatically. Related bitfields: AO_START1_Select. DAQ-STC Technical Reference Manual 3-64 © National Instruments Corporation...
Page 227 Setting this bit to 1 clears AO_STOP_St and acknowledges the STOP interrupt request (in either interrupt bank) if the STOP interrupt is enabled. This bit is cleared automatically. This bit is currently not supported, and it must be set to 0. Related bitfields: AO_STOP_St. © National Instruments Corporation 3-65 DAQ-STC Technical Reference Manual...
Page 228 UPDATE is being asserted, the UPDATE pulse may be masked off. Although this is not an error condition, and the AO_Overrun_St bit will not be set, that specific UPDATE pulse may be blocked. DAQ-STC Technical Reference Manual 3-66 © National Instruments Corporation...
Page 229 This bit selects the signal appearing on the bidirectional pin PFI6/AO_START1 when the pin is configured for output: 0: Output the internal signal DA_START1. 1: Output the internal signal DA_ST1ED after it has been pulse stretched to be 1–2 AO_OUT_TIMEBASE periods long. © National Instruments Corporation 3-67 DAQ-STC Technical Reference Manual...
Page 230 UC counter loads the value contained in this bitfield on AO_UC_Load and on UC_TC. The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address. Related bitfields: AO_UC_Next_Load_Source_St, AO_UC_Load. DAQ-STC Technical Reference Manual 3-68 © National Instruments Corporation...
Page 231 Setting this bit to 1 causes the UC save register to latch the UC counter value at the next UC_CLK falling edge. Setting this bit to 0 causes the UC save register to trace the UC counter. © National Instruments Corporation 3-69 DAQ-STC Technical Reference Manual...
Page 232 Setting this bit to 1 clears AO_UC_TC_St and acknowledges the UC_TC interrupt request (in either interrupt bank) if the UC_TC interrupt is enabled. This bit is cleared automatically. Related bitfields: AO_UC_TC_St. DAQ-STC Technical Reference Manual 3-70 © National Instruments Corporation...
Page 233 Setting this bit to 1 arms the UI counter. The counter remains armed, and the bit remains set, until it is disarmed either by hardware or by setting AO_Disarm to 1. Related bitfields: AO_UI_Arm, AO_Disarm. © National Instruments Corporation 3-71 DAQ-STC Technical Reference Manual...
Page 234 UI counter loads the value contained in this bitfield on AO_UI_Load and on UI_TC. The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address. Related bitfields: AO_UI_Next_Load_Source_St, AO_UI_Load. DAQ-STC Technical Reference Manual 3-72 © National Instruments Corporation...
Page 235 START1 trigger and the first UPDATE pulse different from the remaining update intervals. 7: Switch load register on BC_TC. Use this setting to synchronously change the update interval at each BC_TC. This is convenient for staged analog output operation. © National Instruments Corporation 3-73 DAQ-STC Technical Reference Manual...
Page 236 This action is internally synchronized to the falling edge of the UI_CLK. This bit is cleared automatically. This bitfield is currently not supported, and it must be set to 0. DAQ-STC Technical Reference Manual 3-74 © National Instruments Corporation...
Page 237 If you do not set this bit to 1, the DAQ-STC may behave erroneously. You can clear this bit by setting AO_UI2_Configuration_End to 1. Related bitfields: AO_UI2_Configuration_End. © National Instruments Corporation 3-75 DAQ-STC Technical Reference Manual...
Page 238 If the UI2 counter is disarmed, this bit selects the initial UI2 load register: 0: Load register A. 1: Load register B. If the UI2 counter is armed, writing to this bit has no effect. Related bitfields: AO_UI2_Arm. DAQ-STC Technical Reference Manual 3-76 © National Instruments Corporation...
Page 239 Read in: AO_UI2_Save_Register address: 23 This bitfield reflects the contents of the UI2 counter. Reading from this bitfield while the UI2 counter is counting may result in an erroneous value. © National Instruments Corporation 3-77 DAQ-STC Technical Reference Manual...
Page 240 Setting this bit to 1 causes the UI2 counter to switch load registers at the next UI2_TC. This bit is cleared automatically. AO_UI2_TC_Error_Confirm bit: 5 type: Strobe in: Interrupt_B_Ack_Register address: 3 Setting this bit to 1 clears AO_UI2_TC_Error_St. This bit is cleared automatically. Related bitfields: AO_UI2_Error_St. DAQ-STC Technical Reference Manual 3-78 © National Instruments Corporation...
Page 241 This bit indicates whether the UI2 counter has reached TC: 0: No. 1: Yes. To clear this bit, set AO_UI2_TC_Interrupt_Ack to 1. Related bitfields: AO_UI2_TC_Interrupt_Ack. Refer to Table 8-2, Interrupt Condition Summary, for more information. © National Instruments Corporation 3-79 DAQ-STC Technical Reference Manual...
Page 242 UPDATE2 pulses are not blocked. UPDATE2 pulses can be blocked by the secondary external gate or by AO_UI2_Software_Gate. The pulsewidth of the output signal is determined by AO_UPDATE2_Pulse_Width. This bit is cleared automatically. Related bitfields: AO_UI2_Software_Gate, AO_UPDATE2_Pulse_Width. DAQ-STC Technical Reference Manual 3-80 © National Instruments Corporation...
Page 243 Related bitfields: AO_UPDATE_St. AO_UPDATE_Interrupt_Enable bit: 2 type: Write in: Interrupt_B_Enable_Register address: 75 This bit enables the UPDATE interrupt: 0: Disabled. 1: Enabled. UPDATE interrupts are generated on the trailing edge of UPDATE. © National Instruments Corporation 3-81 DAQ-STC Technical Reference Manual...
Page 244 UPDATE pulses are not blocked. UPDATE pulses can be blocked by the external gate or by AO_Software_Gate. The pulsewidth of the output signals is determined by AO_UPDATE_Pulse_Width. This bit is cleared automatically. Related bitfields: AO_UPDATE_Output_Select, AO_Software_Gate, AO_UPDATE_Pulse_Width. DAQ-STC Technical Reference Manual 3-82 © National Instruments Corporation...
Page 245 This bit selects the active edge of the UPDATE source (the signal that is selected by AO_UPDATE_Source_Select): 0: Rising edge. 1: Falling edge. You must set this bit to 0 in the internal UPDATE mode. Related bitfields: AO_UPDATE_Source_Select. © National Instruments Corporation 3-83 DAQ-STC Technical Reference Manual...
Page 246: Timing Diagrams
Some of the tables in this section indicate that OSC is the reference pin, with RTSI_OSC included in parentheses. This indicates that you can use RTSI_Clock_Mode to choose between OSC and RTSI_OSC as the reference pin. DAQ-STC Technical Reference Manual 3-84 © National Instruments Corporation...
Page 247: Table 3-2. Update_Src Reference Pin Selection
The UI2 source is selected to be the output of general-purpose counter 0. The reference pin is determined by G0_Source_Select. To determine delays for this case, the source to output delay (Tso) from general-purpose counter 0 must be added. © National Instruments Corporation 3-85 DAQ-STC Technical Reference Manual...
Page 248: Table 3-4. Daq-Stc-Driven Analog Output Timing
The delay will be in clock period increments, and an internally synchronized version of the AOFEF enables or disables the generation of the TMRDACWR. The UPDATE signal simultaneously transfers the written data to the outputs of all of the DACs. DAQ-STC Technical Reference Manual 3-86 © National Instruments Corporation...
Page 249: Figure 3-14. Daq-Stc-Driven Analog Output Timing
OUT_CLK to UPDATE deasserted Tupwr (0.5) (1.5) UPDATE to TMRDACWR asserted Tctwr OUT_CLK to TMRDACWR asserted Tctreq OUT_CLK to TMRDACREQ asserted Treqneg OUT_CLK to TMRDACREQ deasserted (2, 3) (2, 3) TMRDACWR pulsewidth © National Instruments Corporation 3-87 DAQ-STC Technical Reference Manual...
Page 250: Cpu-Driven Analog Output Timing
CPUDACWR. This allows the board to only decode one set of address lines when both TMRDACWR and CPUDACWR are being used. Figure 3-15 shows the basic timing involved in CPU-driven analog output. Both modes of CHRDY_OUT are shown, demonstrating the savings in bus bandwidth. DAQ-STC Technical Reference Manual 3-88 © National Instruments Corporation...
Page 251: Figure 3-15. Cpu-Driven Analog Output Timing
OUT_CLK to CPUDACWR deasserted 2 (3) 5 (9) AO_ADDR<0..3> setup to CPUDACWR 2 (3) 5 (12) AO_ADDR<0..3>hold from CPUDACWR All timing values are in nanoseconds. Figure 3-15. CPU-Driven Analog Output Timing © National Instruments Corporation 3-89 DAQ-STC Technical Reference Manual...
Page 252: Daq-Stc- And Cpu-Driven Analog Output Timing
DAQ-STC write cycle in progress. If the DAQ-STC is writing to the DACs, the CPU bus cycle will be extended to the next write slot. This case is detailed in Figure 3-16. DAQ-STC Technical Reference Manual 3-90 © National Instruments Corporation...
Page 253: Figure 3-16. Analog Output Contention Timing, Case A
DAQ-STC continued with its own write cycle. Each write slot is separated by one clock period, as shown in the timing diagram. The two signals CPUDACWR and TMRDACWR can never occur at the same time and will be separated by at least one clock period. © National Instruments Corporation 3-91 DAQ-STC Technical Reference Manual...
Page 254: Figure 3-17. Analog Output Contention Timing, Case B
The timing parameters are identical to those for the first conflict case. OUT_CLK Tctwrd Tctwr TMRDACWR CPUDACREQ Treqchrdy Tcwrcrdy CHRDY_OUT Tccwrd Tcwr Tccwr CPUDACWR Figure 3-17. Analog Output Contention Timing, Case B DAQ-STC Technical Reference Manual 3-92 © National Instruments Corporation...
Page 255: Secondary Analog Output Timing
The UPDATE2 signal can be programmed to one or three output clock periods, or one source clock period (see AO_UPDATE2_Pulse_Width). The synchronization for UPDATE2(OUT) counts either three or seven output clock edges, regardless of polarity. © National Instruments Corporation 3-93 DAQ-STC Technical Reference Manual...
Page 256: Decoded Signal Timing
TMRDACWR or CPUDACWR cycle. The DACWR0 signal can be configured to ignore the AO_ADDR0 line, for use with a single DAC package. In this option, the DACWR0 signal will be asserted on every TMRDACWR and CPUDACWR cycle. DAQ-STC Technical Reference Manual 3-94 © National Instruments Corporation...
Page 257: Figure 3-19. Decoded Signal Timing
TMRDACWR to da_addr change Tascpu AO_ADDR setup to CPUDACWR Tahcpu AO_ADDR hold from CPUDACWR All timing values are in nanoseconds. Figure 3-19. Decoded Signal Timing The numbers in parentheses are for DACWR<0..1>. © National Instruments Corporation 3-95 DAQ-STC Technical Reference Manual...
Page 258: Local Buffer Mode Timing
FIFO. When the FIFO becomes empty, the DAQ-STC asserts the AOFFRT signal, which sets the FIFO read pointer back to the first location of the FIFO. The waveform can then be output again, as shown in Figure 3-20. DAQ-STC Technical Reference Manual 3-96 © National Instruments Corporation...
Page 259: Figure 3-20. Local Buffer Mode Timing
The AOFEF is recognized by the DAQ-STC at the trailing edge of the TMRDACWR signal. This leads to the assertion of AOFFRT, which is deasserted on the next rising edge of the output clock. © National Instruments Corporation 3-97 DAQ-STC Technical Reference Manual...
Page 260: Unbuffered Data Interface Timing
The primary output signals are UPDATE, TMRDACWR, CHRDY_OUT, CPUDACWR, and AO_ADDR<0..3>. Primary input signals are AOFEF and CPUDACREQ. Figure 3-21 shows the timing for this mode. DAQ-STC Technical Reference Manual 3-98 © National Instruments Corporation...
Page 261: Figure 3-21. Unbuffered Data Interface Timing
43 (47) OUT_CLK to CPUDACWR asserted Tcwr [2,3] [2, 3] CPUDACWR pulsewidth All timing values are in nanoseconds. Figure 3-21. Unbuffered Data Interface Timing The numbers in parentheses are for DACWR<0..1>. © National Instruments Corporation 3-99 DAQ-STC Technical Reference Manual...
Page 262 DMA accesses. The AO_ADDR<0..3> lines still indicate the destination DAC but change on the CPUDACWR signal instead of the TMRDACWR signal as before. The bus address lines A<0..3> will still pass through to the AO_ADDR<0..3> lines during a CPU access. DAQ-STC Technical Reference Manual 3-100 © National Instruments Corporation...
Page 263: Maximum Update Rate Timing
TMRDACWR. The next UPDATE pulse can be asserted at the same output clock edge on which the last TMRDACWR signal is deasserted. Therefore, the shortest cycle time for the case above is four output clock periods for one channel, plus three output clock periods for © National Instruments Corporation 3-101 DAQ-STC Technical Reference Manual...
Page 264: External Trigger Timing
Figures 3-23 through 3-28. The four modes are called asynchronous-level sensitive, asynchronous edge sensitive, synchronous-level sensitive, and synchronous edge sensitive. Ts_strt1 Th_strt1 UPDATE_SRC START1 Figure 3-23. External Trigger, Asynchronous Level Ts_strt1 UPDATE_SRC Tstrt1 START1 Figure 3-24. External Trigger, Asynchronous Edge DAQ-STC Technical Reference Manual 3-102 © National Instruments Corporation...
Page 265: Figure 3-25. External Trigger, Synchronous Level, Internal Update Mode
Figure 3-26. External Trigger, Synchronous Edge, Internal UPDATE Mode Ts_strt1 Th_strt1 UPDATE_SRC START1 Figure 3-27. External Trigger, Synchronous Level, External UPDATE Mode Ts_strt1 UPDATE_SRC Tstrt1 START1 Figure 3-28. External Trigger, Synchronous Edge, External UPDATE Mode © National Instruments Corporation 3-103 DAQ-STC Technical Reference Manual...
Page 266: Trigger Output
UPDATE or external UPDATE, using AI_UPDATE_Source_Select. In the internal UPDATE mode, the inactive edge of the UI source that recognizes the external trigger generates the output. Figure 3-29 shows the propagation delays for START1. DAQ-STC Technical Reference Manual 3-104 © National Instruments Corporation...
Page 267: Figure 3-29. Start1 Delays, Synchronous Mode, Internal Update
Minimum Maximum Tpfi Source to PFI output Trtsi Source to RTSI output Tbrd Source to BRD output All timing values are in nanoseconds. Figure 3-29. START1 Delays, Synchronous Mode, Internal UPDATE © National Instruments Corporation 3-105 DAQ-STC Technical Reference Manual...
Page 268: Figure 3-30. Start1 Delays, Synchronous Mode, External Update
Figure 3-30. START1 Delays, Synchronous Mode, External UPDATE Asynchronous Mode When you select asynchronous mode for START1, the external trigger itself generates the rising edge of the output. Figure 3-31 shows the propagation delays for START1. DAQ-STC Technical Reference Manual 3-106 © National Instruments Corporation...
Page 269: Counter Outputs
Figure 3-32 shows the delays associated with the BC_TC signal. BC Source BC_TC Name Description Minimum Maximum BC Source to BC_TC All timing values are in nanoseconds. Figure 3-32. BC_TC Delay © National Instruments Corporation 3-107 DAQ-STC Technical Reference Manual...
Page 270: Uc_Tc
In addition to the counters, the primary logic blocks are the counter control blocks, the trigger block, the interrupt control block, and the output control block. DAQ-STC Technical Reference Manual 3-108 © National Instruments Corporation...
Page 271: Internal Signals And Operation
End on UC_TC—This signal is the schematic name for the synchronized version of the register map bitfield AO_End_On_UC_TC. AO_END2 End on BC_TC—This signal is the schematic name for the synchronized version of the register map bitfield AO_End_On_BC_TC. © National Instruments Corporation 3-109 DAQ-STC Technical Reference Manual...
Page 272 BC source. The external trigger and gate inputs which are not generated synchronous to the BC source outside of the timer can and should be synchronized to the BC source inside of the timer. DAQ-STC Technical Reference Manual 3-110 © National Instruments Corporation...
Page 273 100 kHz. Related bitfields: Slow_Internal_Time_Divide_By_2, Slow_Internal_Timebase. INT_SCLK_SEL Internal Update Indicator—This signal indicates whether internal or external UPDATE mode is selected. It is 1 for internal UPDATE mode and 0 for external UPDATE mode. © National Instruments Corporation 3-111 DAQ-STC Technical Reference Manual...
Page 274 = 1, the UC save register latches the UC counter output. Related bitfields: AO_UC_Save_Trace. UC_LOAD UC Load—This signal pulses to load the value from the selected UC load register into the UC counter. Related bitfields: AO_UC_Load. DAQ-STC Technical Reference Manual 3-112 © National Instruments Corporation...
Page 275 UI Source—The UI source is the timebase for the UI counter. It is software selectable from AO_IN_TIMEBASE1, IN_TIMEBASE2, PFI<0..9>, and RTSI_TRIGGER<0..6>. Related bitfields: AO_UI_Source_Select. UI_TC Update Interval Counter TC—The UI_TC signal is primarily used as the internal UPDATE. © National Instruments Corporation 3-113 DAQ-STC Technical Reference Manual...
Page 276: Trigger Selection And Conditioning
20-to-1 multiplexer followed by an exclusive OR gate for polarity selection. The routing logic for the trigger signal START1 has additional controls for edge detection and synchronization, as shown in Figure 3-35. When synchronization is selected, START1 is synchronized to both UI_SRC and BC_SRC. DAQ-STC Technical Reference Manual 3-114 © National Instruments Corporation...
Page 277: Figure 3-35. Start1 Routing Logic
Table 3-7 summarizes the selections available for each of the trigger signals through the PFI selector. Table 3-7. PFI Selectors 1–10 11–17 AO_START1_Source PFI<0..9> RTSI<0..6> — AI_ST1 — AO_START_Source SW, UC_TC PFI<0..9> RTSI<0..6> — — — AO_UPDATE_Source UI_TC PFI<0..9> RTSI<0..6> — GOUT1 — © National Instruments Corporation 3-115 DAQ-STC Technical Reference Manual...
Page 278: Using Edge Detection
START1 is the trigger for the waveform generation, initiating the output sequence. It can be generated by software or by an external pulse. START1 can also be internally conditioned to provide enhanced master/slave operation. DAQ-STC Technical Reference Manual 3-116 © National Instruments Corporation...
Page 279: Analog Output Counters
The UI control circuit generates the count enable signals. © National Instruments Corporation 3-117 DAQ-STC Technical Reference Manual...
Page 280: Ui Control
During normal operation, the UC counter synchronously reloads from the selected load register following UC_TC. Two options—AO_UC_Switch_Load_On_End and AO_UC_Switch_Load_On_TC—change the selected load register under various conditions. DAQ-STC Technical Reference Manual 3-118 © National Instruments Corporation...
Page 281: Uc Control
G'H' + H'I'J UC_LOAD = EK + AO_UC_Load UC_CE = BK (EXT_GATE + INT_SCLK_SEL) (CNT(n) + CNT(n+1)) UC_DISARM = (H + I + N) CNT(n) WAIT(n+1) Figure 3-38. UC Control Circuit State Transitions © National Instruments Corporation 3-119 DAQ-STC Technical Reference Manual...
Page 282: Bc Counter
The BC counter has the option AO_Trigger_Once to disarm itself after the first BC_TC. At the end of a nonretriggerable waveform-generation sequence, the BC_TC masks off the last UPDATE pulse to prevent an undesired output. DAQ-STC Technical Reference Manual 3-120 © National Instruments Corporation...
Page 283: Ui2 Counter
3.8.3.8 UI2 Control UI2 runs unless disarmed, stopped, or gated. The following are the UI2 counter logic equations. UI2_LOAD = UI2_TC + AO_UI2_LOAD UI2_CE = AI_UI2_Arm(STOP’) (EXT_GATE2 + (DA_SFGATE2’) AO_UI2_External_Gate_Enable’) © National Instruments Corporation 3-121 DAQ-STC Technical Reference Manual...
Page 284: Table 3-8. Analog Output Interrupts
UPDATE may not have completed for several reasons, such as interference from CPU writes to the DACs, an UPDATE interval that is too short, or a FIFO empty condition that delays TMRDACWR. DAQ-STC Technical Reference Manual 3-122 © National Instruments Corporation...
Page 285: Output Control
Conditions the CPU writes to DAC signal CPUDACWR • Arbitrates the DAQ-STC and CPU write signals to prevent local bus conflict • Generates the bus extend request signal to the CPU CHRDY_OUT © National Instruments Corporation 3-123 DAQ-STC Technical Reference Manual...
Page 286: Table 3-9. Analog Output Nominal Signal Widths
Asserted when data needed, removed at TMRDACWR. AO_ADDR<0..3> Changes on trailing edge of TMRDACWR. Bus address pass through during CPUDACWR. CHRDY_OUT From CPUDACREQ to edge of CPUDACWR. DACWR0 — 2, 3 DACWR1 — 2, 3 AOFFRT — DAQ-STC Technical Reference Manual 3-124 © National Instruments Corporation...
Page 287: Overview
The GPCT module has the following features: • Two independent 24-bit binary up/down counters • Count up/count down control via hardware or software • Programmable counter source and gate selection from 17 signal sources © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 288: Simplified Model
0 and 1. Figure 4-1 shows a simplified model of the counter. G_UP_DOWN G_SOURCE Load Registers G_OUT 24 Bit Up/Down Counter Save Registers G_GATE INTERRUPT Figure 4-1. General-Purpose Counter/Timer Simplified Model DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 289: Counter/Timer Functions
4.4 Counter/Timer Functions The purpose of the GPCT is to provide counter/timer functions that are improved over those available on the Am9513-based DAQ boards through NI-DAQ, the National Instruments software for data acquisition. Examples of existing counter/timer functions supported by the DAQ-STC are event counting, period measurement, pulsewidth measurement, pulse generation, and pulse-train generation.
Page 290: Figure 4-2. Simple Event Counting
Buffered noncumulative event counting is similar to simple event counting except that there are multiple counting intervals. The G_GATE signal indicates the boundary between consecutive counting intervals. The counter counts the number of pulses that occur on the DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 291: Figure 4-4. Buffered Noncumulative Event Counting
Figure 4-5 shows cumulative event counting where the gate action causes the HW save register to save the counter contents twice. Software Arm G_GATE G_SOURCE Counter Value HW Save Register Figure 4-5. Cumulative Event Counting © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 292: Time Measurement
G_GATE input. The counter counts the number of rising edges that occur on G_SOURCE between two active edges of G_GATE. At the completion of the period interval for G_GATE, the HW save register latches the counter value for software read. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 293: Figure 4-7. Single-Period Measurement
G_GATE input, counting the number of rising edges that occur on G_SOURCE between each pair of active edges of G_GATE. At the completion of each period interval for G_GATE, the HW save register © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 294: Figure 4-9. Buffered Period Measurement
G_SOURCE rising edges. Notice that you do not know whether the first value is saved on a rising edge or a falling edge. G_GATE G_SOURCE Counter Value HW Save Register Figure 4-10. Buffered Semiperiod Measurement DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 295: Pulse Generation
G_SOURCE input. Software implements pulse generation by loading the delay value into the counter, loading the pulsewidth value into the load register, and programming the counter © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 296: Figure 4-12. Single Pulse Generation
Figure 4-13 shows the generation of a single pulse with a pulse delay of four and a pulsewidth of three. G_GATE G_SOURCE Counter Value Counter TC G_OUT Figure 4-13. Single Triggered-Pulse Generation DAQ-STC Technical Reference Manual 4-10 © National Instruments Corporation...
Page 297: Figure 4-14. Retriggerable Single Pulse Generation
The first pulse has a pulse delay of five and a pulsewidth of three. The second pulse has a pulse delay of six and a pulsewidth of four. © National Instruments Corporation 4-11...
Page 298: Pulse-Train Generation
TC. Figure 4-16 shows the generation of three pulses with a delay from trigger of three, a pulse interval of four and a pulsewidth of three. DAQ-STC Technical Reference Manual 4-12 © National Instruments Corporation...
Page 299: Figure 4-16. Continuous Pulse-Train Generation
G_GATE G_SOURCE Counter Value 0 3 2 1 0 2 1 Counter TC G_OUT Software Counter Figure 4-17. Buffered Static Pulse-Train Generation © National Instruments Corporation 4-13 DAQ-STC Technical Reference Manual...
Page 300: Figure 4-18. Buffered Pulse-Train Generation
Figure 4-19 shows an example of FSK. When G_GATE is low, the counter generates a low-frequency signal with a long pulsewidth. When G_GATE is high, the counter generates a high-frequency signal with a short pulsewidth. DAQ-STC Technical Reference Manual 4-14 © National Instruments Corporation...
Page 301: Figure 4-19. Frequency Shift Keying
ETS. In this figure, the delay from the trigger to the pulse increases after each subsequent G_GATE active edge. START G_GATE Counter TC G_OUT D2= D1+∆D D3= D1+2∆D Figure 4-20. Pulse Generation for ETS © National Instruments Corporation 4-15 DAQ-STC Technical Reference Manual...
Page 302: Table 3-1. Pin Interface
These pins are pulled down on the first revision of the DAQ-STC, and pulled up on later revisions. See Appendix D, DAQ-STC Revision History, for DAQ-STC revision information. Related bitfields: Gi_Up_Down. DAQ-STC Technical Reference Manual 4-16 © National Instruments Corporation...
Page 303: Programming Information
X and bank Y. The two load registers in each bank are called load register A and load register B. The two save registers are used for saving the contents of the counter; they are called the HW save register and the save register. © National Instruments Corporation 4-17 DAQ-STC Technical Reference Manual...
Page 304: Notation
4.6.1.4 Arming Use the following function to arm the counter after the programming sequence is complete. This function will cause the counter to begin the programmed operation. Function Gi_Arm_All Gi_Arm = 1; DAQ-STC Technical Reference Manual 4-18 © National Instruments Corporation...
Page 305: Simple Event Counting
18 (AI START2) or 19 (UI2_TC) or 20 (other G_TC) or 21 (AI START1) or 31 (logic low); Gi_OR_Gate = 0; Gi_Output_Polarity = 0 (active high) or 1 (active low); Gi_Gate_Select_Load_Source = 0; © National Instruments Corporation 4-19 DAQ-STC Technical Reference Manual...
Page 306: Buffered Event Counting
In cumulative mode, the stale data error is ignored because the gate actions do not affect the counter contents, so that the HW save register always contains the correct value. DAQ-STC Technical Reference Manual 4-20 © National Instruments Corporation...
Page 307 Gi_Up_Down = 0 (down counting) or 1 (up counting) or 2 (controlled by G_UP_DOWNi) or 3 (controlled by the internal gate value); Gi_Bank_Switch_Enable = 0; Gi_Bank_Switch_Mode = 0; Gi_TC_Interrupt_Enable = 0; Gi_Gate_Interrupt_Enable = 1; © National Instruments Corporation 4-21 DAQ-STC Technical Reference Manual...
Page 308 Inform user that a gate acknowledge latency error has occurred; Gi_Gate_Error_Confirm = 1; If (Gi_TC_St is 1) then /*rollover error — counter value is not correct*/ Inform user that a rollover error has occurred; Gi_TC_Interrupt_Ack = 1; DAQ-STC Technical Reference Manual 4-22 © National Instruments Corporation...
Page 309: Relative Position Sensing
Gi_Reload_Source_Switching = 1; Gi_Loading_On_Gate = 0; Gi_Loading_On_TC = 0; Gi_Gating_Mode = 2; Gi_Gate_On_Both_Edges = 0; Gi_Trigger_Mode_For_Edge_Gate = 3; Gi_Stop_Mode = 0; Gi_Counting_Once = 0; If (hardware controlled relative position sensing) then © National Instruments Corporation 4-23 DAQ-STC Technical Reference Manual...
Page 310: Single-Period And Pulsewidth Measurement
Program the Gi_Gate to select the signal on which you want to measure the period or pulsewidth. Function Single_Period_And_Pulse_Width_Measurement Gi_Load_Source_Select = 0; Gi_Load_A = initial counter value; ∑ Gi_Load = 1; ∑ DAQ-STC Technical Reference Manual 4-24 © National Instruments Corporation...
Page 311 Gi_Loading_On_TC = 0; Gi_Gating_Mode = 1; Gi_Gate_On_Both_Edges = 0; Gi_Trigger_Mode_For_Edge_Gate = 2; Gi_Stop_Mode = 0; Gi_Counting_Once = 2; Gi_Up_Down = 1; Gi_Bank_Switch_Enable = 0; Gi_Bank_Switch_Mode = 0; Gi_TC_Interrupt_Enable = 0; Gi_Gate_Interrupt_Enable = 0; © National Instruments Corporation 4-25 DAQ-STC Technical Reference Manual...
Page 312: Buffered Period, Semiperiod, And Pulsewidth Measurement
Gi_Gate_Polarity = 0 (disable inversion) or 1 (enable inversion); Gi_Output_Mode = 1 (one clock cycle output) or 2 (toggle on TC) or 3 (toggle on TC or gate); Gi_Reload_Source_Switching = 0; Gi_Loading_On_Gate = 1; Gi_Loading_On_TC = 0; DAQ-STC Technical Reference Manual 4-26 © National Instruments Corporation...
Page 313 If (Gi_Stale_Data_St is 1) then /*stale data — no source transitions between two relevant gate edges*/ = 0; save_1 If ( is 0) AND (buffer is not full) then g_buffer_done © National Instruments Corporation 4-27 DAQ-STC Technical Reference Manual...
Page 314: Pulse And Continuous Pulse-Train Generation
Program the Gi_Source to select the signal that you want to use as a reference clock. For single-triggered pulse generation and retriggerable single pulse generation, program Gi_Gate to select the signal that you want to use as a hardware trigger. DAQ-STC Technical Reference Manual 4-28 © National Instruments Corporation...
Page 315 If (single pulse generation) then Gi_Gating_Mode = 0; Else /*Single-triggered pulse generation or retriggerable single pulse generation*/ Gi_Gating_Mode = 2; Gi_Gate_On_Both_Edges = 0; Gi_Trigger_Mode_For_Edge_Gate = 2; Gi_Stop_Mode = 2; If (retriggerable single pulse generation) then © National Instruments Corporation 4-29 DAQ-STC Technical Reference Manual...
Page 316 Gi_Output_Mode = 1 (one clock cycle output) or 2 (toggle on TC) or 3 (toggle on TC or gate); Gi_Reload_Source_Switching = 1; Gi_Loading_On_Gate = 0; Gi_Loading_On_TC = 1; Gi_Gating_Mode = 2; Gi_Gate_On_Both_Edges = 0; Gi_Trigger_Mode_For_Edge_Gate = 2; DAQ-STC Technical Reference Manual 4-30 © National Instruments Corporation...
Page 317: Frequency Shift Keying
500 kHz square wave when the controlling signal has a high logic value. No errors are detected in this application. © National Instruments Corporation 4-31 DAQ-STC Technical Reference Manual...
Page 318 Gi_Loading_On_TC = 1; Gi_Gating_Mode = 1; Gi_Gate_On_Both_Edges = 0; Gi_Trigger_Mode_For_Edge_Gate = 3; Gi_Stop_Mode = 0; Gi_Counting_Once = 0; Gi_Up_Down = 0; Gi_Bank_Switch_Enable = 1; Gi_Bank_Switch_Mode = 0; Gi_TC_Interrupt_Enable = 0; Gi_Gate_Interrupt_Enable = 0; DAQ-STC Technical Reference Manual 4-32 © National Instruments Corporation...
Page 319: Pulse-Train Generation For Ets
3 (toggle on TC or gate); Gi_Reload_Source_Switching = 1; Gi_Loading_On_Gate = 0; Gi_Loading_On_TC = 1; Gi_Gating_Mode = 2; Gi_Gate_On_Both_Edges = 0; Gi_Trigger_Mode_For_Edge_Gate = 2; Gi_Stop_Mode = 2; Gi_Counting_Once = 0; Gi_Up_Down = 0; Gi_Bank_Switch_Enable = 0; © National Instruments Corporation 4-33 DAQ-STC Technical Reference Manual...
Page 320: Reading The Counter Contents
The Gi_Gate_Interrupt_St bit will be set whenever a value is saved in the Gi_HW_Save_Registers. This status bit indicates when it is time to read the hardware save registers. DAQ-STC Technical Reference Manual 4-34 © National Instruments Corporation...
Page 321: Enabling The General Purpose Counter/Timer Output Pin
Before setting this bit to 1, make sure that the analog trigger is not being used by any other part of the DAQ-STC. You should not set this bit to 1 in any other case. This bit is cleared automatically. © National Instruments Corporation 4-35 DAQ-STC Technical Reference Manual...
Page 322 27 i = 1 bit: 1 type: Read in: Joint_Status_1_Register address: 27 This bit indicates the load register bank used by general-purpose counter i: 0: Bank X. 1: Bank Y. DAQ-STC Technical Reference Manual 4-36 © National Instruments Corporation...
Page 323 0: No hardware disarm. 1: Disarm at the TC that stops counting. 2: Disarm at the G_GATE that stops counting. 3: Disarm at the TC or G_GATE that stops counting, whichever comes first. © National Instruments Corporation 4-37 DAQ-STC Technical Reference Manual...
Page 324 4 This bit indicates the detection of a general-purpose counter i gate acknowledge latency error: 0: No. 1: Yes. To clear this bit, set Gi_Gate_Error_Confirm to 1. Related bitfields: Gi_Gate_Error_Confirm. DAQ-STC Technical Reference Manual 4-38 © National Instruments Corporation...
Page 325 This bit enables you to use both gate edges to generate the gate interrupt and/or to control counter operation: 0: Disabled. 1: Enabled. This bit also affects where interrupts are generated. © National Instruments Corporation 4-39 DAQ-STC Technical Reference Manual...
Page 326 19: The internal analog output signal UI2_TC. See AO_UPDATE2_Output_Toggle. 20: The G_TC signal from the other general-purpose counter. 21: The internal analog input signal START1. 31: Logic low. Related bitfields: AO_UPDATE2_Output_Toggle. DAQ-STC Technical Reference Manual 4-40 © National Instruments Corporation...
Page 327 • Rising edge if Gi_Gating_Polarity is set to 1. When Gi_Gating_Mode is 0 (gating disabled), gate level is available only for control of counting direction (up/down), and for no other purpose. Related bitfields: Gi_Gating_Polarity. © National Instruments Corporation 4-41 DAQ-STC Technical Reference Manual...
Page 328 Strobe in: G1_Command_Register address: 7 Setting this bit to 1 loads the contents of the selected load register into general-purpose counter i. This bit is cleared automatically. Related bitfields: Gi_Load_Source_Select. DAQ-STC Technical Reference Manual 4-42 © National Instruments Corporation...
Page 329 0: Load register A. 1: Load register B. The source for subsequent loads depends on Gi_Reload_Source_Switching. If general-purpose counter i is armed, writing to this bit has no effect. Related bitfields: Gi_Reload_Source_Switching, Gi_Arm, Gi_Arm_Copy. © National Instruments Corporation 4-43 DAQ-STC Technical Reference Manual...
Page 330 4 i = 1 bit: 11 type: Read in: G_Status_Register address: 4 This bit indicates that a counter reload did not occur for general-purpose counter i between two relevant G_GATE edges. DAQ-STC Technical Reference Manual 4-44 © National Instruments Corporation...
Page 331 29 i = 1 bit: 1 type: Read in: Joint_Status_2_Register address: 29 This bit indicates the current G_OUT state (after the polarity selection): 0: Low. 1: High. Related bitfields: Gi_Output_Polarity. © National Instruments Corporation 4-45 DAQ-STC Technical Reference Manual...
Page 332 Joint_Reset_Register address: 72 Setting this bit to 1 resets the counter, clears Gi_Arm and Gi_Arm_Copy, clears the G0_Mode_Register, and clears the appropriate bits of the G_Input_Select_Register. This bit is cleared automatically. DAQ-STC Technical Reference Manual 4-46 © National Instruments Corporation...
Page 333 The eight MSBs are located at the lower address and the 16 LSBs are located at the higher address. Related bitfields: Gi_Save_Trace, Gi_Save_Trace_Copy. © National Instruments Corporation 4-47 DAQ-STC Technical Reference Manual...
Page 334 Gi_Gating_Mode and Gi_Trigger_Mode_For_Edge_Gate (in case of edge gating). Selections 1 and 2 are valid only if Gi_Trigger_Mode_For_Edge_Gate is set to 2 (no hardware limit on this). Related bitfields: Gi_Disarm, Gi_Gating_Mode, Gi_Trigger_Mode_For_Edge_Gate. DAQ-STC Technical Reference Manual 4-48 © National Instruments Corporation...
Page 335 Setting this bit to 1 clears Gi_TC_St and acknowledges the TC interrupt request (in either interrupt bank) if the TC interrupt is enabled. This bit is cleared automatically. Related bitfields: Gi_TC_St. © National Instruments Corporation 4-49 DAQ-STC Technical Reference Manual...
Page 336 Selections 0, 1, and 2 are valid only if Gi_Gating_Mode is set to 2 or 3. Selection 3 is valid only if Gi_Gating_Mode is not set to 0. Related bitfields: Gi_Gating_Mode, Gi_Stop_Mode. DAQ-STC Technical Reference Manual 4-50 © National Instruments Corporation...
Page 337 This bit configures the G_OUT0/RTSI_IO bidirectional pin: 0: Input. Use this pin to route an external signal to the RTSI_TRIGGER bus. See RTSI_Trig_i_Output_Select 1: Output. Use GPFO_0_Output_Select to select the output signal. Related bitfields: RTSI_Trig_i_Output_Select, GPFO_0_Output_Select. © National Instruments Corporation 4-51 DAQ-STC Technical Reference Manual...
Page 338 Related bitfields: GPFO_1_OUTPUT_Enable. G_Source_Divide_By_2 bit: 10 type: Write in: Clock_and_FOUT_Register address: 56 This bit determines the frequency of the internal timebase G_IN_TIMEBASE: 0: Same as IN_TIMEBASE. 1: IN_TIMEBASE divided by 2. DAQ-STC Technical Reference Manual 4-52 © National Instruments Corporation...
Page 339: Timing Diagrams
The delay gate is provided so that the signals synchronized to the early version of CTRSRC have sufficient time to settle to a known state before being used by the counter. © National Instruments Corporation 4-53 DAQ-STC Technical Reference Manual...
Page 340: Table 4-2. Ctrgate Reference Pin Selection
Reference Pin G_UP_DOWNi Same reference pin as selected by CTRGATE Reference Pin Selection CTROUT refers to following pins: • G_OUT0/RTSI_OUT • G_OUT1/DIV_TC_OUT INTERRUPT refers to the following pins: • IRQ_OUT<0..7> • SEC_IRQ_OUT_BANK<0..1> DAQ-STC Technical Reference Manual 4-54 © National Instruments Corporation...
Page 341: Ctrsrc Minimum Period And Minimum Pulsewidth
0 for its source, then the total delay (OSC to the CTROUT of general-purpose counter 1) will be 18 + 27 = 45 (MIN) and 55 + 80 = 135 (MAX). © National Instruments Corporation 4-55 DAQ-STC Technical Reference Manual...
Page 342: G_Gate Minimum Pulsewidth
Figure 4-23 and the accompanying table indicate the minimum pulsewidth for the general-purpose counter gate signal, CTRGATE. Tgatepw CTRGATE Tgatepw Name Description Minimum Maximum Tgatepw — CTRGATE minimum pulsewidth All timing values are in nanoseconds. Figure 4-23. G_GATE Minimum Pulsewidth DAQ-STC Technical Reference Manual 4-56 © National Instruments Corporation...
Page 343: Ctrgate To Ctrout Delay
INTERRUPT when the counter gate generates an interrupt. CTRGATE Tgatei INTERRUPT Name Description Minimum Maximum Tgatei CTRGATE to INTERRUPT All timing values are in nanoseconds. Figure 4-25. CTRGATE to INTERRUPT Timing © National Instruments Corporation 4-57 DAQ-STC Technical Reference Manual...
Page 344: Ctrgate Setup
Tgtclk Tgtclk CTRSRC Counter Counter TC CTRGATE Name Description Minimum Maximum Tgtclk — CTRGATE to CTRSRC setup All timing values are in nanoseconds. Figure 4-26. CTRGATE Setup Timing, Internal Timing Mode DAQ-STC Technical Reference Manual 4-58 © National Instruments Corporation...
Page 345: Ctr_U/D Setup
CTR_U/D is synchronized to the active edge of CTRSRC before it enters a delay gate. Figures 4-28 and 4-29, and the accompanying table indicate the setup time requirements for CTR_U/D relative to the relevant edge of CTRSRC. © National Instruments Corporation 4-59 DAQ-STC Technical Reference Manual...
Page 346: Figure 4-28. Ctr_U/D Setup Timing, Internal Timing Mode
Tgtclk Tgtclk CTRSRC Counter Counter TC CTR_U/D Name Description Minimum Maximum Tgtclk — CTR_U/D to CTRSRC setup All timing values are in nanoseconds. Figure 4-29. CTR_U/D Setup Timing, External Timing Mode DAQ-STC Technical Reference Manual 4-60 © National Instruments Corporation...
Page 347: Detailed Description
(for example, in buffered pulse-train generation). Load register A in bank X has a special autoincrement feature that is used in pulse-train generation for ETS. Each time the counter reloads from the load register, the autoincrement circuit adds a constant fixed value © National Instruments Corporation 4-61 DAQ-STC Technical Reference Manual...
Page 348: Internal Signals And Operation
Gi_Source selector through polarity selection. Related bitfields: Gi_Source_Select. G_TC Counter TC—G_TC is the actual general-purpose counter TC signal. G_OUT Counter Output—G_OUT is the G_TC signal after output and polarity selection. Related bitfields: Gi_Output_Mode, Gi_Output_Polarity. DAQ-STC Technical Reference Manual 4-62 © National Instruments Corporation...
Page 349: G_Source Selection And Conditioning
G_IN_TIMEBASE1 has possible values of 20 MHz and 10 MHz, and IN_TIMEBASE2 is 100 kHz. Table 4-6 shows the conditioning available for G_SOURCE. Table 4-6. G_SOURCE Conditioning Gi_Source_Polarity Polarity Rising edge active Falling edge active © National Instruments Corporation 4-63 DAQ-STC Technical Reference Manual...
Page 350: G_Gate Selection And Conditioning
G_UP_DOWN pins to the I/O connector because of pin count limitations. Note On the E Series boards, the UP_DOWN control inputs G_UP_DOWN0 and G_UP_DOWN1 pins are tied together with the DIO <6..7>. DAQ-STC Technical Reference Manual 4-64 © National Instruments Corporation...
Page 351: G_Out Conditioning And Routing
The Gi_Output_Polarity bits further condition the output signal G_OUT, as shown in Table 4-11. Table 4-11. G_OUT Polarity Gi_Output_Polarity Description Active high. Output is normally low. Active low. Output is normally high. © National Instruments Corporation 4-65 DAQ-STC Technical Reference Manual...
Page 352: Table 4-12. G_Out0/Rtsi_Io Selection
DAQ-STC modules. The general-purpose counter 0 output G_OUT connects to the AITM of the DAQ-STC. The general-purpose counter 1 output G_OUT connects to the AOTM of the DAQ-STC. Refer to the appropriate module description for more details. DAQ-STC Technical Reference Manual 4-66 © National Instruments Corporation...
Page 353: G_Control Conditioning
Generate interrupt on G_GATE Gi_Gate_Interrupt_Enable Change output polarity on G_GATE Gi_Output_Mode Select load Register on G_CONTROL Gi_Gate_Select_Load_Source Disarm Counter on G_CONTROL Gi_Counting_Once Switch load bank selection on G_CONTROL Gi_Bank_Switch_Enable; Gi_Bank_Switch_Mode; Gi_Bank_Switch_Start © National Instruments Corporation 4-67 DAQ-STC Technical Reference Manual...
Page 354: Start/Stop On G_Control
GATE/ Trigger Loading CONTROL Mode for On Gate Conditioning Edge Gate Selected Reload Mode G_CONTROL does not cause counter reload. Level gating Counter reload occurs on G_CONTROL transition to ACTIVE state. DAQ-STC Technical Reference Manual 4-68 © National Instruments Corporation...
Page 355: Up/Down On G_Control
ACTIVE and on every counter TC. 4.8.7.7 Select Load Register on G_CONTROL When Gi_Gate_Select_Load_Source is set to 1, an ACTIVE G_CONTROL selects load register A, and an INACTIVE G_CONTROL selects load register B. © National Instruments Corporation 4-69 DAQ-STC Technical Reference Manual...
Page 356: Table 3-7. Pfi Selectors
The G_OUT signal from general-purpose counter 0. GOUT1 The G_OUT signal from general-purpose counter 1. G_TB1 The internal signal G_IN_TIMEBASE1. The internal signal IN_TIMEBASE2 UI2_TC The internal analog output signal UI2_TC. DAQ-STC Technical Reference Manual 4-70 © National Instruments Corporation...
Page 357: Error Detection
If the stale data error is set at any point in a repetitive measurement, then the permanent stale data error (Gi_Permanent_Stale_Data_St) is set to indicate that a measurement error occurred at some point in the sequence. © National Instruments Corporation 4-71 DAQ-STC Technical Reference Manual...
Page 358: Detailed Operation By Application
Figure 4-31. G_SOURCE Generation 4.8.11.1 Simple Event Counting In simple event counting, the counter increments on every G_SOURCE rising edge following the ARM. To read the counter contents, use the save register. DAQ-STC Technical Reference Manual 4-72 © National Instruments Corporation...
Page 359: Figure 4-32. Simple Event Counting
The dotted line indicates where the ARM occurs and the arrow indicates where the gate interrupt is generated. G_SOURCE G_GATE G_CONTROL Counter Value HW Save HW Save Register Figure 4-33. Simple Gated-Event Counting © National Instruments Corporation 4-73 DAQ-STC Technical Reference Manual...
Page 360: Figure 4-34. Buffered Noncumulative-Event Counting
G_GATE. The counter increments on every G_SOURCE rising edge following the ARM. The HW save register switches to transparent mode on the rising edge of G_GATE and returns to latched mode on the next G_SOURCE falling edge. DAQ-STC Technical Reference Manual 4-74 © National Instruments Corporation...
Page 361: Figure 4-35. Buffered Cumulative-Event Counting
After the ARM, the counter increments when up/down is high and decrements when up/down is low. Figure 4-36 shows an example of relative-position sensing. The dotted line indicates where the ARM occurs. G_SOURCE G_UP_DOWN Up/Down Counter Value Figure 4-36. Relative-Position Sensing © National Instruments Corporation 4-75 DAQ-STC Technical Reference Manual...
Page 362: Figure 4-37. Single-Period Measurement
G_SOURCE rising edges. The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated. G_SOURCE G_GATE G_CONTROL Counter Value HW Save HW Save Register Figure 4-37. Single-Period Measurement DAQ-STC Technical Reference Manual 4-76 © National Instruments Corporation...
Page 363: Figure 4-38. Single Pulsewidth Measurement
G_GATE is low. If ARM occurs while G_GATE is high, the G_GATE pulse will only be measured from ARM until the end of the pulse. G_SOURCE G_GATE G_CONTROL Counter Value HW Save HW Save Register Figure 4-38. Single Pulsewidth Measurement © National Instruments Corporation 4-77 DAQ-STC Technical Reference Manual...
Page 364: Figure 4-39. Buffered Period Measurement
G_SOURCE rising edges. The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated. G_SOURCE G_GATE G_CONTROL Counter Load Counter Value HW Save HW Save Register Figure 4-39. Buffered Period Measurement DAQ-STC Technical Reference Manual 4-78 © National Instruments Corporation...
Page 365: Figure 4-40. Buffered Semiperiod Measurement
The dotted line indicates where the ARM occurs and the arrows indicate where the gate interrupt is generated. G_SOURCE G_GATE G_CONTROL Counter Load Counter Value HW Save HW Save Register Figure 4-40. Buffered Semiperiod Measurement © National Instruments Corporation 4-79 DAQ-STC Technical Reference Manual...
Page 366: Figure 4-41. Buffered Pulsewidth Measurement
G_GATE is low. If ARM occurs while G_GATE is high, the initial pulse will only be measured from ARM until the end of the pulse. G_SOURCE G_GATE G_CONTROL Counter Load Counter Value HW Save HW Save Register Figure 4-41. Buffered Pulsewidth Measurement DAQ-STC Technical Reference Manual 4-80 © National Instruments Corporation...
Page 367: Figure 4-42. Single Pulse Generation
Figure 4-42 shows an example of single pulse generation with a pulse delay of five and a pulsewidth of three. The dotted line indicates where the ARM occurs. G_SOURCE Load Select Counter Load Counter Value Counter TC G_OUT Figure 4-42. Single Pulse Generation © National Instruments Corporation 4-81 DAQ-STC Technical Reference Manual...
Page 368: Figure 4-43. Single-Triggered Pulse Generation
Figure 4-43 shows an example of single-triggered pulse generation with a pulse delay of five and a pulsewidth of three. The dotted line indicates where the ARM occurs. G_SOURCE G_GATE G_CONTROL Load Select Counter Load Counter Value Counter TC G_OUT Figure 4-43. Single-Triggered Pulse Generation DAQ-STC Technical Reference Manual 4-82 © National Instruments Corporation...
Page 369: Figure 4-44. Retriggerable Single Pulse Generation
The dotted line indicates where the ARM occurs. G_SOURCE G_GATE G_CONTROL Load Select Counter Load Counter Value Counter TC G_OUT Figure 4-44. Retriggerable Single Pulse Generation © National Instruments Corporation 4-83 DAQ-STC Technical Reference Manual...
Page 370: Figure 4-45. Continuous Pulse-Train Generation
The dotted line indicates where the ARM occurs. G_SOURCE G_GATE G_CONTROL Load Select Counter Load Counter Value Counter TC G_OUT Figure 4-45. Continuous Pulse-Train Generation DAQ-STC Technical Reference Manual 4-84 © National Instruments Corporation...
Page 371: Figure 4-46. Buffered Pulse-Train Generation
ARM occurs and the arrows indicate where the TC interrupt is generated. G_SOURCE G_GATE G_CONTROL Bank Select Load Select Counter Load Counter Value Counter TC G_OUT Figure 4-46. Buffered Pulse-Train Generation © National Instruments Corporation 4-85 DAQ-STC Technical Reference Manual...
Page 372: Figure 4-47. Frequency Shift Keying
1 0 1 0 2 1 0 1 0 4 3 2 1 0 3 2 1 0 4 3 2 1 0 3 2 1 0 Counter Value Counter TC G_OUT Figure 4-47. Frequency Shift Keying DAQ-STC Technical Reference Manual 4-86 © National Instruments Corporation...
Page 373: Figure 4-48. Pulse Generation For Ets
Load Select Counter Load 1 0 1 0 2 1 0 1 0 3 2 1 0 1 0 5 Counter Value Counter TC G_OUT Figure 4-48. Pulse Generation for ETS © National Instruments Corporation 4-87 DAQ-STC Technical Reference Manual...
Page 374: Overview
– Outputs: START1 and UPDATE • General-purpose counter/timer interface – Inputs: G0 source, G0 gate, G1 source, and G1 gate – Outputs: G0 source, G0 gate, G1 source, and G1 gate © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 375: Pin Interface
• If AI_Trigger_Length is 1, this pin reflects the internal AI signal AD_VSTART2 after it has been pulse stretched to be 1–2 AI_OUT_TIMEBASE periods long. Source/Destination: This pin is appropriate for use as a bidirectional PRETRIG signal. Related bitfields: BD_1_Pin_Dir, AI_Trigger_Length. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 376 AO signal DACUPDN (the update signal from the analog output section). Source/Destination: This pin is appropriate for use as a bidirectional EXTDACUPDATE* signal. Related bitfields: BD_5_Pin_Dir. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 377 SCAN_IN_PROG. If SCAN_IN_PROG is configured for high impedance, PFI7/AI_START will output ground. Source/Destination: This pin is appropriate to input an EXTGATE from the I/O connector. Related bitfields: BD_7_Pin_Dir, AI_START_Output_Select, AI_Trigger_Length, AI_SCAN_IN_PROG_Output_Select. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 378: Programming Information
Use this function to configure the direction of one of the 10 PFI pins. Function MSC_IO_Pin_Configure switch (pin number) case 0: BD_0_Pin_Dir = 0 (input) or 1 (output); break; case 1: BD_1_Pin_Dir = 0 (input) or 1 (output); break; © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 379: Bitfield Descriptions
The PFI-related bitfields are described below. Not all bitfields referred to in section 5.4, Programming Information, are listed here. To locate a particular bitfield description within this manual, refer to Appendix B, Register Information. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 380: Detailed Description
RTSI<0..6> AI_ST1 AO_START_Source PFI<0..9> RTSI<0..6> UC_TC AO_UPDATE_Source UI_TC PFI<0..9> RTSI<0..6> GOUT1 AO_UI_Source AO_TB1 PFI<0..9> RTSI<0..6> AO_UI2_Source AO_TB1 PFI<0..9> RTSI<0..6> G0_TC G1_TC AO_UI_External_Gate PFI<0..9> RTSI<0..6> AO_UI2_External_Gate PFI<0..9> RTSI<0..6> G0_Source G_TB1 PFI<0..9> RTSI<0..6> G1_TC © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 381: Table 5-3. Pfi<0..9> Output Selections
PFI pin when the pin is configured for output. Refer to section 5.3, Interface, for more detailed information on the internal signal tap point. Table 5-3. PFI<0..9> Output Selections SIGNAL AI START1 AI START2 CONVERT G1 Source G1 Gate AO UPDATE AO START1 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 382 Chapter 5 Programmable Function Inputs Table 5-3. PFI<0..9> Output Selections SIGNAL AI START or AI SCAN_IN_PROG G0 Source G0 Gate © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 383: Overview
Four additional bidirectional pins for communication between the RTSI trigger bus and board signals 6.3 Pin Interface The RTSI signals are listed in the following table. Pin Type Notation: B9TU Bidirectional, 9 mA sink, 5 mA source tri-state, pull up (50 kΩ) © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 384: Programming Information
DAQ-STC, see section 2.6, Programming Information. 6.4.1 Programming the RTSI Interface This section contains detailed programming information for users who need to do bit-level programming of the RTSI interface for specialized applications. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 385: Bitfield Descriptions
RTSI trigger-related bitfields are described below. Not all bitfields referred to in section 6.4, Programming Information, are listed here. To locate a particular bitfield description within this manual, refer to Appendix B, Register Information. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 386 OSC pin. The signal from the OSC pin will pass through two buffers provided for use with the RTSI_OSC pin before becoming the internal timebase; this design provides the best master/slave clock synchronization. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 387 14 type: Write in: RTSI_Trig_Direction_Register address: 58 i = 6 bit: 15 type: Write in: RTSI_Trig_Direction_Register address: 58 This bit selects the of the bidirectional pin RTSI_TRIGGERi: 0: Input. 1: Output. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 388: Detailed Description
RTSI_TRIGGER pins. RTSI_BRD<0..1> can also be driven by AI STOP. RTSI_BRD<2..3> can also be driven by the AI START and SCAN_IN_PROG signals. Tables 6-3 and 6-4 summarize the available output selections on RTSI_BRD<0..3>. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 389: Table 6-3. Rtsi_Brd<0..1> Output Selections
• If AI_Trigger_Length is 1, this pin reflects the internal signal AD_START after it has been pulse stretched to be 1–2 AI_OUT_TIMEBASE periods long. If AI_START_Output_Select is 1, this pin will output the same signal as SCAN_IN_PROG. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 390: Overview
The DIO module contains the hardware necessary to perform serial and parallel digital I/O, as well as support for a status and control register interface. Figure 7-1 shows a simplified model of the DIO module. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 391: Overview Of Dio Functions
The software inputs data asynchronously from the DIO port by reading from the parallel input register. Software must perform handshaking to ensure that the data is read and written safely. The EXTSTROBE/SDCLK output is available for simple handshaking operations. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 392: Parallel Input
EXTSTROBE/SDCLK falling edge. The DAQ-STC transmits the data bytes 0x55 and 0xAA hex. EXTSTROBE/SDCLK 0x55 0xAA DIO<7..0> SW UPDATE SW UPDATE Figure 7-3. Parallel Output © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 393: Serial Output
EXTSTROBE/SDCLK to complete the current 8-bit data transfer. Each 8-bit transfer is initiated under software control. Figure 7-5 shows a serial input operation where the DAQ-STC outputs the data byte 0x4B hex. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 394: Serial I/O
Figure 7-6 shows a serial I/O operation where the DAQ-STC simultaneously reads the data byte 0x4B hex and outputs the data byte 0x97 hex. SW START EXTSTROBE/SDCLK DIO4/SDIN Read Locations DIO0/SDOUT Figure 7-6. Serial I/O © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 395: Pin Interface
SCXI at one of two selectable clock rates. See also EXTSTROBE/SDCLK. Related bitfields: DIO_Pins_Dir, DIO_Parallel_Date_In_St, DIO_Parallel_Data_Out, DIO_Serial_Data_In_St. DIO<5..7> B18TU Digital I/O Lines<5..7>—Individually programmable DIO lines. Related bitfields: DIO_Pins_Dir, DIO_Parallel_Data_In_St, DIO_Parallel_Data_Out. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 396: Programming Information
/* DAQ_STC base address */ /* on the AT-MIO-E Series */ #define DAQ_STC_Window_Address_Reg DAQ_STC_Base_Addr + 0x00 #define DAQ_STC_Window_Data_Write_Reg DAQ_STC_Base_Addr + 0x01*2 #define DAQ_STC_Window_Data_Read_Reg DAQ_STC_Base_Addr + 0x01*2 #define DAQ_STC_DIO_Output_Register 0x0A #define DAQ_STC_DIO_Control_Register 0x0B #define DAQ_STC_DIO_All_Outputs 0xFF © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 397: Programming The Digital Interface
DIO4 can be used for 8-bit serial digital input, and line DIO0 can be used for 8-bit serial digital output. To program the eight DIO pins for input or output, use the following function: DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 398: Parallel Digital I/O
Values corresponding to the pins configured for output will reflect the values being output on those pins. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 399: Hardware-Controlled Serial Digital I/O
DIO_Serial_Out_Divide_By_2 = 0 (do not divide by 2) or 1 (divide by 2); DIO_HW_Serial_Timebase = 0 (1.2 µs clock) or 1 (10 µs clock); DIO_HW_Serial_Enable = 1; Use the following function to initiate a serial transfer. Function DIO_HW_Serial_Initialize If (DIO_Serial_IO_In_Progress_St is 1) then DAQ-STC Technical Reference Manual 7-10 © National Instruments Corporation...
Page 400 If you do not need serial digital input, you can omit the Serial DIO Input section from your program. If, in addition, you know that no software running on your computer will need the © National Instruments Corporation 7-11 DAQ-STC Technical Reference Manual...
Page 401: Software-Controlled Serial Digital I/O
Function MSC_Generic_Control Control = output value; Note These are generic control lines. Refer to the user manual for your DAQ board or device for information on how these lines are used. DAQ-STC Technical Reference Manual 7-12 © National Instruments Corporation...
Page 402: Bitfield Descriptions
1: Enabled. EXTSTROBE/SDCLK pin is controlled by serial hardware. DIO_HW_Serial_Start bit: 8 type: Strobe in: DIO_Control_Register address: 11 Setting this bit to 1 starts the hardware-controlled serial digital I/O if enabled. This bit is cleared automatically. Related bitfields: DIO_HW_Serial_Enable. © National Instruments Corporation 7-13 DAQ-STC Technical Reference Manual...
Page 403 I/O is in progress. Related bitfields: DIO_Serial_IO_In_Progress. DIO_Serial_Data_Out bits: <8..15> type: Write in: DIO_Output_Register address: 10 This bitfield is used for data to be serially output on DIO0. DAQ-STC Technical Reference Manual 7-14 © National Instruments Corporation...
Page 404: Serial Input Timing
7.7.1 Serial Input Timing In the serial-input mode, the rising edge of the EXTSTROBE/SDCLK signal clocks data on the DIO4/SDIN line. Figure 7-7 shows the setup and hold times for serial input. © National Instruments Corporation 7-15 DAQ-STC Technical Reference Manual...
Page 405: Serial Output Timing
DIO0/SDOUT line. Figure 7-8 shows the propagation delay for serial output. EXTSTROBE/SDCLK DIO0/SDOUT Name Description Minimum Maximum EXTSTROBE/SDCLK to DIO0/SDOUT All timing values are in nanoseconds. Figure 7-8. Serial Output Timing DAQ-STC Technical Reference Manual 7-16 © National Instruments Corporation...
Page 406: Detailed Description
In parallel I/O mode, the bits in the read register that correspond to pins configured for output should be ignored. Similarly, the bits in the write register that correspond to pins configured for input are ignored by the hardware. © National Instruments Corporation 7-17 DAQ-STC Technical Reference Manual...
Page 407: Overview
Two external interrupt inputs for board-level interrupts generated outside the DAQ-STC. • 18 internally generated interrupt sources relating to the AITM, AOTM, and GPCT modules. • Two additional independently controlled outputs for each group allow an additional mechanism for interrupt service. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 408: Pin Interface
NuBus. Destination: CPU bus. Related bitfields: Interrupt_A_Output_Select, Interrupt_A_Output_Enable, Interrupt_B_Output_Select, Interrupt_B_Output_Enable, Interrupt_Output_Polarity, Interrupt_Output_On_3_Pins. SEC_IRQ_OUT_BANK0 OD18U Secondary Interrupt Output for Interrupt Group A. SEC_IRQ_OUT_BANK1 OD18U Secondary Interrupt Output for Interrupt Group B. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 409: Programming Information
Function MSC_IRQ_Configure switch (interrupt group) case A: Interrupt_A_Output_Select = 0 through 7 (IRQ_OUT<0..7>); Interrupt_A_Enable = 0 (disabled) or 1 (enabled); break; case B: Interrupt_B_Output_Select = 0 through 7 (IRQ_OUT<0..7>); © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 410 Use the following function to enable the use of an external interrupt condition on pins IRQ_IN<0..1>. Function MSC_Pass_Through_Interrupt switch (pass through interrupt) case 0: Pass_Thru_0_Interrupt_Enable = 0 (disabled) or 1 (enabled); break; case 1: Pass_Thru_1_Interrupt_Enable = 0 (disabled) or 1 (enabled); break; DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 411: Interrupt Handling
The following sections present the functions that should be executed when an appropriate interrupt is asserted. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 412 If (Soft_Copy(AI_FIFO_Interrupt_Enable) is 1) then If (AI_FIFO_Request_St is 1) then /*AI FIFO caused the interrupt*/ Service AI FIFO interrupt; /*You cannot explicitly acknowledge a FIFO interrupt. You must perform an action external*/ DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 413 /*The interrupt was caused by AI SC_TC signal*/ Service the AI SC_TC interrupt; /*To clear this interrupt, set AI_SC_TC_Interrupt_Ack = 1*/ /*To enable this interrupt, set AI_SC_TC_Interrupt_Enable = 1*/ Else if (Soft_Copy(AI_START1_Interrupt_Enable) is 1) then © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 414 If (AI_START_St is 1) then /*The interrupt was caused by AI START signal*/ Service the AI START interrupt; /*To clear this interrupt, set AI_START_Interrupt_Ack = 1*/ /*To enable this interrupt, set AI_START_Interrupt_Enable = 1*/ DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 415 /*external to the DAQ-STC in order to clear this interrupt condition. Normally, board hardware*/ /*should be designed so that you can cause this action*/ /*To enable this interrupt, set AI_Pass_Thru_1_Interrupt_Enable = 1*/ © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 416 Else if (Soft_Copy(AO_UC_TC_Interrupt_Enable) is 1) then If (AO_UC_TC_St is 1) then /*The interrupt was caused by AO UC_TC signal*/ Service the AO BU_TC interrupt; /*To clear this interrupt, set AO_UC_TC_Interrupt_Ack = 1*/ DAQ-STC Technical Reference Manual 8-10 © National Instruments Corporation...
Page 417 /*To clear this interrupt, set AO_STOP_Interrupt_Ack = 1*/ /*To enable this interrupt, set AO_STOP_Interrupt_Enable = 1*/ /*This interrupt is not supported*/ Else if (Soft_Copy(AO_START_Interrupt_Enable) is 1) then If (AO_START_St is 1) then © National Instruments Corporation 8-11 DAQ-STC Technical Reference Manual...
Page 418: Bitfield Descriptions
This bit enables interrupt request generation on the IRQ_OUT pin selected by Interrupt_A_Output_Select: 0: Disabled. 1: Enabled. Related bitfields: Interrupt_A_Output_Select. Interrupt_A_Output_Select bits: <8..10> type: Write in: Interrupt_Control_Register address: 59 This bit selects the output pin IRQ_OUT<0..7> for interrupt group A: 0–7: IRQ_OUT<0..7>. DAQ-STC Technical Reference Manual 8-12 © National Instruments Corporation...
Page 419 Additional output on IRQ_OUT0 and IRQ_OUT1 pins is: 0: Disabled. 1: Enabled. Interrupt_Output_Polarity bit: 0 type: Write in: Interrupt_Control_Register address: 59 This bit selects the polarity of the IRQ_OUT<0..7> output signals: 0: Active high. 1: Active low. © National Instruments Corporation 8-13 DAQ-STC Technical Reference Manual...
Page 420 = 1 bit: 11 type: Write in: Second_Irq_B_Enable_Register address: 76 This bit enables the pass through i interrupt in the secondary interrupt bank: 0: Disabled. 1: Enabled. Related bitfields: Pass_Thru_i_Interrupt_Polarity. DAQ-STC Technical Reference Manual 8-14 © National Instruments Corporation...
Page 421: Interrupt Conditions
Interrupts are generated on the leading edge of the G_TC signal from general-purpose counter 0. G0 Gate Interrupt Interrupts are generated on the G_CONTROL signal from general-purpose counter 0. Refer to section 4.8.7, Gate Actions, for a complete description. © National Instruments Corporation 8-15 DAQ-STC Technical Reference Manual...
Page 422 4.8.7, Gate Actions for a complete description. Pass-Through Interrupt 0 Interrupts are generated when the IRQ_IN0 pin is asserted. Pass-Through Interrupt 1 Interrupts are generated when the IRQ_IN1 pin is asserted. DAQ-STC Technical Reference Manual 8-16 © National Instruments Corporation...
Page 423: Overview
The I/O signals relevant to the Bus Interface are listed in the following table. An asterisk following a pin name indicates that the default polarity for that pin is active low. Pin Type Notation: TTL input, pull down (50 kΩ) Input, pull up (50 kΩ) © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 424: Table 9-1. Pin Interface
Bidirectional Tri-State Data Bus—This signal transfers data between the DAQ-STC and the CPU. Source/Destination: CPU bus. INTEL/MOTO* Intel/Motorola Bus Interface Selection—Intel mode uses RD and WR signals. Motorola mode uses R/W and DS signals. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 425: Programming Information
FIFOs. Related bitfields: Write_Strobe_0, Write_Strobe_1, Write_Strobe_2, Write_Strobe_3. 9.4 Programming Information This section presents programming information that is specific to the bus interface. For general information about programming the DAQ-STC, see section 2.6, Programming Information. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 426: Programming The Write Strobes
Analog_Trigger_Etc_Register address: 61 Setting this bit to 1 enables the hardware test mode, which tri-states all the output signals. Setting this bit to 1 is equivalent to bringing the TEXT_IN pin low. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 427: Timing Diagrams
Figure 9-1, and the write timing is shown in Figure 9-2. The read timing for the Motorola-style bus interface is shown in Figure 9-3, and the write timing is shown in Figure 9-4. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 428: Figure 9-1. Intel Bus Interface Read Timing
Table 9-2. Intel Bus Interface Timing Name Description Minimum Maximum Tcs-rd 45 (50) — CS-RD pulsewidth Tcs-wr — CS-WR pulsewidth Tads — Address setup time Tadh — Address hold time 44 (49) Data valid Data invalid DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 429: Figure 9-3. Motorola Bus Interface Read Timing
CS-RD and CS-WR. The timing parameters are all relative to the combined signal. Tads Tadh Trws Tcs-ds Trwh CS-DS RD/WR A<1..7> D<0..15> Figure 9-3. Motorola Bus Interface Read Timing © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 430: Figure 9-4. Motorola Bus Interface Write Timing
The internal signals will be asserted only when both the chip-select and data-strobe signals are asserted, shown above as CS-DS. The timing parameters are all relative to the combined signal. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 431: Overview
Output pin for board-level use of the main clock selection • Frequency output – Divides the master timebase by any integer between 1 and 16 • Analog trigger • Test mode © National Instruments Corporation 10-1 DAQ-STC Technical Reference Manual...
Page 432: Clock Distribution
Table 10-1 indicates the internal timebases derived from IN_TIMEBASE. Table 10-1. Timebases Derived from IN_TIMEBASE Timebase Related Bitfields Divide Options IN_TIMEBASE2 Slow_Internal_Time_Divide_By_2, 100, 200 Slow_Internal_Timebase AI_IN_TIMEBASE1 AI_Source_Divide_By_2 1, 2 DAQ-STC Technical Reference Manual 10-2 © National Instruments Corporation...
Page 433: Frequency Output
Many boards will also have the ability to source an analog trigger to external devices based on DAQ-STC timing. The output ANALOG_TRIG_DRIVE selects the I/O direction of the analog trigger signal. You have direct control over ANALOG_TRIG_DRIVE through a bit in the register map. © National Instruments Corporation 10-3 DAQ-STC Technical Reference Manual...
Page 434: Figure 10-2. Low-Window Mode
Figure 10-2. Low-Window Mode In the high-window mode, the trigger indicates when the signal value is greater than the HI value. The LOW value is unused. HI Value Trigger Figure 10-3. High-Window Mode DAQ-STC Technical Reference Manual 10-4 © National Instruments Corporation...
Page 435: Figure 10-4. Middle-Window Mode
To use analog triggering in any of the hysteresis modes, reset the hysteresis register during initialization using one of the analog trigger reset bits. HI Value LOW Value Trigger Figure 10-5. High-Hysteresis Mode © National Instruments Corporation 10-5 DAQ-STC Technical Reference Manual...
Page 436: Test Mode
The output of the tree appears on the pin TEST_OUT. The internal gate tree consists of multiple two-input AND gates connected to an OR structure. Figure 10-7 shows the structure of the internal gate tree. DAQ-STC Technical Reference Manual 10-6 © National Instruments Corporation...
Page 437: Figure 10-7. Test Mode Internal Gate Tree
Toggle the first member of the pair low, then high. Observe the change on TEST_OUT. Toggle the second member of the pair low, then high. Observe the change on TEST_OUT. Bring both members of the pair low. TEST_OUT will be high. © National Instruments Corporation 10-7 DAQ-STC Technical Reference Manual...
Page 438: Table 10-2. Test Mode Input Pin Pairs
AIFEF AIFHF MUXFEF AI_STOP_IN ANALOG_TRIG_IN_LO ANALOG_IN_TRIG_HI AOFFF AOFHF AOFEF CPUDACREQ CHRDY_IN DIO0/SDOUT DIO1 DIO2 DIO3 PFI0/AI_START1 PFI1/AI_START2 DIO4/SDIN DIO5 PFI2/CONV PFI3/G_SRC1 DIO6 DIO7 PFI4/G_GATE1 PFI5/UPDATE STATUS0 STATUS1 PFI6/AO_START PFI7/AI_START STATUS2 STATUS3 DAQ-STC Technical Reference Manual 10-8 © National Instruments Corporation...
Page 439: Pin Interface
Analog Input Trigger Low Voltage Reference—This pin indicates that the analog trigger waveform has dropped below the LOW voltage reference. Source: This input is typically fed from an analog comparator on the board. © National Instruments Corporation 10-9 DAQ-STC Technical Reference Manual...
Page 440: Programming Information
IN_TIMEBASE can be selected from two sources—OSC or RTSI_OSC. If the OSC pin is the IN_TIMEBASE source, the RTSI_OSC pin can be used as the IN-TIMEBASE signal output. The IN_TIMEBASE signal, unmodified or divided down by 2, can be fed to the board by DAQ-STC Technical Reference Manual 10-10 © National Instruments Corporation...
Page 441 DAQ-STC, the external circuitry, or both. You must enable the slow internal timebase (IN_TIMEBASE2) if you want to use it. © National Instruments Corporation 10-11 DAQ-STC Technical Reference Manual...
Page 442: Programming Fout
Appendix B, Register Information. Analog_Trigger_Drive bit: 4 type: Write in: Analog_Trigger_Etc_Register address: 61 This bit controls the ANALOG_TRIG_DRIVE output signal: 0: Logic low. 1: Logic high. DAQ-STC Technical Reference Manual 10-12 © National Instruments Corporation...
Page 443 This bit selects the divide ratio for the FOUT output signal: 0: Divide by 16. FOUT = FOUT_TIMEBASE divided by 16. 1-15: Divide by 1-15. FOUT = FOUT_TIMEBASE divided by 1-15. Related bitfields: FOUT_Timebase_Select, FOUT_Enable. © National Instruments Corporation 10-13 DAQ-STC Technical Reference Manual...
Page 444 12 type: Write in: Clock_and_FOUT_Register address: 56 This bit determines whether to divide the IN_TIMEBASE2 clock (obtained by dividing the IN_TIMEBASE clock by 100) by 2: 0: No. 1: Yes. DAQ-STC Technical Reference Manual 10-14 © National Instruments Corporation...
Page 445 Write in: Clock_and_FOUT_Register address: 56 This bit enables the slow internal clock (IN_TIMEBASE2) and the clocks used for serial digital output for communication with SCXI (SERIAL_TIMEBASE): 0: Disabled. 1: Enabled. © National Instruments Corporation 10-15 DAQ-STC Technical Reference Manual...
Page 446 Max source frequency ......20 Mhz Min source pulse duration...... 6 ns Min gate pulse duration......6 ns Digital I/O Number of channels ....... 8 I/O Compatibility ......... TTL in, CMOS out © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 447 High-level input voltage ......2.2 V min, V V max Input rise or fall time ......0 ns min, 200 ns max Input rise or fall time, Schmitt (Buffer I )........0 ns min, 10 ms max DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 448 = 0.4 V) Pin Type Value O4TU 4.5 mA min B9TU, O9TU, O9 9.0 mA min B18TU, OD18U 24.0 mA min = 5 V ±10%, T Note = –40 to +85 C. © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 449 Low-level output voltage (V = 0 mA) ...........0.1 V max High-level output voltage (V = 0 mA) ...........V - 0.1 V min = 5 V ±10%, T Note = –40 to +85 C. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 450: Table B-1. Daq-Stc Registers
Write 0x3C AI_Personal_Register Write 0x4D AI_SC_Load_A_Registers Write 18–19 0x12–0x13 AI_SC_Load_B_Registers Write 20–21 0x14–0x15 AI_SC_Save_Registers Read 66–67 0x42–43 AI_SI_Load_A_Registers Write 14–15 0x0E–0x0F AI_SI_Load_B_Registers Write 16–17 0x10–0x11 AI_SI_Save_Registers Read 64–65 0x40–0x41 AI_SI2_Load_A_Register Write 0x17 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 451 AO_START_Select_Register Write 0x42 AO_Status_1_Register Read 0x03 AO_Status_2_Register Read 0x06 AO_Trigger_Select_Register Write 0x43 AO_UC_Load_A_Registers Write 48–49 0x30–0x31 AO_UC_Load_B_Registers Write 50–51 0x32–0x33 AO_UC_Save_Registers Read 20–21 0x14–0x15 AO_UI_Load_A_Registers Write 40–41 0x28–0x29 AO_UI_Load_B_Registers Write 42–43 0x2A–0x2B DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 452 0x0C–0x0D G1_Autoincrement_Register Write 0x45 G1_Command_Register Write 0x07 G1_HW_Save_Registers Read 10–11 0x0A–0x0B G1_Input_Select_Register Write 0x25 G1_Load_A_Registers Write 32–33 0x20–0x21 G1_Load_B_Registers Write 34–35 0x22–0x23 G1_Mode_Register Write 0x1B G1_Save_Registers Read 14–15 0x0E–0x0F Generic_Control_Register Write 0x47 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 453 Write 0x50 RTSI_Trig_Direction_Register Write 0x3A Second_Irq_A_Enable_Register Write 0x4A Second_Irq_B_Enable_Register Write 0x4C Window_Address_Register Write 0x00 Window_Data_Read_Register Read 0x01 Window_Data_Write_Register Write 0x01 Write_Strobe_0_Register Write 0x52 Write_Strobe_1_Register Write 0x53 Write_Strobe_2_Register Write 0x54 Write_Strobe_3_Register Write 0x55 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 454: Table B-2. Registers In Order Of Address*
Interrupt_A_Ack_Register Interrupt_B_Ack_Register AI_Command_2_Register AO_Command_2_Register G0_Command_Register G1_Command_Register AI_Command_1_Register AO_Command_1_Register DIO_Output_Register DIO_Control_Register AI_Mode_1_Register AI_Mode_2_Register 14–15 AI_SI_Load_A_Registers 16–17 AI_SI_Load_B_Registers 18–19 AI_SC_Load_A_Registers 20–21 AI_SC_Load_B_Registers AI_SI2_Load_A_Register AI_SI2_Load_B_Register G0_Mode_Register G1_Mode_Register 28–29 G0_Load_A_Registers 30–31 G0_Load_B_Registers 32–33 G1_Load_A_Registers 34–35 G1_Load_B_Registers © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 455 G0_Input_Select_Register G1_Input_Select_Register AO_Mode_1_Register AO_Mode_2_Register 40–41 AO_UI_Load_A_Registers 42–43 AO_UI_Load_B_Registers 44–45 AO_BC_Load_A_Registers 46–47 AO_BC_Load_B_Registers 48–49 AO_UC_Load_A_Registers 50–51 AO_UC_Load_B_Registers AO_UI2_Load_A_Register AO_UI2_Load_B_Register Clock_and_FOUT_Register IO_Bidirection_Pin_Register RTSI_Trig_Direction_Register Interrupt_Control_Register AI_Output_Control_Register Analog_Trigger_Etc_Register AI_START_STOP_Select_Register AI_Trigger_Select_Register AI_DIV_Load_A_Register AO_START_Select_Register AO_Trigger_Select_Register G0_Autoincrement_Register G1_Autoincrement_Register AO_Mode_3_Register © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 456 Table B-2. Registers in Order of Address* (Continued) Address Register Name Generic_Control_Register Joint_Reset_Register Interrupt_A_Enable_Register Second_Irq_A_Enable_Register Interrupt_B_Enable_Register Second_Irq_B_Enable_Register AI_Personal_Register AO_Personal_Register RTSI_Trig_A_Output_Register RTSI_Trig_B_Output_Register RTSI_Board_Register Write_Strobe_0_Register Write_Strobe_1_Register Write_Strobe_2_Register Write_Strobe_3_Register AO_Output_Control_Register AI_Mode_3_Register Window_Data_Read_Register AI_Status_1_Register AO_Status_1_Register G_Status_Register AI_Status_2_Register AO_Status_2_Register DIO_Parallel_Input_Register 8–9 G0_HW_Save_Registers 10–11 G1_HW_Save_Registers © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 457 12–13 G0_Save_Registers 14–15 G1_Save_Registers 16–17 AO_UI_Save_Registers 18–19 AO_BC_Save_Registers 20–21 AO_UC_Save_Registers AO_UI2_Save_Register AI_SI2_Save_Register AI_DIV_Save_Register Joint_Status_1_Register DIO_Serial_Input_Register Joint_Status_2_Register 64–65 AI_SI_Save_Registers 66–67 AI_SC_Save_Registers * Write registers are presented in their entirety, followed by read registers. DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 458: Table B-3. Bitfield Description Guide
Chapter 4 Generic_Status Chapter 7 Interrupt Chapter 8 Misc_Counter Chapter 10 Pass_Thru Chapter 8 RTSI Chapter 6 Reserved Chapter 10 Slow Chapter 10 Software Chapter 9 Window Chapter 9 Write_Strobe Chapter 9 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 459 AI_End_On_SC_TC AI_Analog_Trigger_Reset AI_End_On_End_Of_Scan AI_Disarm Reserved AI_SI2_Arm Reserved AI_SI2_Load AI_START1_Disable AI_SI_Arm AI_SC_Save_Trace AI_SI_Load AI_SI_Switch_Load_On_SC_TC AI_DIV_Arm AI_SI_Switch_Load_On_STOP AI_DIV_Load AI_SI_Switch_Load_On_TC AI_SC_Arm Reserved AI_SC_Load Reserved AI_SCAN_IN_PROG_Pulse AI_SC_Switch_Load_On_TC AI_EXTMUX_CLK_Pulse AI_STOP_Pulse AI_LOCALMUX_CLK_Pulse AI_START_Pulse AI_SC_TC_Pulse AI_START2_Pulse AI_CONVERT_Pulse AI_START1_Pulse DAQ-STC Technical Reference Manual B-10 © National Instruments Corporation...
Page 460 AI_SC_Gate_Enable AI_CONVERT_Source_Select AI_Start_Stop_Gate_Enable AI_CONVERT_Source_Select AI_Pre_Trigger AI_CONVERT_Source_Select AI_External_MUX_Present AI_CONVERT_Source_Select Reserved AI_SI_Source_Select Reserved AI_SI_Source_Select AI_SI2_Initial_Load_Source AI_SI_Source_Select AI_SI2_Reload_Mode AI_SI_Source_Select AI_SI_Initial_Load_Source AI_SI_Source_Select AI_SI_Reload_Mode AI_CONVERT_Source_Polarity AI_SI_Reload_Mode AI_SI_Source_Polarity AI_SI_Reload_Mode AI_Start_Stop AI_SI_Write_Switch Reserved_One AI_SC_Initial_Load_Source AI_Continuous AI_SC_Reload_Mode AI_Trigger_Once AI_SC_Write_Switch © National Instruments Corporation B-11 DAQ-STC Technical Reference Manual...
Page 461 Reserved AI_EOC_Polarity Reserved AI_SOC_Polarity Reserved AI_SHIFTIN_Polarity Reserved AI_CONVERT_Pulse_Timebase Reserved AI_CONVERT_Pulse_Width Reserved AI_CONVERT_Original_Pulse Reserved AI_FIFO_Flags_Polarity Reserved AI_Overrun_Mode AI_SC_Load_A AI_EXTMUX_CLK_Pulse_Width AI_SC_Load_A AI_LOCALMUX_CLK_Pulse_Width AI_SC_Load_A AI_AIFREQ_Polarity AI_SC_Load_A Reserved AI_SC_Load_A Reserved AI_SC_Load_A Reserved AI_SC_Load_A Reserved AI_SC_Load_A DAQ-STC Technical Reference Manual B-12 © National Instruments Corporation...
Page 462 Reserved AI_SC_Load_B Reserved AI_SC_Load_B Reserved AI_SC_Load_B Reserved AI_SC_Load_B Reserved AI_SC_Load_B Reserved AI_SC_Load_B Reserved AI_SC_Load_B Reserved AI_SC_Load_B AI_SC_Save_Value AI_SC_Load_B AI_SC_Save_Value AI_SC_Load_B AI_SC_Save_Value AI_SC_Load_B AI_SC_Save_Value AI_SC_Load_B AI_SC_Save_Value AI_SC_Load_B AI_SC_Save_Value AI_SC_Load_B AI_SC_Save_Value AI_SC_Load_B AI_SC_Save_Value © National Instruments Corporation B-13 DAQ-STC Technical Reference Manual...
Page 463 Reserved AI_SI_Load_A Reserved AI_SI_Load_A Reserved AI_SI_Load_A Reserved AI_SI_Load_A Reserved AI_SI_Load_A Reserved AI_SI_Load_A Reserved AI_SI_Load_A Reserved AI_SI_Load_A AI_SI_Load_B AI_SI_Load_A AI_SI_Load_B AI_SI_Load_A AI_SI_Load_B AI_SI_Load_A AI_SI_Load_B AI_SI_Load_A AI_SI_Load_B AI_SI_Load_A AI_SI_Load_B AI_SI_Load_A AI_SI_Load_B AI_SI_Load_A AI_SI_Load_B DAQ-STC Technical Reference Manual B-14 © National Instruments Corporation...
Page 464 AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A AI_SI_Save_Value AI_SI2_Load_A © National Instruments Corporation B-15 DAQ-STC Technical Reference Manual...
Page 465 Interrupt_A_St AI_STOP_Polarity AI_FIFO_Full_St AI_STOP_Sync AI_FIFO_Half_Full_St AI_STOP_Edge AI_FIFO_Empty_St AI_STOP_Select AI_Overrun_St AI_STOP_Select AI_Overflow_St AI_STOP_Select AI_SC_TC_Error_St AI_STOP_Select AI_START2_St AI_STOP_Select AI_START1_St AI_START_Sync AI_SC_TC_St AI_START_Edge AI_START_St AI_START_Select AI_STOP_St AI_START_Select G0_TC_St AI_START_Select G0_Gate_Interrupt_St AI_START_Select AI_FIFO_Request_St AI_START_Select Pass_Thru_0_Interrupt_St DAQ-STC Technical Reference Manual B-16 © National Instruments Corporation...
Page 466 Reserved GPFO_0_Output_Enable Reserved GPFO_0_Output_Select Reserved GPFO_0_Output_Select Reserved GPFO_0_Output_Select Reserved Reserved Reserved Reserved Reserved Reserved Reserved GPFO_1_Output_Select AO_BC_Load_A Misc_Counter_TCs_Output_Enable AO_BC_Load_A Software_Test AO_BC_Load_A Analog_Trigger_Drive AO_BC_Load_A Analog_Trigger_Enable AO_BC_Load_A Analog_Trigger_Mode AO_BC_Load_A Analog_Trigger_Mode AO_BC_Load_A Analog_Trigger_Mode AO_BC_Load_A © National Instruments Corporation B-17 DAQ-STC Technical Reference Manual...
Page 467 Reserved AO_BC_Load_B Reserved AO_BC_Load_B Reserved AO_BC_Load_B Reserved AO_BC_Load_B Reserved AO_BC_Load_B Reserved AO_BC_Load_B Reserved AO_BC_Load_B Reserved AO_BC_Load_B AO_BC_Save_Value AO_BC_Load_B AO_BC_Save_Value AO_BC_Load_B AO_BC_Save_Value AO_BC_Load_B AO_BC_Save_Value AO_BC_Load_B AO_BC_Save_Value AO_BC_Load_B AO_BC_Save_Value AO_BC_Load_B AO_BC_Save_Value AO_BC_Load_B AO_BC_Save_Value DAQ-STC Technical Reference Manual B-18 © National Instruments Corporation...
Page 468 AO_UPDATE_Source_Select AO_End_On_UC_TC AO_UPDATE_Source_Select AO_Start_Stop_Gate_Enable AO_UPDATE_Source_Select AO_UC_Save_Trace AO_UPDATE_Source_Select AO_BC_Gate_Enable AO_UPDATE_Source_Select AO_BC_Save_Trace AO_UI_Source_Select AO_UI_Switch_Load_On_BC_TC AO_UI_Source_Select AO_UI_Switch_Load_On_Stop AO_UI_Source_Select AO_UI_Switch_Load_On_TC AO_UI_Source_Select AO_UC_Switch_Load_On_BC_TC AO_UI_Source_Select AO_UC_Switch_Load_On_TC AO_Multiple_Channels AO_BC_Switch_Load_On_TC AO_UPDATE_Source_Polarity AO_Mute_B AO_UI_Source_Polarity AO_Mute_A AO_UC_Switch_Load_Every_TC AO_UPDATE2_Pulse AO_Continuous AO_START1_Pulse AO_Trigger_Once © National Instruments Corporation B-19 DAQ-STC Technical Reference Manual...
Page 469 Reserved AO_External_Gate_Select AO_Number_Of_DAC_Packages AO_External_Gate_Select AO_Fast_CPU AO_External_Gate_Select AO_TMRDACWR_Pulse_Width AO_External_Gate_Select AO_FIFO_Flags_Polarity AO_External_Gate_Select AO_FIFO_Enable AO_Number_Of_Channels AO_AOFREQ_Polarity AO_Number_Of_Channels AO_DMA_PIO_Control AO_Number_Of_Channels AO_UPDATE_Original_Pulse AO_Number_Of_Channels AO_UPDATE_Pulse_Timebase AO_UPDATE2_Output_Select AO_UPDATE_Pulse_Width AO_UPDATE2_Output_Select AO_BC_Source_Select AO_External_Gate_Polarity AO_Interval_Buffer_Mode AO_UPDATE2_Output_Toggle AO_UPDATE2_Original_Pulse AO_UPDATE_Output_Select AO_UPDATE2_Pulse_Timebase AO_UPDATE_Output_Select AO_UPDATE2_Pulse_Width DAQ-STC Technical Reference Manual B-20 © National Instruments Corporation...
Page 470 AO_UI2_External_Gate_Enable AO_UC_Armed_St AO_Delayed_START1 AO_UI2_Count_Enable_St AO_START1_Polarity AO_UI2_Next_Load_Source_St AO_UI2_Source_Polarity AO_UI2_Armed_St AO_UI2_Source_Select AO_UI2_TC_Error_St AO_UI2_Source_Select AO_UI_Q_St AO_UI2_Source_Select AO_UI_Count_Enable_St AO_UI2_Source_Select AO_UC_Save_St AO_UI2_Source_Select AO_UI_Next_Load_Source_St AO_START1_Sync AO_UI_Armed_St AO_START1_Edge AO_BC_TC_Trigger_Error_St AO_START1_Select AO_BC_Q_St AO_START1_Select AO_BC_Save_St AO_START1_Select AO_BC_Next_Load_Source_St AO_START1_Select AO_BC_Armed_St AO_START1_Select © National Instruments Corporation B-21 DAQ-STC Technical Reference Manual...
Page 471 AO_UC_Load_B Reserved AO_UC_Load_B Reserved AO_UC_Load_B Reserved AO_UC_Load_B Reserved AO_UC_Load_B Reserved AO_UC_Load_B Reserved AO_UC_Load_B Reserved AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B AO_UC_Load_B DAQ-STC Technical Reference Manual B-22 © National Instruments Corporation...
Page 472 AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B AO_UI2_Load_A AO_UI2_Load_B © National Instruments Corporation B-23 DAQ-STC Technical Reference Manual...
Page 473 Reserved AO_UI_Load_A Reserved AO_UI_Load_A Reserved AO_UI_Load_A Reserved AO_UI_Load_A Reserved AO_UI_Load_A Reserved AO_UI_Load_A Reserved AO_UI_Load_A Reserved AO_UI_Load_A AO_UI_Load_B AO_UI_Load_A AO_UI_Load_B AO_UI_Load_A AO_UI_Load_B AO_UI_Load_A AO_UI_Load_B AO_UI_Load_A AO_UI_Load_B AO_UI_Load_A AO_UI_Load_B AO_UI_Load_A AO_UI_Load_B AO_UI_Load_A AO_UI_Load_B DAQ-STC Technical Reference Manual B-24 © National Instruments Corporation...
Page 474 FOUT_Enable AO_UI_Save_Value FOUT_Timebase_Select AO_UI_Save_Value DIO_Serial_Out_Divide_By_2 AO_UI_Save_Value Slow_Internal_Time_Divide_By_2 AO_UI_Save_Value Slow_Internal_Timebase AO_UI_Save_Value G_Source_Divide_By_2 AO_UI_Save_Value Clock_To_Board_Divide_By_2 AO_UI_Save_Value Clock_To_Board AO_UI_Save_Value AI_Output_Divide_By_2 AO_UI_Save_Value AI_Source_Divide_By_2 AO_UI_Save_Value AO_Output_Divide_By_2 AO_UI_Save_Value AO_Source_Divide_By_2 AO_UI_Save_Value FOUT_Divider AO_UI_Save_Value FOUT_Divider AO_UI_Save_Value FOUT_Divider AO_UI_Save_Value FOUT_Divider © National Instruments Corporation B-25 DAQ-STC Technical Reference Manual...
Page 475 Reserved_2_St Reserved_1_St Reserved_2_St Reserved_1_St Reserved_2_St Reserved_1_St Reserved_2_St Reserved_1_St Reserved_2_St Reserved_1_St Reserved_2_St Reserved_1_St Reserved_2_St Reserved_1_St Reserved_2_St DIO_Parallel_Data_In_St DIO_Serial_Data_In_St DIO_Parallel_Data_In_St DIO_Serial_Data_In_St DIO_Parallel_Data_In_St DIO_Serial_Data_In_St DIO_Parallel_Data_In_St DIO_Serial_Data_In_St DIO_Parallel_Data_In_St DIO_Serial_Data_In_St DIO_Parallel_Data_In_St DIO_Serial_Data_In_St DIO_Parallel_Data_In_St DIO_Serial_Data_In_St DIO_Parallel_Data_In_St DIO_Serial_Data_In_St DAQ-STC Technical Reference Manual B-26 © National Instruments Corporation...
Page 476 G0_HW_Save_Value Reserved G0_HW_Save_Value Reserved G0_HW_Save_Value Reserved G0_HW_Save_Value Reserved G0_HW_Save_Value Reserved G0_HW_Save_Value Reserved G0_HW_Save_Value Reserved G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value G0_HW_Save_Value © National Instruments Corporation B-27 DAQ-STC Technical Reference Manual...
Page 477 Reserved G0_Load_A Reserved G0_Load_A Reserved G0_Load_A Reserved G0_Load_A Reserved G0_Load_A Reserved G0_Load_A Reserved G0_Load_A Reserved G0_Load_A G0_Load_B G0_Load_A G0_Load_B G0_Load_A G0_Load_B G0_Load_A G0_Load_B G0_Load_A G0_Load_B G0_Load_A G0_Load_B G0_Load_A G0_Load_B G0_Load_A G0_Load_B DAQ-STC Technical Reference Manual B-28 © National Instruments Corporation...
Page 478 G0_Save_Value Reserved G0_Save_Value Reserved G0_Save_Value Reserved G0_Save_Value Reserved G0_Save_Value Reserved G0_Save_Value Reserved G0_Save_Value Reserved G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value G0_Save_Value © National Instruments Corporation B-29 DAQ-STC Technical Reference Manual...
Page 479 G1_GW_Save_Value Reserved G1_GW_Save_Value Reserved G1_GW_Save_Value Reserved G1_GW_Save_Value Reserved G1_GW_Save_Value Reserved G1_GW_Save_Value Reserved G1_GW_Save_Value Reserved G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value G1_GW_Save_Value DAQ-STC Technical Reference Manual B-30 © National Instruments Corporation...
Page 480 Reserved G1_Load_A Reserved G1_Load_A Reserved G1_Load_A Reserved G1_Load_A Reserved G1_Load_A Reserved G1_Load_A Reserved G1_Load_A Reserved G1_Load_A G1_Load_B G1_Load_A G1_Load_B G1_Load_A G1_Load_B G1_Load_A G1_Load_B G1_Load_A G1_Load_B G1_Load_A G1_Load_B G1_Load_A G1_Load_B G1_Load_A G1_Load_B © National Instruments Corporation B-31 DAQ-STC Technical Reference Manual...
Page 481 G1_Save_Value Reserved G1_Save_Value Reserved G1_Save_Value Reserved G1_Save_Value Reserved G1_Save_Value Reserved G1_Save_Value Reserved G1_Save_Value Reserved G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value G1_Save_Value DAQ-STC Technical Reference Manual B-32 © National Instruments Corporation...
Page 482 Reserved G0_TC_Interrupt_Ack Reserved AI_Error_Interrupt_Ack Reserved AI_STOP_Interrupt_Ack Reserved AI_START_Interrupt_Ack Reserved AI_START2_Interrupt_Ack Reserved AI_START1_Interrupt_Ack Pass_Thru_0_Interrupt_Enable AI_SC_TC_Interrupt_Ack G0_Gate_Interrupt_Enable AI_SC_TC_Error_Confirm AI_FIFO_Interrupt_Enable G0_TC_Error_Confirm G0_TC_Interrupt_Enable G0_Gate_Error_Confirm AI_Error_Interrupt_Enable Reserved AI_STOP_Interrupt_Enable Reserved AI_START_Interrupt_Enable Reserved AI_START2_Interrupt_Enable Reserved AI_START1_Interrupt_Enable Reserved AI_SC_TC_Interrupt_Enable © National Instruments Corporation B-33 DAQ-STC Technical Reference Manual...
Page 483 Reserved Interrupt_B_Output_Select Reserved Interrupt_B_Output_Select Reserved Interrupt_B_Output_Select Reserved Interrupt_A_Enable Reserved Interrupt_A_Output_Select Reserved Interrupt_A_Output_Select BD_9_Pin_Dir Interrupt_A_Output_Select BD_9_Pin_Dir Reserved BD_9_Pin_Dir Reserved BD_9_Pin_Dir Reserved BD_9_Pin_Dir Reserved BD_9_Pin_Dir Pass_Thru_0_Interrupt_Polarity BD_9_Pin_Dir Pass_Thru_1_Interrupt_Polarity BD_9_Pin_Dir Interrupt_Output_On_3_Pins BD_9_Pin_Dir Interrupt_Output_Polarity BD_9_Pin_Dir DAQ-STC Technical Reference Manual B-34 © National Instruments Corporation...
Page 484 RTSI_Board_3_Pin_Dir G0_Permanent_Stale_Data_St RTSI_Board_2_Pin_Dir G1_HW_Save_St RTSI_Board_1_Pin_Dir G0_HW_Save_St RTSI_Board_0_Pin_Dir Generic_Status RTSI_Board_3_Output_Select Generic_Status RTSI_Board_3_Output_Select Generic_Status RTSI_Board_3_Output_Select Generic_Status RTSI_Board_2_Output_Select AI_Scan_In_Progress_St RTSI_Board_2_Output_Select AI_Config_Memory_Empty_St RTSI_Board_2_Output_Select AO_TMRDACWRs_In_Progress_St RTSI_Board_1_Output_Select AI_EOC_St RTSI_Board_1_Output_Select AI_SOC_St RTSI_Board_1_Output_Select AO_STOP_St RTSI_Board_0_Output_Select G1_Output_St RTSI_Board_0_Output_Select G0_Output_St RTSI_Board_0_Output_Select © National Instruments Corporation B-35 DAQ-STC Technical Reference Manual...
Page 485 Reserved RTSI_Trig_5_Pin_Dir Reserved RTSI_Trig_4_Pin_Dir Reserved RTSI_Trig_3_Pin_Dir Reserved RTSI_Trig_2_Pin_Dir Reserved RTSI_Trig_1_Pin_Dir Reserved RTSI_Trig_0_Pin_Dir Pass_Thru_0_Second_Irq_Enable Reserved G0_Gate_Second_Irq_Enable Reserved AI_FIFO_Second_Irq_Enable Reserved G0_TC_Second_Irq_Enable Reserved AI_Error_Second_Irq_Enable Reserved AI_STOP_Second_Irq_Enable Reserved AI_START_Second_Irq_Enable Reserved AI_START2_Second_Irq_Enable RTSI_Clock_Mode AI_START1_Second_Irq_Enable RTSI_Clock_Mode AI_SC_TC_Second_Irq_Enable DAQ-STC Technical Reference Manual B-36 © National Instruments Corporation...
Page 486 Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved Window_Data Reserved © National Instruments Corporation B-37 DAQ-STC Technical Reference Manual...
Page 487 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Write_Strobe_1 Write_Strobe_2 Write_Strobe_3_Register Address: 85 Type: Write-only Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Write_Strobe_3 DAQ-STC Technical Reference Manual B-38 © National Instruments Corporation...
Page 488: Table C-1. Daq-Stc Pins In Alphabetical Order
Refer to Table C-1 for a description of the buffer types. Table C-1. DAQ-STC Pins in Alphabetical Order Pin Name Pin Number Buffer Type AI_FIFO_SHIFTIN* O9TU AI_STOP_IN AI_STOP_OUT O4TU AIFEF* AIFFF* AIFHF* AIFREQ O4TU ANALOG_TRIG_DRIVE O4TU ANALOG_TRIG_IN_HI ANALOG_TRIG_IN_LO © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 489 AOFHF* AOFREQ O9TU BC_TC O4TU CHRDY_IN CHRDY_OUT OD18U CONVERT* O9TU CPUDACREQ* CPUDACWR* O4TU CTRL0 O4TU CTRL1 O4TU CTRL2 O4TU CTRL3 O4TU CTRL4 O4TU CTRL5 O4TU CTRL6 O4TU CTRL7 O4TU B9TU B9TU B9TU DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 490 B9TU B9TU B9TU B9TU B9TU B9TU DACWR*0 O4TU DACWR*1 O4TU DIO0/SDOUT B18TU DIO1 B18TU DIO2 B18TU DIO3 B18TU DIO4/SDIN B18TU DIO5 B18TU DIO6 B18TU DIO7 B18TU DIV_TC O4TU EXTMUX_CLK O9TU EXTSTROBE*/SDCLK O9TU © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 491 G_UP_DOWN1 ID/IU GHOST — — — — — — — — — — INTEL/MOTO* IRQ_IN0 IRQ_IN1 IRQ_OUT0 OD18U IRQ_OUT1 OD18U IRQ_OUT2 OD18U IRQ_OUT3 OD18U IRQ_OUT4 OD18U IRQ_OUT5 OD18U IRQ_OUT6 OD18U IRQ_OUT7 OD18U DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 492 PFI3/G_SRC1 B9TU PFI4/G_GATE1 B9TU PFI5/UPDATE* B9TU PFI6/AO_START1 B9TU PFI7/AI_START B9TU PFI8/G_SRC0 B9TU PFI9/G_GATE0 B9TU RD/WR* RESET* RTSI_BRD0 B9TU RTSI_BRD1 B9TU RTSI_BRD2 B9TU RTSI_BRD3 B9TU RTSI_OSC B9TU RTSI_TRIGGER0 B9TU RTSI_TRIGGER1 B9TU RTSI_TRIGGER2 B9TU © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 493 O9TU SCAN_IN_PROG 04TU SEC_IRQ_OUT_BANK0 OD18U SEC_IRQ_OUT_BANK1 OD18U SHIFTIN* O9TU SI_TC O4TU STATUS0 STATUS1 STATUS2 STATUS3 TEST_IN* TEST_OUT TMRDACREQ O9TU TMRDACWR* O4TU UC_TC O4TU UPDATE* O9TU UPDATE2* O9TU — — — — — DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 494: Table C-2. Summary Of Buffer Types
— CMOS 3 State 50 k Up –2.5 — 50 k Down — — TTL Schmitt — — — — — 50 k Up — — — 5 k Up — — © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 495 Appendix C Pin List Note Pull-up/pull-down resistance values are as follows: Resistance (kΩ) Nominal Value Minimum Typical Maximum 50 kΩ 5 kΩ DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 496 It is not the same as the CCA number typically printed on a label and located on the front of the board. Product Name PWB Number AT-MIO-16E-1 183020B-01 AT-MIO-16E-2 182412D-01 AT-MIO-64E-10 182642B-01 AT-MIO-16DE-10 182637C-01 AT-MIO-16XE-50 182542C-01 PCI-MIO-16XE-50 183118C-01 DAQPad-MIO-16XE-50 182951A-01 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 497 Appendix D DAQ-STC Revision History Product Name PWB Number NEC-MIO-16E-4 182397C-01 NEC-AI-16E-4 182397C-01 NEC-MIO-16XE-50 182832A-01 NEC-AI-16XE-50 182832A-01 SB-MIO-16E-4 182467C-01 VXI-MIO-64E-1 183006C-01 VXI-MIO-64XE-10 183392B-01 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 498 Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24-hour support with a collection of files and documents to answer most common customer questions. From these sites, you can also download the latest instrument drivers, updates, and example programs. For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information, call 512 795 6990.
Page 499 Telephone and Fax Support National Instruments has branch offices all over the world. Use the list below to find the technical support number for your country. If there is no National Instruments office in your country, contact the source from which you purchased your software to obtain support.
Page 500 National Instruments for technical support helps our applications engineers answer your questions more efficiently. If you are using any National Instruments hardware or software products related to this problem, include the configuration forms from their user manuals. Include additional pages if necessary.
Page 501 Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Page 502 Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: ™ DAQ-STC Technical Reference Manual Edition Date: January 1999 Part Number: 340934B-01 Please comment on the completeness, clarity, and organization of the manual.
Page 503 AI data FIFO empty flag ADFFF AI data FIFO full flag ADFHF AI data FIFO empty flag ADFREQ AI data FIFO half-full flag ADR_START1 internal START1 signal without Master/Slave synchronization ADR_START2 START2 signal without master/slave synchronization © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 504 AI_TB1 internal analog input signal AI_IN_TIMEBASE1 ANALOG_TRIG_DRIVE analog trigger drive signal ANALOG_TRIG_IN_HI analog trigger input high voltage reference ANALOG_TRIG_IN_LO analog input trigger low voltage reference analog output AO START1 AO start signal DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 505 24-bit buffer repetition counter BC_CE BC count enable signal BC_CLK BC clock signal binary coded decimal BC_DISARM BC disarm signal BC_HOLD BC hold signal BC_LOAD BC load signal BC_LOAD_SRC BC load source signal © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 506 CTROUT counter output signal CTRSRC general purpose counter source signal D<0..15> bidirectional tri-state data bus signals digital-to-analog D/A converter DACUPDN DAC update signal DACWR<0..1> DAC write strobe 0 through 1 data acquisition DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 507 EXTMUX_CLK external multiplexer clock signal EXTSTROBE external strobe signal EXTSTROBE/SDCLK external strobe serial data clock signal EXT_CLK external clock signal EXT_DIVTC external DIV_TC signal EXT_GATE external gate signal © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 508 GPCT counter control signal G_GATE GPCT gate input signal G_IN_TIMEBASE1 internal timebase for GPCT module G_OUT GPCT output signal G_TB1 internal signal G_IN_TIMEBASE1 G_TC GPCT counter TC signal G_UP_DOWN GPCT up/down control input signal DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 509 IN_TIMEBASE2 slow internal timebase signal input/output high-level output current low-level output current IRQ_IN<0..1> individually programmable polarity general-purpose interrupt input signal IRQ_OUT<0..7> programmable polarity interrupt output signal Industry Standard Architecture interrupt service program © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 510 Multiple Iterations of a Single Buffer most significant bit multiplexer MUXFEF configuration FIFO empty flag signal oscillator source signal OUTBRD_OSC oscillator source signal for output to the board OUT_CLK AI_OUT_TIMEBASE signal programmable function input DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 511 Return Manual Authorization RTSI trigger module RTSI Real-Time System Integration RTSI_BRD<0..3> RTSI board interface signal, channels 0 through 3 RTSI_OSC RTSI oscillator source signal RTSI_TRIGGER<0..6> RTSI trigger signal, channels 0 through 6 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 512 A SEC_IRQ_OUT_BANK1 secondary interrupt output for interrupt group B SEL<0..4> select signal, channels 0 through 4 SHIFTIN data shift pulse signal 24-bit scan interval counter DAQ-STC Technical Reference Manual G-10 © National Instruments Corporation...
Page 513 SC counter in the pretrigger mode STATUS<0..3> status signal, channels 0 through 3 STOP stop scan signal that terminates the buffer in progress STST_GATE start/stop gate signal software © National Instruments Corporation G-11 DAQ-STC Technical Reference Manual...
Page 514 UI2_CE UI2 count enable signal t UI2_CLK UI2 clock signal and the UI2 control logic UI2_LOAD UI2 load signal UI2_LOAD_SRC UI2 load source signal DAQ-STC Technical Reference Manual G-12 © National Instruments Corporation...
Page 515 WR/DS in Intel mode, a write cycle signal in Motorola mode, a read cycle signal WRITE_STROBE<0..3> general-purpose write strobe signal, channels 0 through 3 © National Instruments Corporation G-13 DAQ-STC Technical Reference Manual...
Page 516 AI_CONVERT_Source_Select bit, 2-51 AI_FIFO_SHIFTIN signal AI_Delay_START bit, 2-52 description (table), 2-19 AI_Delayed_START bit, 2-51 simplified analog input model, 2-5 to 2-6 AI_Delayed_START2 bit, 2-52 AI_Hardware_Gating function, 2-30 to 2-31 AI_Disarm bit, 2-52 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 517 AI_SI2_Next_Load_Source_St bit, 2-72 AI_SC_TC_Interrupt_Ack bit, 2-65 AI_SI2_Q_St bit, 2-72 AI_SC_TC_Interrupt_Enable bit, 2-65 AI_SI2_Reload_Mode bit, 2-72 AI_SC_TC_Output_Select bit, 2-66 AI_SI2_Save_Value bit, 2-72 AI_SC_TC_Pulse bit, 2-66 AI_SI2_Source_Select bit, 2-73 AI_SC_TC_Second_Irq_Enable bit, 2-66 AI_SOC_Polarity bit, 2-73 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 518 2-16 AI_START2_St bit, 2-80 posttrigger acquisition mode, 2-14 AI_START2_Sync bit, 2-80 pretrigger acquisition mode, AI_STOP_Edge bit, 2-81 2-14 to 2-15 AI_STOP_IN signal (table), 2-20 staged acquisition, 2-16 AI_STOP_Interrupt_Ack bit, 2-81 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 519 2-2 to 2-3 windowing registers, 2-25 internal signals and operation (table), simplified model, 2-4 to 2-6 2-113 to 2-119 specifications, A-1 interrupt control, 2-130 to 2-131 macro-level analog input timing, 2-106 to 2-108 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 520 3-30 to 3-31 continuous mode, 3-13 to 3-14 stop on error, 3-29 master/slave trigger, 3-15 to 3-16 trigger signals, 3-23 to 3-24 mute buffers, 3-15 update selection, 3-26 to 3-28 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 521 (figure), 10-5 nominal signal pulsewidths, 3-124 high-window mode (figure), 10-4 output control, 3-123 to 3-124 low-hysteresis mode (figure), 10-6 overview, 3-1 to 3-2 low-window mode (figure), 10-4 pin interface (table), 3-16 to 3-20 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 522 AO_BC_Source_Select bit, 3-49 AO_FIFO_Mode bit, 3-57 AO_BC_Switch_Load_On_TC bit, 3-49 AO_FIFO_Request_St bit, 3-57 AO_BC_TC_Error_Confirm bit, 3-49 AO_FIFO_Retransmit_Enable bit, 3-57 AO_BC_TC_Error_St bit, 3-49 AO_FIFO_Second_Irq_Enable bit, 3-57 AO_BC_TC_Interrupt_Ack bit, 3-50 AO_IN_TIMEBASE signal (table), 3-110 AO_BC_TC_Interrupt_Enable bit, 3-50 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 523 AO_START1_Polarity bit, 3-64 AO_UI_Count_Enabled_St bit, 3-72 AO_START1_Pulse bit, 3-64 AO_UI_Initial_Load_Source bit, 3-72 AO_START1_Second_Irq_Enable bit, 3-65 AO_UI_Load_A bit, 3-72 AO_START1_Select bit, 3-65 AO_UI_Load_B bit, 3-73 AO_START1_St bit, 3-65 AO_UI_Load bit, 3-72 AO_START1_Sync bit, 3-65 DAQ-STC Technical Reference Manual © National Instruments Corporation...
Page 524 (table), 3-17 AO_UI2_TC_St bit, 3-79 simplified analog output model, 3-5 AO_UPDATE_Interrupt_Ack bit, 3-81 AOFFRT* signal AO_UPDATE_Interrupt_Enable bit, 3-81 description (table), 3-17 AO_UPDATE_Original_Pulse bit, 3-82 local buffer mode, 3-9 to 3-10 AO_UPDATE_Output_Select bit, 3-82 © National Instruments Corporation DAQ-STC Technical Reference Manual...
Page 525 BC_TC error, 3-123 AI_Error_Interrupt_Ack, 2-54 BC_TC signal AI_Error_Interrupt_Enable, 2-54 continuous-mode, 3-13 to 3-14 AI_Error_Second_Irq_Enable, 2-54 description (table), 3-17, 3-111 AI_External_Gate_Mode, 2-55 output timing (figure), 3-107 AI_External_Gate_Polarity, single-buffer mode, 3-13 2-31, 2-55 DAQ-STC Technical Reference Manual I-10 © National Instruments Corporation...
Page 526 AI_SC_Load, 2-63 AI_SI_Switch_Load_On_Stop, 2-70 AI_SC_Load_A, 2-63 AI_SI_Switch_Load_On_TC, 2-70 AI_SC_Load_B, 2-63 AI_SI_Write_Switch, 2-71 AI_SC_Next_Load_Source_St, 2-63 AI_SI2_Arm, 2-71 AI_SC_Q_St, 2-64 AI_SI2_Armed_St, 2-71 AI_SC_Reload_Mode, 2-64 AI_SI2_Initial_Load_Source, 2-71 AI_SC_Save_St, 2-64 AI_SI2_Load, 2-71 AI_SC_Save_Trace, 2-64 AI_SI2_Load_A, 2-71 © National Instruments Corporation I-11 DAQ-STC Technical Reference Manual...
Page 527 AI_START1_Select, 2-78 AO_BC_Save_Trace, 3-48 AI_START1_St, 2-78 AO_BC_Save_Value, 3-49 AI_START1_Sync, 2-78 AO_BC_Source_Select, 3-49 AI_START2_Edge, 2-79 AO_BC_Switch_Load_On_TC, 3-49 AI_START2_Interrupt_Ack, 2-79 AO_BC_TC_Error_Confirm, 3-49 AI_START2_Interrupt_Enable, 2-79 AO_BC_TC_Error_St, 3-49 AI_START2_Interrupt_Polarity, AO_BC_TC_Interrupt_Ack, 3-50 2-79 AO_BC_TC_Interrupt_Enable, 3-50 AI_START2_Interrupt_Pulse, 2-79 DAQ-STC Technical Reference Manual I-12 © National Instruments Corporation...
Page 528 AO_FIFO_Retransmit_Enable, 3-57 AO_STOP_Interrupt_Enable, 3-66 AO_FIFO_Second_Irq_Enable, 3-57 AO_Stop_On_BC_TC_Error, 3-66 AO_Interval_Buffer_Mode, 3-58 AO_Stop_On_BC_TC_Trigger_ AO_LDACi_Source_Select, 3-58 Error, 3-66 AO_Multiple_Channels, 3-58 AO_Stop_On_Overrun_Error, 3-66 AO_Mute_A, 3-58 AO_STOP_Second_Irq_Enable, AO_Mute_B, 3-59 3-67 AO_Not_An_UPDATE, 3-59 AO_STOP_St, 3-67 AO_Number_Of_Channels, 3-59 © National Instruments Corporation I-13 DAQ-STC Technical Reference Manual...
Page 529 AO_UI_Arm, 3-71 AO_UI2_Source_Select, 3-78 AO_UI_Armed_St, 3-72 AO_UI2_Switch_Load_Next_TC, AO_UI_Count_Enabled_St, 3-72 3-78 AO_UI_Initial_Load_Source, 3-72 AO_UI2_TC_Error_Confirm, 3-78 AO_UI_Load, 3-72 AO_UI2_TC_Error_St, 3-79 AO_UI_Load_A, 3-72 AO_UI2_TC_Interrupt_Ack, 3-79 AO_UI_Load_B, 3-73 AO_UI2_TC_Interrupt_Enable, 3-79 AO_UI_Next_Load_Source_St, 3-73 AO_UI2_TC_Second_Irq_Enable, AO_UI_Q_St, 3-73 3-79 DAQ-STC Technical Reference Manual I-14 © National Instruments Corporation...
Page 530 I/O, 7-13 to 7-15 Gi_Gate_St, 4-41 Control, 7-13 Gi_Gating_Mode, 4-41 DIO_HW_Serial_Enable, 7-13 Gi_HW_Save_St, 4-42 DIO_HW_Serial_Start, 7-13 Gi_HW_Save_Value, 4-42 DIO_HW_Serial_Timebase, 7-14 Gi_Little_Big_Endian, 4-42 DIO_Parallel_Data_In_St, 7-14 Gi_Load, 4-42 DIO_Parallel_Data_Out, 7-14 Gi_Load_A, 4-43 DIO_Pins_Dir, 7-14 Gi_Load_B, 4-43 © National Instruments Corporation I-15 DAQ-STC Technical Reference Manual...
Page 531 GPFO_1_Output_Enable, 4-52 analog input programming GPFO_1_Output_Select, 4-52 considerations, 2-24 interrupt control, 8-12 to 8-14 guide to location in manual (table), B-9 Interrupt_A_Enable, 8-12 block diagram for DAQ-STC, 1-4 Interrupt_A_Output_Select, 8-12 DAQ-STC Technical Reference Manual I-16 © National Instruments Corporation...
Page 532 9-4 continuous mode, buffer timing and control, timing diagrams, 9-5 to 9-8 primary analog output, 3-13 to 3-14 Intel bus interface read timing Continuous_Pulse_Train_Generation (figure), 9-6 function, 4-30 to 4-31 © National Instruments Corporation I-17 DAQ-STC Technical Reference Manual...
Page 533 4-9 to 4-12 analog input timing/control module buffered retriggerable single pulse generation, 4-11 to 4-12 DIV_TC signal (figure), 2-106 retriggerable single pulse SC_TC signal (figure), 2-105 generation, 4-11 SI_TC signal (figure), 2-105 DAQ-STC Technical Reference Manual I-18 © National Instruments Corporation...
Page 534 3-101 DAQ-STC- and CPU-driven analog output simplified analog output model, 3-4 timing, 3-90 to 3-92 unbuffered data interface, 3-11 DAQ-STC registers. See registers. DAQ-STC-driven analog output, 3-6 © National Instruments Corporation I-19 DAQ-STC Technical Reference Manual...
Page 535 DIV counter operation, 2-129 example, 7-7 to 7-8 DIV_CLK signal (table), 2-114 serial mode, 7-4 to 7-5 DIV_DISARM signal, DIV counter serial input, 7-4 operation, 2-129 serial I/O, 7-5 serial output, 7-4 to 7-5 DAQ-STC Technical Reference Manual I-20 © National Instruments Corporation...
Page 536 4-4 to 4-5 about this manual, xxiii programming conventions used in manual, xxv buffered event counting, 4-20 to 4-22 National Instruments documentation, xxvi relative position sensing, 4-23 to 4-24 organization of manual, xxiii-xxiv simple event counting, 4-19 to 4-20 related documentation, xxvi-xxvii...
Page 537 FOUT_Divider bit, 10-13 synchronous mode (figure), 3-106 FOUT_Enable bit, 10-14 EXTMUX_CLK signal FOUT signal configuration FIFO control and external description (table), 10-10 multiplexer control, 2-8 programming, 10-12 purpose and use, 10-3 DAQ-STC Technical Reference Manual I-22 © National Instruments Corporation...
Page 538 4-14 to 4-15 generation, 4-13 minimum pulsewidth, 4-56 continuous pulse-train generation, pulse generation for ETS, 4-15 4-12 to 4-13 retriggerable single pulse relative position sensing, 4-6 generation, 4-11 © National Instruments Corporation I-23 DAQ-STC Technical Reference Manual...
Page 539 4-55 to 4-56 pulse generation, 4-9 to 4-12 CTR_U/D reference pin selection pulse-train generation, 4-12 to 4-15 (table), 4-54 time measurement, 4-6 to 4-9 G_GATE minimum pulsewidth, 4-56 features, 4-1 to 4-2 DAQ-STC Technical Reference Manual I-24 © National Instruments Corporation...
Page 540 Gi_Little_Big_Endian bit, 4-42 GPFO_0_Output_Enable bit, 4-51 Gi_Load_A bit, 4-43 GPFO_0_Output_Select bit, 4-52 Gi_Load_B bit, 4-43 GPFO_1_Output_Enable bit, 4-52 Gi_Load bit, 4-42 GPFO_1_Output_Select bit, 4-52 Gi_Load_Source_Select bit, 4-43 Gi_Loading_On_Gate bit, 4-44 Gi_Loading_On_TC bit, 4-44 © National Instruments Corporation I-25 DAQ-STC Technical Reference Manual...
Page 541 START and SCAN_IN_PROG trigger overview, 8-1 output, 2-101 pin interface (table), 8-2 START trigger output, 2-101 interrupt latency, 3-32, 3-42 START1 and START2 triggers in Interrupt_Output_On_3_Pins bit, 8-13 synchronous mode, 2-97 to 2-98 DAQ-STC Technical Reference Manual I-26 © National Instruments Corporation...
Page 542 (figure), 10-4 maximum rate analog input, 2-91 to 2-92 low-hysteresis mode (figure), 10-6 nominal pulsewidths (table), 2-133 low-window mode (figure), 10-4 simplified analog input model, 2-5 middle-window mode (figure), 10-5 © National Instruments Corporation I-27 DAQ-STC Technical Reference Manual...
Page 543 MSC_Write_Strobe function, 9-4 analog input timing/control MSC_IO_Pin_Configure function, 5-5 to 5-6 module, 2-132 MSC_RTSI_Pin_Configure function, 6-3 analog output timing/control multiplexer control, external, 2-7 to 2-9 module, 3-122 mute buffers, 3-15 DAQ-STC Technical Reference Manual I-28 © National Instruments Corporation...
Page 544 (table), 8-2 3-115 to 3-116 miscellaneous functions (table), PFI signals 10-9 to 10-10 CTRGATE reference pin selection PFI module (table), 5-2 to 5-5 (table), 4-54 © National Instruments Corporation I-29 DAQ-STC Technical Reference Manual...
Page 545 FIFO mode, 3-29 to 3-30 board environment setup, interrupts, 3-35 to 3-37 2-29 to 2-30 LDAC source and UPDATE board power-up initialization, mode, 3-29 2-27 to 2-28 master/slave operation considerations, 3-35 DAQ-STC Technical Reference Manual I-30 © National Instruments Corporation...
Page 546 7-13 clock distribution, 10-10 to 10-11 software-controlled serial digital FOUT, 10-12 I/O, 7-12 PFI module, 5-5 to 5-6 windowed mode register access pulse generation for ETS, 4-15 example, 7-7 to 7-8 © National Instruments Corporation I-31 DAQ-STC Technical Reference Manual...
Page 547 4-24 to 4-25 general-purpose counter/timer single-pulsewidth measurement, 4-7 module, 4-18 pulsewidths, nominal retriggerable single pulse generation, 4-11 analog input timing/control module revision history for DAQ-STC, D-1 to D-2 (table), 2-133 RTSI_Board_i_Output_Select bit, 6-4 DAQ-STC Technical Reference Manual I-32 © National Instruments Corporation...
Page 548 MSC_RTSI_Pin_Configure 2-100 to 2-102 function, 6-3 external CONVERT mode, 2-102 RTSI_BRD<0..1> output selections (table), 6-7 internal CONVERT mode, 2-101 RTSI_BRD<2..3> output selections deassertion, analog input trigger (table), 6-7 output, 2-103 © National Instruments Corporation I-33 DAQ-STC Technical Reference Manual...
Page 549 SI2 counter serial link data interface, 3-10 control circuitry, 2-127 to 2-128 serial mode, digital I/O, 7-4 to 7-5 description, 2-127 hardware-controlled serial digital I/O, 7-10 to 7-12 serial input, 7-4 DAQ-STC Technical Reference Manual I-34 © National Instruments Corporation...
Page 550 4-4 analog input programming, 2-44 to 2-45 programming, 4-19 to 4-20 description, 2-16 simple gated-event counting, 4-4 start of scans, analog input programming, 2-34 to 2-37 © National Instruments Corporation I-35 DAQ-STC Technical Reference Manual...
Page 551 (figure), 2-120 trigger output, 2-103 to 2-104 START1 signal, analog output timing/control asynchronous mode (figure), 2-104 module synchronous mode (figure), 2-104 continuous-mode, 3-14 trigger routing logic (figure), 2-120 DAQ-STC Technical Reference Manual I-36 © National Instruments Corporation...
Page 552 9-6 to 9-7 data FIFOs, 2-88 Intel bus interface write timing external CONVERT source, (figure), 9-6 2-92 to 2-93 Motorola bus interface read timing external triggers, 2-93 to 2-97 (figure), 9-7 © National Instruments Corporation I-37 DAQ-STC Technical Reference Manual...
Page 553 3-96 to 3-97 analog output timing/control module, maximum update rate timing, 3-101 3-114 to 3-116 serial link data interface, 3-10 edge detection, 3-116 simplified analog output model, 3-4 DAQ-STC Technical Reference Manual I-38 © National Instruments Corporation...
Page 554 FIFO data interface, 3-9 UI_DISARM signal (table), 3-113 internal UPDATE timing, 3-11 to 3-12 UI_LOAD signal (table), 3-113 local buffer mode timing, 3-96 to 3-97 UI_LOAD_SRC signal (table), 3-113 maximum update rate timing, 3-101 © National Instruments Corporation I-39 DAQ-STC Technical Reference Manual...
Page 555 3-42 to 3-44 counting, 3-40 windowed mode register access analog input programming considerations, 2-25 digital I/O programming example, 7-7 to 7-8 WR/DS* signal (table), 9-3 WRITE_STROBE<0..3> signal description (table), 9-3 programming, 9-4 DAQ-STC Technical Reference Manual I-40 © National Instruments Corporation...