Two 40-Pin Expansion Headers - Arrow BeMicro Max 10 Getting Started User Manual

Pinout Information for MAX 10 FPGA I/O Pinout Information for MAX 10 FPGA I/O Pinout Information for MAX 10 FPGA I/O

3.5.2 Two 40-pin Expansion Headers

3.5.2 Two 40-pin Expansion Headers 3.5.2 Two 40-pin Expansion Headers
Two 40-pin prototyping headers, J3 and J4, provide access to single ended digital signals, differential LVDS transmit Two 40-pin prototyping headers, J3 and J4, provide access to single ended digital signals, differential LVDS transmit Two 40-pin prototyping headers, J3 and J4, provide access to single ended digital signals, differential LVDS transmit
pairs and differential receive pairs. The pinout for these connectors match the pinout of several daughter cards pairs and differential receive pairs. The pinout for these connectors match the pinout of several daughter cards pairs and differential receive pairs. The pinout for these connectors match the pinout of several daughter cards
available from third-party vendors such as Terasic. available from third-party vendors such as Terasic. available from third-party vendors such as Terasic.
Signal Name Signal Name Signal Name MAX 10 Pin MAX 10 Pin MAX 10 Pin
GPIO_01 GPIO_01 GPIO_01 B2 B2 B2
GPIO_02 GPIO_02 GPIO_02 B1 B1 B1
GPIO_03 GPIO_03 GPIO_03 C3 C3 C3
GPIO_04 GPIO_04 GPIO_04 A2 A2 A2
GPIO_05 GPIO_05 GPIO_05 B3 B3 B3
GPIO_06 GPIO_06 GPIO_06 A3 A3 A3
GPIO_07 GPIO_07 GPIO_07 B4 B4 B4
GPIO_08 GPIO_08 GPIO_08 A4 A4 A4
GPIO_09 GPIO_09 GPIO_09 B5 B5 B5
GPIO_10 GPIO_10 GPIO_10 A5 A5 A5
GPIO_11 GPIO_11 GPIO_11 B7 B7 B7
GPIO_12 GPIO_12 GPIO_12 A6 A6 A6
DIFF_RX_P[0] DIFF_RX_P[0] DIFF_RX_P[0] K14 K14 K14
DIFF_RX_P[0](n) DIFF_RX_P[0](n) DIFF_RX_P[0](n) K15 K15 K15
DIFF_RX_P[1] DIFF_RX_P[1] DIFF_RX_P[1] E16 E16 E16
DIFF_RX_P[1](n) DIFF_RX_P[1](n) DIFF_RX_P[1](n) E15 E15 E15
DIFF_RX_P[2] DIFF_RX_P[2] DIFF_RX_P[2] D17 D17 D17
DIFF_RX_P[2](n) DIFF_RX_P[2](n) DIFF_RX_P[2](n) C17 C17 C17
DIFF_RX_P[3] DIFF_RX_P[3] DIFF_RX_P[3] H14 H14 H14
DIFF_RX_P[3](n) DIFF_RX_P[3](n) DIFF_RX_P[3](n) J13 J13 J13
DIFF_RX_P[4] DIFF_RX_P[4] DIFF_RX_P[4] C14 C14 C14
DIFF_RX_P[4](n) DIFF_RX_P[4](n) DIFF_RX_P[4](n) C13 C13 C13
DIFF_RX_P[5] DIFF_RX_P[5] DIFF_RX_P[5] A14 A14 A14
DIFF_RX_P[5](n) DIFF_RX_P[5](n) DIFF_RX_P[5](n) B14 B14 B14
DIFF_RX_P[6] DIFF_RX_P[6] DIFF_RX_P[6] D14 D14 D14
DIFF_RX_P[6](n) DIFF_RX_P[6](n) DIFF_RX_P[6](n) E13 E13 E13
DIFF_RX_P[7] DIFF_RX_P[7] DIFF_RX_P[7] E12 E12 E12
DIFF_RX_P[7](n) DIFF_RX_P[7](n) DIFF_RX_P[7](n) D13 D13 D13
DIFF_RX_P[8] DIFF_RX_P[8] DIFF_RX_P[8] H12 H12 H12
DIFF_RX_P[8](n) DIFF_RX_P[8](n) DIFF_RX_P[8](n) J11 J11 J11
DIFF_RX_P[9] DIFF_RX_P[9] DIFF_RX_P[9] B10 B10 B10
DIFF_RX_P[9](n) DIFF_RX_P[9](n) DIFF_RX_P[9](n) C9 C9 C9
DIFF_RX_P[10] DIFF_RX_P[10] DIFF_RX_P[10] A9 A9 A9
DIFF_RX_P[10](n) B8 DIFF_RX_P[10](n) B8 DIFF_RX_P[10](n) B8
DIFF_RX_P[11] DIFF_RX_P[11] DIFF_RX_P[11] A7 A7 A7
DIFF_RX_P[11](n) A8 DIFF_RX_P[11](n) A8 DIFF_RX_P[11](n) A8
BeMicro Max 10 Getting Started User Guide, Version 14.0 BeMicro Max 10 Getting Started User Guide, Version 14.0 BeMicro Max 10 Getting Started User Guide, Version 14.0
J3 Pin J3 Pin J3 Pin Signal Name Signal Name Signal Name
1 1 1 I2C_SDA I2C_SDA I2C_SDA
2 2 2 I2C_SCL I2C_SCL I2C_SCL
3 3 3 GPIO_A GPIO_A GPIO_A
4 4 4 GPIO_B GPIO_B GPIO_B
5 5 5 LVDS_TX_P[0] LVDS_TX_P[0] LVDS_TX_P[0]
6 6 6 LVDS_TX_P[0](n) LVDS_TX_P[0](n) LVDS_TX_P[0](n)
7 7 7 LVDS_TX_P[1] LVDS_TX_P[1] LVDS_TX_P[1]
8 8 8 LVDS_TX_P[1](n) LVDS_TX_P[1](n) LVDS_TX_P[1](n)
9 9 9 LVDS_TX_P[2] LVDS_TX_P[2] LVDS_TX_P[2]
10 10 10 LVDS_TX_P[2](n) LVDS_TX_P[2](n) LVDS_TX_P[2](n)
13 13 13 LVDS_TX_P[3] LVDS_TX_P[3] LVDS_TX_P[3]
14 14 14 LVDS_TX_P[3](n) LVDS_TX_P[3](n) LVDS_TX_P[3](n)
39 39 39 LVDS_TX_P[4] LVDS_TX_P[4] LVDS_TX_P[4]
40 40 40 LVDS_TX_P[4](n) LVDS_TX_P[4](n) LVDS_TX_P[4](n)
37 37 37 LVDS_TX_P[5] LVDS_TX_P[5] LVDS_TX_P[5]
38 38 38 LVDS_TX_P[5](n) LVDS_TX_P[5](n) LVDS_TX_P[5](n)
35 35 35 LVDS_TX_P[6] LVDS_TX_P[6] LVDS_TX_P[6]
36 36 36 LVDS_TX_P[6](n) LVDS_TX_P[6](n) LVDS_TX_P[6](n)
33 33 33 LVDS_TX_P[7] LVDS_TX_P[7] LVDS_TX_P[7]
34 34 34 LVDS_TX_P[7](n) LVDS_TX_P[7](n) LVDS_TX_P[7](n)
31 31 31 LVDS_TX_P[8] LVDS_TX_P[8] LVDS_TX_P[8]
32 32 32 LVDS_TX_P[8](n) LVDS_TX_P[8](n) LVDS_TX_P[8](n)
27 27 27 LVDS_TX_P[9] LVDS_TX_P[9] LVDS_TX_P[9]
28 28 28 LVDS_TX_P[9](n) LVDS_TX_P[9](n) LVDS_TX_P[9](n)
25 25 25 LVDS_TX_P[10] LVDS_TX_P[10] LVDS_TX_P[10]
26 26 26 LVDS_TX_P[10](n) W5 LVDS_TX_P[10](n) W5 LVDS_TX_P[10](n) W5
23 23 23 LVDS_TX_P[11] LVDS_TX_P[11] LVDS_TX_P[11]
24 24 24 LVDS_TX_P[11](n) W4 LVDS_TX_P[11](n) W4 LVDS_TX_P[11](n) W4
21 21 21
22 22 22
19 19 19
20 20 20
17 17 17
18 18 18
15 15 15
16 16 16
MAX 10 Pin MAX 10 Pin MAX 10 Pin J4 Pin J4 Pin J4 Pin
AA14 AA14 AA14 3 3 3
AB15 AB15 AB15 4 4 4
AA15 AA15 AA15 5 5 5
Y16 Y16 Y16 6 6 6
V17 V17 V17 39 39 39
W17 W17 W17 40 40 40
V16 V16 V16 37 37 37
U15 U15 U15 38 38 38
W15 W15 W15 35 35 35
V14 V14 V14 36 36 36
W14 W14 W14 31 31 31
V13 V13 V13 32 32 32
Y14 Y14 Y14 29 29 29
Y13 Y13 Y13 30 30 30
AA10 AA10 AA10 27 27 27
Y10 Y10 Y10 28 28 28
V10 V10 V10 23 23 23
V9 V9 V9 24 24 24
AA7 AA7 AA7 21 21 21
AA6 AA6 AA6 22 22 22
W8 W8 W8 19 19 19
W7 W7 W7 20 20 20
U7 U7 U7 15 15 15
U6 U6 U6 16 16 16
W6 W6 W6 13 13 13
14 14 14
W3 W3 W3 11 11 11
12 12 12
21 21 21