Timer 3 Load Count Register (Tmrlcr3); Timer 4 Load Count Register (Tmrlcr4); Timer 1 & 2 Current Count Register (Tmrccr12); Timer 3 Current Count Register (Tmrccr3) - GE VMIVME-7805 Hardware Reference Manual

44 VMIVME-7805/VME-7805RC Hardware Reference Manual
disabled. The value stored in this register is also automatically reloaded on
terminal count (or timeout) of the timer.

3.4.5 Timer 3 Load Count Register (TMRLCR3)

Timer 3 is 32-bits wide and obtains its load count from the Timer 3 Load Count
Register (TMRLCR3), located at offset 0x14 from the address in BAR2. The
mapping of bits in this register are as follows:
Field
Timer 3 Load Count
When this field is written, Timer 3 is loaded with the written value on the next
rising edge of the timer clock, regardless of whether the timer is enabled or
disabled. The value stored in this register is also automatically reloaded on
terminal count (or timeout) of the timer.

3.4.6 Timer 4 Load Count Register (TMRLCR4)

Timer 4 is 32-bits wide and obtains its load count from the Timer 4 Load Count
Register (TMRLCR4), located at offset 0x18 from the address in BAR2. The
mapping of bits in this register are as follows:
Field
Timer 4 Load Count
When this field is written, Timer 4 is loaded with the written value on the next
rising edge of the timer clock, regardless of whether the timer is enabled or
disabled. The value stored in this register is also automatically reloaded on
terminal count (or timeout) of the timer.
3.4.7 Timer 1 & 2 Current Count Register (TMRCCR12)
The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count
Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The
mapping of bits in this register are as follows:
Field
Timer 2 Count
Timer 1 Count
When either field is read, the current count value is latched and returned. There
are two modes that determine how the count is latched depending on the setting
of the "Read Latch Select" bit in the WDT Control Status Register (CSR2). See the
CSR2 register description for more information on these two modes.

3.4.8 Timer 3 Current Count Register (TMRCCR3)

The current count of Timer 3 may be read via the Timer 3 Current Count Register
(TMRCCR3), located at offset 0x24 from the address in BAR2. The mapping of bits
in this register are as follows:
Field
Timer 3 Count
When this field is read, the current count value is latched and returned. There are
two modes that determine how the count is latched depending on the setting of
Bits Read or Write
TMRLCR3[31..0] Read/Write
Bits Read or Write
TMRLCR4[31..0] Read/Write
Bits Read or Write
TMRCCR12[31..16] Read Only
TMRCCR12[15..0] Read Only
Bits Read or Write
TMRCCR3[31..0] Read Only