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2-1-3.
Parallel Interface
DATA 1
DATA 2
DARA 3
DATA 4
DATA 5
DARA 6
DATA 7
DATA 8
STROBE
BUSY
ACK
ERROR
SELECTED
PAPER OUT
The host computer sends eight bits of data for DATA 1 - 8 to the CN3 connector when the BUSY signal is LOW (printer
is ready).
The data passes through the interface board and gate array, then moves into the CPU.
Printer signals from the CPU (ACK, ERROR, SELECTED, PAPER OUT, etc.) pass through the gate array and are output
the appropriate connector pins.
CN3
A4
B4
A5
B5
A6
B6
A7
B7
A13
A12
B12
A10
A11
B11
LS05
IC1
Parallel Interface Board
Fig. 2-4 Parallel Interface
CN1
CN9
IC10
A4
CD0
B4
CD1
A5
CD2
B5
CD3
A6
CD4
B6
CD5
A7
CD6
B7
CD7
A13
CSTB
A12
BUSY
B12
ACK
A10
ERROR
A11
SELECT
B11
POUT
Gate Array
Main Logic Board
– 20 –
IC5
CPU
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