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Hardware Structure of the CDS _ _ _ _ _ _ _ _ _ _ _
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The various control, flags, etc. are distributed to
the 110 and memory expansion locations on the
hackplane. Module select lines, BANK SELECT for
memory and SELECT for 110, are not wired on the
backplane PC board, but are available for wire-wrap
connections as determined by user system con-
figurations.
Module Description
and Signal Mnemonics
- Each standard module will be described using a
~implified
logic or Block diagram. Detailed logic
diagrams may be found in Appendix D.
Signal naming conventions are as follows:
The signal name is followed by a hyphen and
either the letter N or P. The suffix N means the signal
is asserted (true I when that wire is at grOlmd. The
suffix P means the signal is asserted (true I when that
wire is at the highest logic level (+5 VI. Thus the
signal name gives the meaning assigned to that
conductor, and the suffix defines the electrical value
of the asserted (truel state.
A btmdle of parallel signals is indicated by a (i:jl
notation in the signal name denoting a nmning index
over the range i to j and by the number of parallel
signals (in parentheses I labeling the signal path.
Inputs which are pulled high or Iowan the module are
indicated with resistor symbols to VDD or to GND.
If such an input is not used (not connectedl, it
assume!"! the highllow level defined by its "pull
upl down" resistor. Output signals which are derived
from CMOS transmission gates are labeled with a
"(1'1" in the diagrams. Such outputs may be bussed
("wire-OR 'ed "I together - assuming only one tran-
~mission
gate is enabled at a time. An output derived
from a transmission gate may also be pulled high or
low with a resistor on the board.
Card Nest and Backplane
The backplane of the Card Nest is a double-sided
PC board mounted on the back of the CDS.
It in-
terconnects the pins of the first 25 of the 33 available
connector positions. Some of these positions are
occupied with supplied modules, as indicated in
Table III. The card positions, viewed from the back,
are numbered from left to right.
TABLE III - MODULE POSITION
ASSIGNMENTS IN NEST
Connector
Position
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
-
32
Module
Memory Bus
Memory Bus
Memory Bus
Memory Bus
Memory Bus
Memory Bus
Memory Bus
4-Kilobyte RAM
ROM/RAM
Address Latch and
Memory Bank Select
Blank
CPU
I/O Decode
Terminal Interface
I/O Bus
I/O Bus
I/O Bus
I/O Bus
I/O Bus
I/O Bus
I/O Bus
I/O Bus
I/O Bus
(Floppy Disk Interface)
Control
Power Supply
Part Number
CDP18S205
CDP18S401
CDP18S206
CDP18S102
CDP18S509
CDP18S507
CDP18S813
CDP18S103
The backplane WIrIng schedule in Appendix A
indicates the following types of connection: lillused
pins, pins interconnected by printed wiring, pins
interconnected by a wire-wrap, and pins not con-
nected on the backplane but which have meaning
defined by the plugged-in module. A dash indicates
an lillused pin, In all cases, identically named signals
are interconnected. The backplane is laid out so that
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