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32 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Operator Manual for the RCA CDS II CDP18S005
Depression of the LOAD
switch causes
both
W AIT-N and CLEAR-N to be asserted, defining the
LOAD mode, in which data may be loaded into
memory using DMA-IN.
Depression of the RESET switch results in
·
CLEAR-N asserted and W AIT-N false which puts
the·CPU into the RESET mode.
Depression of RUN P
or
RUN U results in both
. WAIT-N and CLEAR-
fa lse, putting
the
CPU
into
'\'
lh RUN mod. In the a
of
RUN
,lhe signal
'
R
-p
j
.
a
s
rt
a,
and go
via
lh ba kplanetothe
-Addr
,
Latch and Bank
el
t
Modul
where
memory address 8XXX is forced and starts the
Utility program.
When the SINGLE STEP
switch
is set, depression
of RUN U
or
RUN P results in the RUN mode for
one machine
cycle,
stopping between TPA and TPB.
Successive depressions of a R UN
switch
will cause
execution of the program, one machine cycle at a
time.
Inputs for external manipulation of
the control
modes are provided. EXT WAIT-P and EXT
CLEAR-P are available on the backplane connector.
Each is provided with a pull-down resistor and
through one OR gate directly
controls
WAIT and
CLEAR, e.g., a high
on
EXT WAIT-P
causes
a low
on WAIT-N.
An Idle detector circuit
counts
SI states to
determine when
3
or more
sequential
SI
states
occur.
When Idle is detected, the RUN-N line will
go
high
extinguishing the R UN light on the panel. The
operator can terminate the Idle state by depressing
RUNP. Then a single DMAOUT request will be
made,
and
following the S2 state, processing will re-
Sllme with the instruction following the Idle. The
RUN light will be turned on when the program starts
running again.
The Data Bus and Address Bus as well as WAIT-
N. CLEAR-N, SCO-N, SCI-N and Q-P are
sent
to
the display panel via
Jl.
Each of these lines is buf-
fered.
An interface
connector
J2 is provided for at-
tachment of the optional Microterminal. Control
switches from the Microterminal are
electronically
paralleled with those from the Control Panel.
Address Latch and
Bank Select Module
CDP18S206
The Address Latch and Bank Select Module
stores
and decodes the high-order byte of the memory
address for use by
all
memory modules. Fig. 9 is a
block diagram
of
this module. A(7:01 from the CPU
module is latched into an eight-bit register by TPA .
The outputs of this register. AIl5:81, are provided on
the backphllle
connector
and to a
one-of-lo
decoder.
The decoder
outputs
are 16 Bank Select lines,
BSfF:OI. which go to the backplane connector.
A[7:0
J-P
TPA
RNU
-
P
-
- - - ,
MBDS-N
-----<_~
92CS-29613
Fig.
9 -
Address Latch and Bank Select Module
CDP18S206 block diagram.
These
signals
break up the 65-kilobyte memory
field into
sixteen
blocks of 4-kilobytes
each.
The
supplied
4-kilobyte RAM module is wired to the
lowest-order bank-select signal. BSO-P, so that it is
located
starting
at
address
O()OO. The ROM
/
RAM
module is wired to BS7-P locating its starting address
at
~WOO.
RNU, a
signal
derived from the RUN U
control
panel switch, causes the decoder to
see
A15 as
true. Thus. after a RESET. depression
of
RUN U
will
cause the starting address to be 8000, which is the
location of Utility software.
Memory Bank De-Select fMBDS-NI is an input
provided
so
that all Bank Select lines can be
inhibited. A pull-up resistor is provided so that if no
conneetion
is made to this pin. the line is false. and
the Bank Select decoder operates normally. This
input may be used to logically disconnect the memory
system
when another is to be
substituted.
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