RCA 1800 Operator's Manual page 40

Hardware Structure of the CDS
39
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TABLE IV - CDS SYSTEM SIGNALS
Signal Name
Description
Source Destination
A[7:0)-P
Low-order memory address CPU
Memory, Address Latch
bits
Control
A[15:8) -P
High-order memory address
Address Latch Memory
bits
ANY I/O-P OR'ed output from N-lines
CPU Control
BS[F:O) -P
Memory bank select
Address Latch Memory
CDO[7:0) -N Data bits from disk
Disk interface Disk Drive
interface module
module
CLEAR-N CPU clear signal Control
CPU, Disk
"
CLEAR SW From Microterminal
Microterminal Control
CPU[7:0)-N
Command bits from disk Disk interface Disk Drive
interface module module
CPU PWR
+V DD supply to CPU Power Supply/ CPU
User
DB[7:0)-P
Bidirectional data bus CPU Memory, I/O, Control,
Terminal
DI[7:0) -N
Data bits from disk drive Disk Drive
Disk interface module
to disk interface module
DMAI-N
DMA IN request User CPU
DMAO-N DMA OUT request User, Control CPU
EF[4:1) -N Flag inputs to CPU I/O, Terminal, CPU
Control
EX CLK External clock input User CPU
EX WAIT
External wait to CPU CPU User
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INT-N Interrupt request
User CPU
LOAD SW From panel switch Panel Control
MBDS-N Memory bank deselect User Address Latch
MRD-N Memory read signal
CPU
Memory, I/O, Control,
I/O Decode, Terminal
MWR-N Memory write signal CPU
Memory
N[2:0) -P
N-lines from CPU CPU I/O Decode, Control
N=[7:1) -P Decoded N-lines I/O Decode I/O, Terminal, Disk,
Control
Q-P
Single bit output from CPU CPU Terminal, I/O
RESET-OP
Reset signal from control Control Memory, I/O
RESET SW
From panel switch Panel Control
RNU-P Signal to run utility Control Address Latch, I/O Decode
program
RUN-N Signal indicating con-
Control Display
tinuous SO,S1 cycles
RUN P SW From panel or Micro- Panel/Micro- Control
1
terminal terminal
RUN U SW From panel switch Panel
Control
SCO[1:0)-P State code lines CPU
I/O, Terminal, Control
SEL[7:0) -P
Two-level enabling signals I/O Decode I/O, Terminal, Disk
SINGLE-STEP Single-step control input
Panel Control
SW
TPA-P
Early pulse in CPU cycle CPU Memory, Address Latch,
I/O Decode, I/O, Control
Terminal
TPB-P Late pulse in CPU cycle CPU
Memory, I/O Decode, I/O
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Control, Terminal, Disk
UA15-N OR'ed output of A15 Address Latch
User
and RNU
WAIT-N CPU wait signal Control CPU