Appendices; Cds 18S005 Backplane Wiring Schedule - RCA 1800 Operator's Manual

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Appendix A -
CDS II CDP18S005 Backplane Wiring Schedule
Pin Memory
Address CPU I/O
I/O
Control
Pin
No.
Latch and
Decode
No.
Bank
[3)
Location (1-9)
Select (10) (12)
(13)
(14-24) (25)
A
BSE-P TPA-P
TPA-P
TPA-P TPA-P
A
B SPARE
TPB-P
TPB-P TPB-P
TPB-P
B
C DBO-P
BS9-P DBO-P
DBO-P
DBO-P DBO-P
C
D DB1-P
RNU-P
DB1-P DB1-P
DB1-P DB1-P
D
E DB2-P BS8-P
DB2-P DB2-P DB2-P
DB2-P
E
F DB3-P BS7-P
DB3-P DB3-P
DB3-P
DB3-P F
H DB4-P
BS6-P DB4-P DB4-P
DB4-P DB4-P
H
J DB5-P BS5-P
DB5-P DB5-P DB5-P
DB5-P
J
K DB6-P BS4-P
DB6-P DB6-P
DB6-P DB6-P
K
l DB7-P
BS3-P DB7-P DB7-P DB7-P
DB7-P l
M AO-P
BSD-P AO-P SElO-P
AO-P M
N A1-P
BSF-P A1-P
SEL1-P A1-P
N
P
A2-P A15-P A2-P
SEl2-P
N=4-P}
A2-P
P
R A3-P A14-P A3-P
SEl3-P N=5-P [4]
A3-P R
S A4-P _A12-P
A4-P SEl4-P N=6-P
A4-P S
T A5-P
A5-P SEl5-P
A5-P T
U A6-P A6':""P
SEl6-P A6-P U
V A7-P A7-P
SEl7-P A7-P V
W MWR-N BSO-P MWR-N N=7-P N=7-P [5]
W
x
BSN-P [1]
MBDS-N CPU PWR N=6-P EF4-N RUN-N X
Y
VDD VDD VDD VDD
V DD
VDD
Y
Z GND GND GND
GND GND GND Z
1 TPA-P TPA-P
DMAI-N N=1-P DMAI-N
1
2 TPB-P
UA15-N DMAO-N N=2-P DMAO-N
DMAO-N 2
3 SPARE BSC-P ANY I/O-P N=3-P
ANY I/O-P 3
4 BSB-P INT-N N=4-P INT-N
RNU-P 4
5 MRD-N BSA-P MRD-N
MRD-N MRD-N MRD-N 5
6
A12-P
A12-P Q-P N=5-P Q-P Q-P
6
7
A11-P
A11-P SCO-P SCO-P
SCO-P 7
8 A10-P A10-P SC1-P SC1-P
SC1-P 8
9 A9-P A9-P ClEAR-N TLlO-N
ClEAR-N 9
10 A8-P A8-P WAIT-N
WAIT-N 10
11 -5V AO-P -5 V
EX ClR-P 11
12 EX WAIT A1-P EX ClK
EX WAIT-P 12
13 ClK OUT A2-P ClK OUT RESET-OP
RESET-OP RESET-OP 13
14 A3-P NO-P NO-P NO-P 14
15 A4-P N1-P N1-P N1-P 15
16
RESET-OP A5-P N2-P N2-P
N2-P 16
17
A6-P EF1-N EF1-N
17
18 A7-P EF2-N EF2-N 18
19
VDD
[2]
BS2-P EF3-N EF3-N EF3-N 19
20 +12 V BS1-P EF4-N +12 V +12 V +12 V 20
21
VDD VDD VDD VDD VDD VDD
21
22 GND GND GND GND GND GND 22