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28 _ _ _ _ _ _ _ _ _ _
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_ _ _ Operator Manual for the RCA CDS II CDP18S005
10
ADDRESS LATCH
AND
BANK SELECT
CDPI8S206
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----,
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MEMORY
I
EXPANSION
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4- KI
LOB'fT
RAM
CDPI8S205
ROMI RAM
CDPI8S401
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ST.l,TE
CODE
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FLAGS.
D MA .TPA. TPB
.
IN
TERM INAL
I
NTEP~ACE
C DP 185507
14
OPTIONAL 24
DISK
INTERFACE
CDPI85813
I
1
I
IIO
I
EXPANSION
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I
I
I
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Fig. 6 - Block diagram of COSMAC Development
System /I CDP18S005.
92CL-
2
962
5
The control and Display Panel has a PC board on
which are mounted the switches, displays, and
associated electronics. Via a cable, it communicates
with the control module which is inserted into the
card nest. The Control module contains circuits to de-
bounce the switches, interface then to the CPU, and
perfonn some logic control and timing. The Control
module communicates with the CPU module via
wires printed on the backplane.
The CPU module consists of the CDP1802 with a
crystal for the on-chip oscillator and electrical buffers
for the Data and Address Buses. The CPU module is
central to the system, communicating with the
110
and Memory systems to the right and left respectively
in the diagram.
On the memory side, the Address Latch and Bank
Select module. as its name implies. latches the high-
order Memory Address Byte and decodes it into 16
unique Bank Select lines, for use by the entire
memory system. On the
110
side,
the
110
Decode
module accepts the N lines from the CPU, and
decodes them into 7 unique lines. N = 1 through N
= 7 for use by all
110
controllers. In addition. it
latches the
Data Bus on a (61116 instruction, and
provides eight Select lines for use hy all
1/
0 con-
trollers as two-level
110
addressing.
Two
memory
modules
are
provided.
the
ROM/
RAM
and
the
4-kilohyte
RAM.
The
ROM
/
RAM module holds the system 's Utility
program ROM (uT201 plus a small (32-bytel RAM
for use by that Utility
.
The 4-kilobyte RAM module
provides 4 kilobytes
of static RAM
storage.
Additional 4-kilobyte RAM modifications may be
added pre-wired expansion slots.
A Terminal Interface Module is provided, which
may be used to communicate with tenninals having
either the EIA or 20-mA current-loop interface.
All memory and
110
controller modules attach to
•
the common DATA BUS, which is hi-directional.
~
Therefore, these modules must provide a means for
disconnecting from the bus. when not using the bus.
such as tri-state buffers or transmission gates.
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