Introductionl; Cpu Board; Power Supply; Microprocessor - PESA RCP-48X Manual

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RCP–48X
4.1 Introduction
The RCP–48X panel consists of two printed circuit boards. The CPU
board contains a microprocessor that controls the panel's operation and
communicates with the control system. The Switchcard contains pushbut-
tons and indicators used by the operator to control the routing switcher.
The following is a detailed description of each of these boards.

4.2 CPU Board

The CPU board contains all circuitry necessary to communicate with the
system controller and to interface to a front panel switchcard. The circuitry
on the CPU board may be divided into the following sections: Power
Supply, Microprocessor, Clock, Reset, Memory, LED Driver Support, RS-
485 Communications, I/O, and Miscellaneous. The following paragraphs
explain each section in detail.

Power Supply

The power supply circuit on the CPU board consists of a 7805 +5V regula-
tor and filter capacitors. Unregulated DC voltage (7.5 to 9 Vdc) is supplied
by an external power supply via J3. The voltage regulator U7 reduces the
voltage to 5.0 Vdc. C10 and C12 provide filtering for the input and output
of the regulator, respectively. Bypass capacitors (.1 uF) are scattered
about the board to provide power supply bypassing for individual chips.
The regulated voltage is available to external board on both J1 and J2,
pins 31 and 32. The unregulated voltage is available to external board on
both J1 and J2, pins 29 and 30.

Microprocessor

The heart of the CPU board is the Motorola 68HC11 microprocessor (U1).
This IC contains the microprocessor and peripheral circuitry used to oper-
ate the panel. In addition, the 68HC11 contains a PROM with the software
used to operate the panel. The 68HC11 is operated in the expanded
multiplexed mode. In this mode port B (U1 pins 35-42) provides the upper
address byte (A8-A15). Port C (U1 pins 9-16) provides both the lower
address byte (A0-A7) and the data byte (D0-D7). U2 is used to latch the
lower address byte. Figure 4–1 shows an idealized timing diagram for
external bus cycles.
Functional
Section 4
4
FUNCTIONAL
page 4.1
DESCRIPTION

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