Mfr_Chan_Config_Ltc3882-1 - Linear Technology Analog Devices LTC3882-1 Datasheet

LTC3882-1
PMBus COMMAND DETAILS

MFR_CHAN_CONFIG_LTC3882-1

The MFR_CHAN_CONFIG_LTC3882-1 command provides per-channel configuration common to multiple LTC PMBus
products.
Bit Definitions:
BIT MEANING
7:5 (Reserved).
4 RUN pin control:
0: When the channel is commanded off, the associated RUN pin is pulsed low for TOFF_DELAY + TOFF_FALL + 136ms
(or MFR_RESTART_DELAY, if longer) regardless of the state of bit 3.
1: RUN pin is not pulsed low if channel is commanded off.
3 Short cycle control:
0: No special control. Device attempts to follow on/off commands exactly as issued.
1: Output is immediately disabled if commanded back on while waiting for TOFF_DELAY or TOFF_FALL to expire. A minimum off time
of 120ms is then enforced before the channel is turned back on. Additional delay will apply if bit 4 is clear.
2 SHARE_CLK output control:
0: No special control.
1: Output disabled if SHARE_CLK is held low.
1 (Reserved, must write as 0).
0 MFR_RETRY_DELAY control:
0: Output decay to 12.5% of programmed value required for retry after ANY action that turns off the rail.
1: Output decay not required for retry.
This command has one data byte.
76
(PWM Configuration)
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Rev A