Packet Reception; Architecture - Realtek RTL8100 Programming Manual

2 Packet Reception

2.1 Architecture

The receive path of the RTL8100 is designed as a ring buffer. This ring buffer is a physical continuous memory structure. Data
coming from the line is first stored in a Receive FIFO in the chip, and then moved to the receive buffer when the early receive
threshold is met. The register CBA keeps the current address of the data moved to the buffer. CAPR is then a read pointer which
keeps the address of data that the driver had read. The receiving packet status is stored in front of the packet (packet header).
Initialization Block
CR
TCR
RCR
CAPR
RBSTART [31 : 0 ]
TSAD0
TSAD1
TSAD2
TSAD3
TSD0
TSD1
TSD2
TSD3
2001/12/10
[7 : 0 ]
[31 : 0 ]
[31 : 0 ]
[15 : 0 ]
[31 : 0 ]
[31 : 0 ]
[31 : 0 ]
[31 : 0 ]
[31 : 0 ]
[31 : 0 ]
[31 : 0 ]
[31 : 0 ]
CAPR
n n-1
RBSTART
1
2
3
. . . .
Packet Packet
1 2
Rcv. Buffers
m
TSAD0
TSAD1
. . . .
Packet Packet
1 2
Xmit Buffers
6
n-2
. . . .
5
4
Packet
n
m-1 m-2
. . . .
TSAD1
TASD0
TSAD2 TSAD3
Packet
m
RTL8100
Rev.1.0