The Transmission Process - Realtek RTL8100 Programming Manual

1.3 The Transmission Process

The following process describes the transmission of a packet.
1. The packet is copied to a physically continuous buffer in memory.
2. The appropriate descriptor is written as follows.
a. Enter the physical address of this buffer into the Start Address register.
b. Enter the size of this packet, and the early transmit threshold into the Transmit Status register. Also,
clear the OWN bit in TSD. This starts the PCI operation.
3. As the data moved into the FIFO meets the early transmit threshold, the chip starts to move data from the FIFO to the
line.
4. When the whole packet is moved to the FIFO, the OWN bit is set to 1.
5. When the whole packet is moved to the line, the TOK (in TSD) is set to 1.
6. If TOK (IMR) is set to 1 and TOK (ISR) is set, then an interrupt is triggered.
7. When an interrupt service routine is called, the driver should clear TOK (ISR) State Diagram: (TOK,OWN)
2001/12/10
TSAD0
TSD0
TSAD1
TSD1
TSAD2
TSD2
TSAD3
TSD3
Initial
0,1
Driver clears
Own bit
1,1 Finish send
packet
0
Descriptor
Start PCI operation
Own: 1->0
0,0
Finish PCI operation
Own: 0->1
0,1
3
Tx FIFO
Transmit Underrun
RTL8100
Rev.1.0