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While the ASYNC HDLC controller is transmitting data from the buffers, it automatically per-
forms the transparency encoding specified by the protocol. This encoding is described in de-
tail in section 2.3 on page 5.
If the user wishes to re-arrange the transmit queue before the Communications Processor
(CP) has completed transmission of all buffers, the user should issue the STOP TRANSMIT
command. This can be useful for transmitting expidited data prior to previously linked buffers
or for error situations. The ASYNC HDLC controller, when receiving the STOP TRANSMIT
command, will stop transmitting and will send the ASYNC HDLC ABORT sequence (0x7d,
0x7e). It will then transmit IDLE characters until the RESTART TRANSMIT command is giv-
en, at which point it will resume transmission with the next Tx BD.
2.2 ASYNC HDLC Channel Frame Reception Processing
The ASYNC HDLC receiver is also designed to work with a minimum amount of intervention
from the CPU32+ core. The ASYNC HDLC receiver can perform the decoding of the trans-
parency characters, check the CRC of the frame, and detect errors on the line and in the
controller.
When the core enables one of the receivers, the receiver waits for data to be present on the
line. When the receiver detects a data byte of the incoming frame, the ASYNC HDLC con-
troller fetches the next buffer descriptor (BD) and, if the empty (E) bit is set, starts transfer-
ring the incoming frame into the BD's associated data buffer. When the data buffer is full,
the ASYNC HDLC controller clears the empty bit in the BD. If the incoming frame exceeds
the length of the data buffer (as defined in the MRBLR parameter), the ASYNC HDLC con-
troller fetches the next BD in the table and, if empty, continues to transfer the rest of the
frame into this BD's associated data buffer.
During this process, the receiver will automatically perform the transparency character de-
coding required of the ASYNC HDLC protocol. This procedure is described in detail in sec-
tion section 2.4 on page 6.
When the frame ends, the controller checks the incoming CRC field and writes it to the data
buffer. It then writes the length of the entire frame to the data length field of the last BD. The
ASYNC HDLC controller sets the last (L) bit, writes the frame status bits into the BD, and
clears the empty bit if the continuous mode (CM) bit is clear. It then sets the RXF bit in the
event register indicating that a frame has been received and is in memory. The ASYNC
HDLC controller then waits for the start of the next frame which may, or may not, have an
opening FLAG.
2.3 Transmitter Transparency Encoding
The ASYNC-HDLC Controller mapps characters according to RFC 1549. It will examine the
outgoing data bytes and perform the transparency algorithm on a given byte if it matches
one of the following criteria:
• The byte is a FLAG (0x7E)
• The byte is a Control-Escape Character (0x7D)
MOTOROLA
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Asynchronous HDLC
5
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