Tait TM8000 Series Service Manual page 68

Power Supplies
Performance
Requirements
Effect of Tuning Range
Switch-mode Power
Supply
Synthesizer Circuitry
Reference Frequency
68 Circuit Descriptions
Several power supplies are used by the frequency synthesizer owing to a
combination of performance requirements and the availability of suitable
components. The PLL IC includes analogue and digital circuitry and
uses separate power supplies for each section. The digital section is run
on 3 V, while the analogue section is run on approximately 5 V. The
VCOs and buffer amplifiers run off a supply of about 5.3 V. The active
loop filter requires a supply of 14 to 15 V, and a reference voltage of
approximately 2.5 V.
Low noise and good regulation of the power supply are essential to the
performance of the synthesizer. A 6 V regulator IC provides good line
regulation of the 9 V supply and good load regulation. Good regulation
of the power-supply line and load is essential for meeting the transient
ACP requirements. The regulator output voltage is electrically noisy,
however, and filtering is essential. Filtering of the power supply is
achieved with two capacitance multipliers (Q508 and C585 for the VCO
supply, and Q512 and C579 for the PLL and loop-filter supply). The
VCO (or VCOs) use a separate capacitance multiplier because these
multipliers have poor load regulation and the VCOs impart sufficient
load transients to warrant a separate supply.
For reasons of noise performance, the VCOs are designed to be tuned
within a range of 2 to 12 V. Active tuning circuitry is required. An active
loop filter incorporating an IC operational amplifier achieves this range
with a suitable power supply voltage. Normal synthesizer switching
behaviour involves overshoot, which dictates that the tuning voltage
range must extend above and below the range of 2 to 12 V. The 14 V
limit is a result of limits on the working supply voltage of the IC
operational amplifier.
The power supply
VCL SUPPLY
SMPS (switch-mode power supply), which is in turn powered by 9 V.
The SMPS consists of an oscillator (switching circuit) and a detector.
The output voltage is monitored by a feedback circuit that controls the
DC bias of the switching circuit to maintain a constant output voltage.
The essential function of the PLL frequency synthesizer is to multiply a
25 kHz reference frequency to give any desired frequency that is an
integer multiple of 25 kHz. There are some constraints imposed by the
capabilities of the synthesizer hardware, especially the tuning range of the
VCOs.
The 25 kHz (approximate) reference is obtained by dividing the 13 MHz
(approximate) output of the FCL. Any error in the FCL output
frequency will be multiplied by the synthesizer. Therefore, if the
synthesizer is locked but not the FCL, then the synthesizer output
frequency will be wrong. The FCL frequency division is performed by
a digital counter inside the PLL IC. The divider setting is constant.
for the active loop filter is provided by a
TM8100 Mobile Radio Service Manual
May 2004 © Tait Electronics Limited