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Dynamic Engineering PCIeBiSerialDb37-LM9 User Manual

Arc210 if/parallel port pcie 4 lane module transmit and receive interface protocols rs485/422
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DYNAMIC ENGINEERING
150 DuBois St. Suite C, Santa Cruz, CA 95060
831-457-8891
Fax 831-457-4793
http://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
PCIeBiSerialDb37-LM9
ARC210 IF / Parallel Port
PCIe 4 lane Module
Transmit and Receive Interface Protocols
RS485/422
Revision A1
Corresponding Hardware: Revision 1
10-2009-0401
FLASH 0101
Embedded Solutions
Page 1

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  • Page 1 DYNAMIC ENGINEERING 150 DuBois St. Suite C, Santa Cruz, CA 95060 831-457-8891 Fax 831-457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual PCIeBiSerialDb37-LM9 ARC210 IF / Parallel Port PCIe 4 lane Module Transmit and Receive Interface Protocols RS485/422 Revision A1 Corresponding Hardware: Revision 1...
  • Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the product described in this document at any time and without notice.

  • Page 3: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION ADDRESS MAP PROGRAMMING Base Register Definitions LM9_BASE_BASE LM9_BASE_ID LM9_BASE_STATUS LM9_CHAN_CNTRL LM9_CHAN_STATUS LM9_CHAN_TX_FIFO_COUNT LM9_CHAN_RD_DMA_PNTR LM9_CHAN_RX_FIFO_COUNT LM9_CHAN_FIFO LM9_CHAN_TX_AMT_LVL LM9_CHAN_RX_AFL_LVL LM9_CHAN_TX LM9_CHAN_TX_PACKET_LEN_FIFO LM9_CHAN_TX_PACKET_LEN_REG LM9_CHAN_RX LM9_CHAN_RX_PACKET_LEN_FIFO LM9_CHAN_RX_TIMEOUT_LEN LM9_CHAN_RX_BYTECOUNT_LEN LOOP-BACK PCIE MODULE FRONT PANEL IO INTERFACE PIN ASSIGNMENT APPLICATIONS GUIDE Interfacing Construction and Reliability Thermal Considerations...
  • Page 4 Out of Warranty Repairs SPECIFICATIONS ORDER INFORMATION Embedded Solutions Page 4...
  • Page 5 List of Figures FIGURE 1 PCIEBISERIALDB37LM9 BLOCK DIAGRAM FIGURE 2 PCIEBISERIALDB37LM9 TIMING DIAGRAM FIGURE 3 PCIEBISERIALDB37LM9 INTERNAL ADDRESS MAP BASE FUNCTIONS FIGURE 4 PCIEBISERIALDB37LM9 CHANNEL ADDRESS MAP FIGURE 5 PCIEBISERIALDB37LM9 CONTROL BASE REGISTER BIT MAP FIGURE 6 PCIEBISERIALDB37LM9 ID AND SWITCH BIT MAP FIGURE 7 PCIEBISERIALDB37LM9 STATUS PORT BIT MAP FIGURE 8 PCIEBISERIALDB37LM9 CHANNEL CONTROL REGISTER FIGURE 9 PCIEBISERIALDB37LM9 CHANNEL STATUS PORT...

  • Page 6: Product Description

    Engineering is happy to assist in your decision regarding architecture and other trade- offs with the form factor decision. Dynamic Engineering has carriers for IP and PMC modules for most systems, and is adding more as new solutions are requested by our clients.

  • Page 7: Figure 1 Pciebiserialdb37Lm9 Block Diagram

    “LM9” is set to use the RS485/RS422 standard, and supports one Transmit and one Receive channel plus a parallel port. The transmitter and receiver are designed to interface with the ARC-210 radio. Figure 1 PCIEBISERIALDB37LM9 Block Diagram The ARC-210 will supply the “SendTiming” and “ReceiveTiming” clock reference signals.
  • Page 8 The number of bytes to send is programmable. The number can be stored into a secondary FIFO to allow multiple packets to be transmitted from a single larger DMA transfer. The number of bytes can also be stored into a register to cover cases where the size of each packet is consistent.
  • Page 9 Custom cables can be manufactured to your requirements. The loop-back IO definitions are toward the end of this manual. Please contact Dynamic Engineering with your specifications. In the “LM9” design the Termination and Direction controls are set in the VHDL for the ARC-210 IO and programmable with software for the GPIO.
  • Page 10 From a software perspective the design can be treated as “Flat” or as a hierarchy. The Dynamic Engineering Windows® driver uses the hierarchical approach to allow for more consistent software with common bit maps and offsets. This implentation has only one channel.

  • Page 11: Figure 2 Pciebiserialdb37Lm9 Timing Diagram

    If you see what you need in one version and prefer it on another please contact Dynamic Engineering about porting the design. In most cases it will require a recompile of the VHDL and not much more. We do a lot of “just like but different “...

  • Page 12: Address Map

    Address Map Function Offset // PCIeBiSerialDb37LM9 BASE definitions #define LM9_BASE_BASE 0x0000 // 0 LM9Base Base control register #define LM9_BASE_PLL_WRITE 0x0000 // 0 LM9Base Base control register #define LM9_BASE_PLL_READ 0x0000 // 0 LM9Base base control register #define LM9_BASE_USER_SWITCH 0x0004 // 1 LM9Base User DIP switch read #define LM9_BASE_XILINX_REV 0x0004 // 1 LM9Base Xilinx revision read port #define LM9_BASE_XILINX_DES...

  • Page 13: Figure 4 Pciebiserialdb37Lm9 Channel Address Map

    Function Offset from Channel Base Address // PCIeBiSerialDb37LM9 Channel definitions #define LM9_CHAN_CNTRL 0x00000000 //0 LM9Chan General control register #define LM9_CHAN_STATUS 0x00000004 //1 LM9Chan Interrupt status port #define LM9_CHAN_INT_CLEAR 0x00000004 //1 LM9Chan Interrupt clear port #define LM9_CHAN_WR_DMA_PNTR 0x00000008 //2 LM9Chan Write DMA dpr physical PCI address register #define LM9_CHAN_TX_FIFO_COUNT 0x00000008 //2 LM9Chan TX FIFO count read port...

  • Page 14: Programming

    The Driver comes with reference software showing how to use the card and reference frequency files to allow the user to duplicate the test set-up used in manufacturing at Dynamic Engineering. Using simple, known to work routines is a good way to get acquainted with new hardware.
  • Page 15 DMA should be set-up before starting the channel port function. For transmission this will result in the FIFO being full or close to it when the transfer is started or at least the Packet loaded if shorter than the FIFO size. For reception it means that the FIFO is under HW control and the delay from starting reception to starting DMA won’t cause an overflow condition.

  • Page 16: Base Register Definitions

    Base Register Definitions LM9_BASE_BASE [$00 Base Control Register Port read/write] DATA BIT DESCRIPTION 31-21 spare bit 19 read-back of pll_dat register bit pll_dat [write to PLL, read-back from PLL] pll_s2 pll_sclk pll_en 15-0 spare Figure 5 PcieBiSerialDb37Lm9 Control Base Register Bit Map This is the base control register for the LM9.

  • Page 17: Lm9_Base_Id

    The reference frequency for the PLL is 50 MHz. LM9_BASE_ID [$04 Switch and Design number port read only] DATA BIT DESCRIPTION 31-24 spare 23-8 Design ID and Revision DIP switch Figure 6 PcieBiSerialDb37Lm9 ID and Switch Bit Map The DIP Switch is labeled for bit number and ‘1’ ‘0’ in the silk screen. The DIP Switch can be read from this port and used to determine which PcieBiserialDb37Lm9 physical card matches each PCI address assigned in a system with multiple cards installed.

  • Page 18: Lm9_Base_Status

    LM9_BASE_STATUS [$08 Board level Status Port read only] DATA BIT DESCRIPTION 31-10 set to ‘0 undefined undefined set to ‘0’, reserved for additional channels Unmasked Ch0 Interrupt Figure 7 PcieBiSerialDb37Lm9 Status Port Bit Map Channel Interrupt – The local interrupt status from the channel. Each channel can have different interrupt sources.

  • Page 19: Lm9_Chan_Cntrl

    Channel Bit Maps The LM9 design has 1 channel. The basic control signals are the same for the channel base, channel status, FIFO and DMA interfaces across multiple designs. Notes: The offsets shown are relative to the channel base address not the card base address. LM9_CHAN_CNTRL [0x0] Channel Control Register (read/write) Channel Control Register...
  • Page 20 Force Interrupt: When this bit is set to a one, a system interrupt will occur provided the Channel Interrupt enable is set. This is useful for interrupt testing. InUrgent / OutUrgent when set causes the DMA request to have higher priority under certain circumstances.

  • Page 21: Lm9_Chan_Status

    LM9_CHAN_STATUS [0x4] Channel Status Read/Clear Latch Write Port Channel Status Register Data Bit Description Interrupt Status LocalInt 29-28 Spare RxPacketFull RxPacketMt TxPacketFull TxPacketMt BurstInIdle BurstOutIdle TxIdleState RxIdleState TxFifoUnFlLat RxFifoOvFlLat RxPacketCompletedLat TxPacketCompletedLat Read DMA Interrupt Occurred Write DMA Interrupt Occurred Read DMA Error Occurred Write DMA Error Occurred RxAFLvlIntLat TxAELvlIntLat...
  • Page 22 Please note with the Rx side status; the status reflects the state of the FIFO and does not take the 4 deep pipeline into account. For example the FIFO may be empty and there may be valid data within the pipeline. The data count with the combined FIFO and pipeline value and can also be used for read size control.
  • Page 23 TxFifoUnFlLat: When a one is read, an error has been detected. This will occur if FIFO is empty when the state machine tries to read from it. A zero indicates that no error has occurred. This bit is latched and can be cleared by writing back to the Status register with a one in the appropriate bit position.
  • Page 24 Rx Packet Full: When a one is read, the receive Packet FIFO is full; when a zero is read, there is room for at least one more Packet Definition in the FIFO. Tx Packet Empty: When a one is read, the FIFO contains no Packet Definitions; when a zero is read, there is at least one Packet definition in the FIFO.

  • Page 25: Figure 10 Pciebiserialdb37Lm9 Write Dma Pointer Register

    LM9_CHAN_WR_DMA_PNTR [0x8] Write DMA Pointer (write only) BurstIn DMA Pointer Address Register Data Bit Description 31-2 First Chaining Descriptor Physical Address direction [0] end of chain Figure 10 PcieBiSerialDb37Lm9 Write DMA pointer register This write-only port is used to initiate a scatter-gather write [TX] DMA. When the address of the first chaining descriptor is written to this port, the DMA engine reads three successive long words beginning at that address.

  • Page 26: Lm9_Chan_Tx_Fifo_Count

    LM9_CHAN_TX_FIFO_COUNT [0x8] TX [Target] FIFO data count (read only) TX FIFO Data Count Port Data Bit Description 31-16 Spare 15-0 TX Data Words Stored Figure 11 PcieBiSerialDb37Lm9 TX FIFO data count Port This read-only register port reports the number of 32-bit data words in the Transmit FIFO.

  • Page 27: Lm9_Chan_Rx_Fifo_Count

    Status for the DMA activity can be found in the channel control register and channel status register. Notes: 1. Writing a zero to this port will abort a write DMA in progress. 2. End of chain should not be set for the address written to the DMA Pointer Address Register.

  • Page 28: Lm9_Chan_Tx_Amt_Lvl

    LM9_CHAN_TX_AMT_LVL [0x14] Tx almost-empty level (read/write) Tx Almost-Full Level Register Data Bit Description 31-16 Spare 15-0 Tx FIFO Almost-Empty Level Figure 15 PcieBiSerialDb37Lm9 TX ALMOST EMPTY LEVEL register This read/write port accesses the almost-empty level register. When the number of data words in the transmit data FIFO is less than than this value, the almost-empty status bit will be set.

  • Page 29: Lm9_Chan_Tx

    LM9_CHAN_TX [0x1C] Channel Transmit Control Register (read/write) Channel TX Control Register Data Bit Description 27-16 ClkDiv TxMarkingBit TxStartBit TxClockSrc TxClockDir TxParitySel TxRegPacket TxClkPolarity TxDataBitOrder TxDataByteOrder TxUnderFlowEn TxAEIntEn TxIntEn spare TxEn Figure 17 PcieBiSerialDb37Lm9 Channel Transmit Control Register TxEn when set causes the Transmit State Machine to begin operation. When the Transmitter has determined that Data is in the Transmit FIFO, and a packet definition has been read, and CTS is received, data will be transmitted.
  • Page 30 TxAEIntEn when set enables the interrupt based on the TX FIFO Almost Empty flag. When the interrupt occurs a programmable amount of data can be stored into the FIFO making for an efficient DMA or burst of writes to load the FIFO. TxUnderFlowEn when set allows the UnderFlow error status to cause an interrupt to the host.

  • Page 31: Lm9_Chan_Tx_Packet_Len_Fifo

    TxMarkingBit defines the sense of the Stop Bits and Marking State. When cleared the bits following the parity bit leading up to the start bit will be ‘0’. Please note that TxStartBit and TxMarkingBit should have opposite definitions. The default for the Arc-210 is Start = ‘1’ and Marking = ‘0’. ClkDiv is used to define the secondary divisor option.

  • Page 32: Lm9_Chan_Tx_Packet_Len_Reg

    LM9_CHAN_TX_PACKET_LEN_REG [0x24] TX Packet Size Reg TX Data Count Port Data Bit Description 31-0 TX Data Bytes per Packet Figure 19 PcieBiSerialDb37Lm9 TX Packet Size Register This read-write register port holds the number of bytes to transmit per packet. Data is repeatedly sent until the TX FIFO is empty.

  • Page 33: Lm9_Chan_Rx

    LM9_CHAN_RX [0x34] Channel RX Control Register (read/write) Channel Control Register Data Bit Description RxMarkingBit RxStartBit 13-11 spare RxTimeOutEn RxParitySel spare RxClockPol RxDataBitOrder RxDataByteOrder RxFifoOvFlIntEn RxFifoAFIntEn RxIntEn RxParityErrorIntEn RxEn Figure 20 PcieBiSerialDb37Lm9 Channel Rx Control Register RxEn when set causes the Rx State Machine to begin operation. The ReceiveData line is tested and when the marking state is found [10+ marking bits] the state-machine will look for the start bit.
  • Page 34 RxParityErrorIntEn when set enables the interrupt based on the Rx Parity Error condition. When the State-machine moves data to the secondary holding latches, parity is generated based on the “Odd/Even” selection and tested against the stored [received] value. If the parity generated does not match the parity received an error is declared.

  • Page 35: Lm9_Chan_Rx_Packet_Len_Fifo

    Please note that RxStartBit and RxMarkingBit should have opposite definitions. The default for the Arc-210 is Start = ‘1’ and Marking = ‘0’. LM9_CHAN_RX_PACKET_LEN_FIFO [0x38] RX Packet size RX Packet Data Count Port Data Bit Description 31-0 RX Data Bytes per Packet Received Figure 21 PcieBiSerialDb37Lm9 RX Packet Size This read only port holds the packet size definitions.

  • Page 36: Lm9_Chan_Rx_Bytecount_Len

    observed termination sequence [3 clocks] plus some margin can be used to set the time out. Remember to scale for the period. 5 us ~ 165 clocks at 33 MHz. The counter counts from 0 leading to an N+1 TimeOut length. The count is checked with a Greater Than function effectively making it an N based count.

  • Page 37: Loop-Back

    Loop-back The Engineering kit includes reference software, utilizing external loop-back tests. The test set-up included PcieBiSerialDb37Lm9 and loop-back plug. The Pin numbers are for the interconnections on the Loop-back plug. The IO names can be used to accommodate a different set-up. The loop-back plug is a DB37 connector with the interconnections protected with a connector shell.

  • Page 38: Pcie Module Front Panel Io Interface Pin Assignment

    PCIe Module Front Panel IO Interface Pin Assignment The figure below gives the pin assignments for the IO Interface on the PcieBiSerialDb37Lm9. IO_0p (RTS+) IO_0m (RTS-) IO_1p (CTS+) IO_1m (CTS-) IO_2p (SENDDATA+) IO_2m (SENDDATA-) IO_3p (RXDATA+) IO_3m (RXDATA-) IO_4p (SENDTIMING+) IO_4m (SENDTIMING-) IO_5p (RXTIMING+) IO_5m (RXTIMING-)

  • Page 39: Applications Guide

    Applications Guide Interfacing The pin-out tables are displayed with the pins in the same relative order as the actual connectors. Some general interfacing guidelines are presented below. Do not hesitate to contact the factory if you need more assistance. Watch the system grounds. All electrically connected equipment should have a fail-safe common ground that is large enough to handle all current loads without affecting noise immunity.

  • Page 40: Construction And Reliability

    Construction and Reliability PCIe Modules were conceived and engineered for rugged industrial environments. The PcieBiSerialDb37Lm9 is constructed out of 0.062 inch thick high temperature ROHS compliant material. The traces are matched length from the FPGA ball to the IO pin. The analog switches and termination resistors are located directly under the transceivers and connected with “zero stub”...

  • Page 41: Warranty And Repair

    For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty.
  • Page 42 Specifications Logic Interface: PCIe 1-4 lanes. 4 lanes recommended Digital Parallel IO: RS485 IO [LVDS option] Digital Serial IO: ARC-210 serial interface with RTS/CTS SENDDATA/RECEIVEDATA, SENDTIMING/RECEIVETIMING DIP Switch: DipSwitch supplied for board identification and other user purposes. CLK rates supported: PLLA is programmed to select Transmit Clock rate.
  • Page 43 DB37 cable compatible with PCIeBiSerialDB37. Twisted pairs on correct pin pairs. http://www.dyneng.com/DBcabl37.html PCIe BiSerial DB37 LM9 Eng Kit : Windows or Linux Driver software, Loop-Back Plug, reference schematics. Recommended for first time purchases. http://www.dyneng.com/pciebiserialdb37.html All information provided is Copyright Dynamic Engineering Embedded Solutions Page 43...

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