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Dynamic Engineering PCIe8LSwVPX3U User Manual

Pcie 8 lane vpx 3u compatible carrier
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DYNAMIC ENGINEERING
150 Dubois St. Suite C, Santa Cruz, CA 95060
831-457-8891
Fax 831-457-4793
http://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
PCIe8LSwVPX3U
PCIe 8 Lane VPX 3U Compatible Carrier
Corresponding Hardware: Revision B
Fab number 10-2014-1102
Revision B3 10/19/17
©2014-2017 by Dynamic Engineering.

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Summary of Contents for Dynamic Engineering PCIe8LSwVPX3U

  • Page 1 150 Dubois St. Suite C, Santa Cruz, CA 95060 831-457-8891 Fax 831-457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual PCIe8LSwVPX3U PCIe 8 Lane VPX 3U Compatible Carrier Corresponding Hardware: Revision B Fab number 10-2014-1102 Revision B3 10/19/17 ©2014-2017 by Dynamic Engineering.
  • Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to...

  • Page 3: Table Of Contents

    PRODUCT DESCRIPTION Clocking Headers and TestPoints DipSwitch Settings Switch Status LED’s VPX MODULE BACKPLANE IO INTERFACE PIN ASSIGNMENT SCSI P2 – VPX J2  USER VPX P2 VPX Module J1 PCIe lane assignments VPX Module J0 Power assignments APPLICATIONS GUIDE Interfacing Construction and Reliability Thermal Considerations...
  • Page 4 ORDER INFORMATION FIGURE 1 PCIE8LSWVPX3U CLOCKING FIGURE 2 PCIE8LSWVPX3U P2/J2/USER P2 IO FIGURE 3 PCIE8LSWVPX3U PCIE/J1 FIGURE 4 PCIE8LSWVPX3U POWER/J0 FIGURE 5 VITA SYSTEM CLOCKING – MAXIMUM CONFIGURATION FIGURE 6 PCIE8LSWVPX3U LOOPBACK TEST CONFIGURATION Embedded Solutions Page 4...

  • Page 5: Product Description

    Product Description PCIe8LSwVPX3U is part of the Dynamic Engineering PCI and VPX Compatible family of modular I/O components. PCIe8LSwVPX3U adapts a 3U VPX device to one PCIe position. PCIe8LSwVPX3U features a 16 lane switch buffering the connection between the Gold fingers on the PCIe side and the VPX connector.
  • Page 6 PMC-BiSerial-III to act as a system simulator. PCIeBPMC + PMC BiSerial III in the front slot to create, and read back the IO. PCIe8LSwVPX3U + VPX in the second slot for test. The BiSerial also has a SCSI connector allowing easy connection between the bezels for a complete test path.

  • Page 7: Clocking

    Clocking (SSC). The upstream/host port supports a PCIe REFCLK that is either a SSC or a NSSC, or can be configured to use an on board NSSC if desired. Figure 1 shows the clocking architecture of the PCIe8LSwVPX3U. The clocking mode is selected using DIP Switches described in the DIP switch settings section.

  • Page 8: Headers And Testpoints

    12V power to be used by the PCIe8LSwVPX3U. The PCIe gold fingers allow for about 60W of power to be consumed by the board across all VPX voltages including power supply losses. In many cases the power budget is more than sufficient.

  • Page 9: Dipswitch Settings

    DipSwitch Settings SW1 (Switch 1): Global Address Settings Position 1-5 corresponds to GA0-4. ‘0’ when closed (C). ‘1’ when open (O). Position 6 corresponds to GAP. ‘0’ when closed (C). ‘1’ when open (O). Position 7-8 are spare SW2 (Switch 2): PCIe Switch and Clock Operation Settings C = Closed, O = Open Below are the standard settings that are used to configure the PCIeLSwVPX3U VPX port for either NSSC or SSC operation.
  • Page 10 Switch 2,1 – Selects protocol used for initial configuration and/or register access SMBus with ARP (Address Resolution Protocol) SMBus without ARP I2C (default setting) Switch 3 – Enables/Disables use of I2C/SMBus for initial PCIe Switch configuration. I2C/SMBUS NOT used for initial configuration (default setting) I2C/SMBUS is used for initial configuration.

  • Page 11: Switch Status Led's

    Steady on means Gen3 communications, Flashing 2x per second means Gen2 and Flashing 1 time per second means Gen1. Off means link is not operating. Please note: if PCIe8LSwVPX3U is installed in the PC with no User HW present the downstream port LED will be off.

  • Page 12: Vpx Module Backplane Io Interface Pin Assignment

    VPX Module Backplane IO Interface Pin Assignment The figure below gives the pin assignments for the VPX Module IO Interface – from P2/J2 to the PCIe8LSwVPX3U connector. Also see the User Manual for your VPX board for more information. SCSI P2 – VPX J2  USER VPX P2...

  • Page 13: Vpx Module J1 Pcie Lane Assignments

    I5 etc. Please note: (1) VPX definitions are relative to VPX. PCIe connector definitions are relative to the PCIe bus. PCIe8LSwVPX3U reverses the lanes [TX/RX] between the switch connections and the VPX J1 connector to compensate. (2) VPX standard does not support the PCIe reference clock, but does support independent clocking and SSC using a lower frequency REFCLK.

  • Page 14: Vpx Module J0 Power Assignments

    OPEN PERST# FIGURE 4 PCIE8LSWVPX3U POWER/J0 Note: 3.3V Aux is routed to PCIe 3.3V Aux and will be powered from PC power supply as defined by your PC. PERST# is the PCIe reset signal and is also routed to this connector.

  • Page 15: Applications Guide

    – no frame – to allow for better access to everything. The JTAG header can be installed on the rear of PCIe8LSwVPX3U to keep the JTAG programmer out of the way when working on the installed VPX. This will also allow the VPX to be swapped out without disconnecting the JTAG programmer.

  • Page 16: Construction And Reliability

    Power all system power supplies from one switch. Connecting external voltages to the PCIe8LSwVPX3U when it is not powered can damage it, as well as the rest of the host system. This problem may be avoided by turning all power supplies on and off at the same time.

  • Page 17: Vita Multipoint Ssc Clocking Implemenation

    VITA Multipoint SSC Clocking implementation The VITA Specification defines, and the PCIe8LSwVPX3U circuits support the VITA maximum of 32 circuits connected together on a common transmission media. The PCIe8LSwVPX3U implements this feature per VITA specification by generating, supplying, and using a common 25MHz VITA SSC that is transmitted and received using M-LVDS differential transceivers.

  • Page 18: Loopback Testing

    Loopback Testing For both the validation of, and the ATP for PCIE8LSwVPX3U, Dynamic Engineering uses VPX8LXMC3U, XMC-PARALLEL-TTL, and a loopback fixture. Figure 6 shows the validation and ATP test configuration. LOOPBACK XMC-Parallel-TTL VPX8LXMC3U PCIe8LSwVPX3U SCSI FIXTURE PCI Express Host FIGURE 6...

  • Page 19: Warranty And Repair

    For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty.

  • Page 20: Specifications

    Specifications Logic Interfaces: PCIe up to 8 lanes per VPX Access types: Switch isolated PCIe interface, all modes supported. CLK rates supported: Gen1, Gen2, Gen 3 Software Interface: Transparent design with no software required for adapter. Installed VPX will determine control of that device. Initialization: switch selections for Global Addressing if needed.

  • Page 21: Order Information

    68 pin SCSI II to 68 screw terminal converter with DIN rail mounting. HDEcabl68 http://www.dyneng.com/HDEcabl68.html SCSI cables with latch blocks or thumbscrews and various lengths are available. Custom lengths can be ordered. All information provided is Copyright Dynamic Engineering Embedded Solutions Page 21...

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