Related Manuals for Dynamic Engineering PC104p-SpaceWire-Monitor
Summary of Contents for Dynamic Engineering PC104p-SpaceWire-Monitor
- Page 1 User Manual Hardware and Software SpaceWire Monitor Manual Revision 01p6 Revision Date 01/02/2023 Dynamic Engineering 150 DuBois St. Suite B/C Santa Cruz, CA 95060 (831) 457-8891 www.dyneng.com sales@dyneng.com Est. 1988...
- Page 2 SpaceWire Monitor User Manual PC104p-SpaceWire Corresponding Hardware: 10-2008-0903 PCI-SpaceWire Corresponding Hardware: 10-2006-01(04,05) Embedded Solutions...
- Page 3 SpaceWire Monitor User Manual PCIe-SpaceWire Corresponding Hardware: 10-2018-18(02,03) PMC-SpaceWire Corresponding Hardware: 10-2004-08(10,11) Embedded Solutions...
- Page 4 Dynamic Engineering’s products are not authorized for use as critical components in life support devices or systems without express written approval from the president of Dynamic Engineering.
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Page 5: Table Of Contents
SpaceWire Monitor User Manual Table of Contents Design Revision History ............................1 Manual Revision History ............................1 Key Product Features ............................2 Product Description .............................. 2 Product Specifications ............................3 Construction and Reliability ..........................3 Installation and Interfacing Guidelines ......................... 4 Installation ................................. - Page 6 SpaceWire Monitor User Manual Table 11: SpaceWire Channel Status Register ....................13 Table 12: SpaceWire Channel Read DMA Pointer Port ..................15 Table 13: SpaceWire Channel RX FIFO Data Count Port ................. 16 Table 14: SpaceWire RX Packet-Length FIFO Ports ..................16 Table 15: SpaceWire Channel RX Almost Full Level Register ................
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Page 7: Design Revision History
Updated to new manual format, misc. clean-up. Removal of some items [included in SW manuals] NOTE: Dynamic Engineering has made every effort to ensure that this manual is accurate and complete; that being said, the company reserves the right to make improvements or changes to the product described in this document at any time and without notice. -
Page 8: Key Product Features
The decoded data can be stored to system memory, disk, or another device. SpaceWire-Monitor leverages Dynamic Engineering’s previous design experience with the SpaceWire interface series of modular IO. SpaceWire-BK-128RX was chosen as the starting point due to the added memory designed into ports 0 &... -
Page 9: Product Specifications
Standard MDM connectors and pinout. SpaceWire specification number: compliant Construction and Reliability Dynamic Engineering Modules are conceived and engineered for rugged industrial environments. The SpaceWire family is constructed out of 0.062-inch thick High-Temp RoHS-compliant FR4 material. RoHS and standard processing are available options. -
Page 10: Installation And Interfacing Guidelines
Installation and Interfacing Guidelines Some general interfacing guidelines are presented below. If you need more assistance, contact Dynamic Engineering. Also refer to the base HW manuals for each SpaceWire board type. Installation Warning: Connection of incompatible hardware is likely to cause serious damage. -
Page 11: Theory Of Operation
SpaceWire Monitor User Manual Theory of Operation To use the SpaceWire Monitor, replace the SpaceWire cable between two devices with two cables. Install the Monitor into the appropriate location (PMC, PCI, PCIe, or PCI-104), install the driver, and run the application. Please see the SW section for more information on installing the driver and running the Monitor application. -
Page 12: Address Maps And Register Definitions
SpaceWire Monitor User Manual Address Maps and Register Definitions This section documents the register addresses, and register bit maps. SpaceWire Monitor register bits are all initialized to ‘0’ on reset. Because the SpaceWire Monitor channel is a receive (RX) only channel, the majority of transmit (TX) logic that existed in the SpaceWire channel has been disabled. -
Page 13: Register Definitions
SpaceWire Monitor User Manual Register Definitions SpaceWire Base Control Register Table 5: SpaceWire Base Control Register SPWR_BASE_CNTL [0x0000] Base Control Register (read/write) Data Bit Description BigEndianDma Spare 27-25 Spare PLL USE ALT PLL CHK PLL RD PLL RST PLL Enable 31-24, 23-16, 15-8, 7-0 ó... -
Page 14: Spacewire User Switch Port
4-F Spare NOTE: The Major Revision field is the released name for the particular revision. The Minor Revision field is for Dynamic Engineering revision tracking during development, and for minor released updates between Major Updates. Monitor uses Configuration “3”. Switch 7-0: The user switch is read through this port. The bits are read as the lowest byte. Access the read-only port as a long word and mask off the undefined bits. -
Page 15: Spacewire Pll Data Fifo
31-0 Data to PLL or Data from PLL SpaceWire has an improved I2C interface for programming the PLL. Dynamic Engineering driver support packages include utilities to take the .jed file from the Cypress CyberClocks program, parse and load into the FIFO with the proper sequence of controls via Base Control Register. Please see the reference code for the sequence. -
Page 16: Spacewire Channel Control Register
SpaceWire Monitor User Manual NOTE: The PLL settling time is in addition to the transfer time. Several mS should be delayed after programming the PLL to make sure the specified frequencies are within range. 10 mS is recommended. PLL FIFO RX Data Valid: (Bit 6) is set when data is Valid in the output port for the PLL read path. Data is pre-read from the FIFO and held in the FIFO holding register. - Page 17 SpaceWire Monitor User Manual Read DMA Ready: (Bit 31) These two read-only bits report the DMA state-machine status. If they are read as a one, the corresponding DMA state-machine is idle and available to start a transfer. If the bits are read as a zero, the corresponding DMA state-machine is processing a data transfer. Time-Code Flags: (Bit 29-28) The time-code flags have been moved to the control register to make room for the latched almost empty/full status bits that were added to the status register.
- Page 18 SpaceWire Monitor User Manual RX interrupts are bits [12:8] in the SPWR_CHAN_STATUS register and include bits such as Receive FIFO Overflow, which is now handled by the Monitor Status bits, and Credit Error Detected, which would be detected by either of the devices being monitored. RX Almost Full Interrupt Enable: (Bit 12) When this bit is set to a one, an interrupt will be generated when the receive FIFO level becomes equal or greater to the value specified in the SPWR_CHAN_RX_AFL register, provided the channel master interrupt enable is asserted.
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Page 19: Spacewire Channel Status Register
SpaceWire Monitor User Manual SpaceWire Channel Status Register Table 11: SpaceWire Channel Status Register SPWR_CHAN_STATUS_0-1 [0x0054, 0x00A4] (status read/latch clear write) Data Bit Description Latched Receive FIFO Almost Full 29-24 Time-Code Data Interrupt Active Receive Packet Length Valid SpaceWire Link Established Read DMA Error Read DMA List Complete TICK_OUT Received... - Page 20 SpaceWire Monitor User Manual SpaceWire Link Established: Channel Status Register bit [20] – In a SpaceWire design, this bit indicates a link has been established. In the SpaceWire Monitor design, it indicates the link-up, active, and being monitored. Read DMA Error: When a one is read, it indicates that an error has occurred while the corresponding DMA was in progress.
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Page 21: Spacewire Channel Read Dma Pointer Port
SpaceWire Monitor User Manual Receive FIFO Almost Full: When a one is read, the number of data-words in the receive data FIFO for the corresponding channel is greater or equal to the value written to the SPWR_CHAN_RX_AFL register for that channel; when a zero is read, the level is less than that value. Receive FIFO Empty: When a one is read, the receive data FIFO for the corresponding channel contains no data;... -
Page 22: Spacewire Channel Rx Fifo Data Count Port
SpaceWire Monitor User Manual SpaceWire Channel RX FIFO Data Count Port Table 13: SpaceWire Channel RX FIFO Data Count Port SPWR_CHAN_RX_FIFO_COUNT_0-1 [0x0060, 0x00B0] RX FIFO Data Count (read only) Data Bit Description Channels with External RX Data FIFOs 31-20 Number of RX Packet-length Values Stored 19-0 Number of RX Data-Words Stored Channels with Internal RX Data FIFOs... -
Page 23: Spacewire Channel Rx Almost Full Level Register
SpaceWire Monitor User Manual SpaceWire Channel RX Almost Full Level Register Table 15: SpaceWire Channel RX Almost Full Level Register SPWR_CHAN_RX_AFL_0-1 [0x006C. 0x00BC] RX Almost Full Level (read/write) Data Bit Description 31-0 RX FIFO Almost Full Level These read/write ports access the receiver almost-full level registers for the respective channels. When the number of data words in the receive data FIFO is equal or greater than this value, the almost full status bit is set and an interrupt may be generated if it is enabled. -
Page 24: Table 18: Spacewire Monitor Status Register
SpaceWire Monitor User Manual Monitor Mode: these two bits control the Monitor Mode of operation for the channel. Monitor Mode Name Definition “00” Disabled: Monitor is disabled “01” Link-Down-Start: Configures Monitor to capture data after link comes up “10” Link-Up-Start: Configures Monitor to sync to an active/running link then capture data “11”... -
Page 25: Warranty And Repair
For service on Dynamic Engineering products not purchased directly from Dynamic Engineering, contact your reseller. Products returned to Dynamic Engineering for repair by anyone other than the original customer will be treated as out-of-warranty. -
Page 26: Ordering Information
SpaceWire Monitor User Manual Ordering Information Industrial Temperature Rated Components: -40 - 85°C Table 20: Ordering Information Product Description SpaceWire Monitor: combination of Interface Module and Software. Capture data from 2 links cross connected through Monitor. DMA transfer to host. Up to 200 MHz link rate. -
Page 27: Glossary
Cubic feet per minute FIFO First In First Out memory Flash Non-volatile memory used on Dynamic Engineering boards to store FPGA configurations or BIOS JTAG Joint Test Action Group – a standard used to control serial data transfer for test and programming operations. - Page 28 SpaceWire Monitor User Manual Test Data in – this serial line provides the data input to the device controlled by the TMS commands. For example, the data to program the FLASH comes on the TDI line while the commands to the state machine to move through the necessary states comes over TMS.
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