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PCIeBiSerialDb37-LM9
Dynamic Engineering PCIeBiSerialDb37-LM9 Manuals
Manuals and User Guides for Dynamic Engineering PCIeBiSerialDb37-LM9. We have
1
Dynamic Engineering PCIeBiSerialDb37-LM9 manual available for free PDF download: User Manual
Dynamic Engineering PCIeBiSerialDb37-LM9 User Manual (43 pages)
ARC210 IF/Parallel Port PCIe 4 lane Module Transmit and Receive Interface Protocols RS485/422
Brand:
Dynamic Engineering
| Category:
PCI Card
| Size: 0 MB
Table of Contents
Table of Contents
3
Product Description
6
Figure 1 Pciebiserialdb37Lm9 Block Diagram
7
Figure 2 Pciebiserialdb37Lm9 Timing Diagram
11
Address Map
12
Figure 3 Pciebiserialdb37Lm9 Internal Address Map Base Functions
12
Figure 4 Pciebiserialdb37Lm9 Channel Address Map
13
Programming
14
Base Register Definitions
16
Figure 5 Pciebiserialdb37Lm9 Control Base Register Bit Map
16
Figure 6 Pciebiserialdb37Lm9 ID and Switch Bit Map
17
Lm9_Base_Id
17
Figure 7 Pciebiserialdb37Lm9 Status Port Bit Map
18
Lm9_Base_Status
18
Figure 8 Pciebiserialdb37Lm9 Channel Control Register
19
Lm9_Chan_Cntrl
19
Figure 9 Pciebiserialdb37Lm9 Channel Status Port
21
Lm9_Chan_Status
21
Figure 10 Pciebiserialdb37Lm9 Write Dma Pointer Register
25
Figure 11 Pciebiserialdb37Lm9 Tx Fifo Data Count Port
26
Figure 12 Pciebiserialdb37Lm9 Read Dma Pointer Register
26
Lm9_Chan_Rd_Dma_Pntr
26
Lm9_Chan_Tx_Fifo_Count
26
Figure 13 Pciebiserialdb37Lm9 Rx Fifo Data Count Port
27
Figure 14 Pciebiserialdb37Lm9 Rx/Tx Fifo Port
27
Lm9_Chan_Fifo
27
Lm9_Chan_Rx_Fifo_Count
27
Figure 15 Pciebiserialdb37Lm9 Tx Almost Empty Level Register
28
Figure 16 Pciebiserialdb37Lm9 Rx Almost Full Level Register
28
Lm9_Chan_Rx_Afl_Lvl
28
Lm9_Chan_Tx_Amt_Lvl
28
Figure 17 Pciebiserialdb37Lm9 Channel Transmit Control Register
29
Lm9_Chan_Tx
29
Figure 18 Pciebiserialdb37Lm9 Tx Packet Size Fifo
31
Lm9_Chan_Tx_Packet_Len_Fifo
31
Figure 19 Pciebiserialdb37Lm9 Tx Packet Size Register
32
Lm9_Chan_Tx_Packet_Len_Reg
32
Figure 20 Pciebiserialdb37Lm9 Channel Rx Control Register
33
Lm9_Chan_Rx
33
Figure 21 Pciebiserialdb37Lm9 Rx Packet Size
35
Figure 22 Pciebiserialdb37Lm9 Rx Timeout Length
35
Lm9_Chan_Rx_Packet_Len_Fifo
35
Lm9_Chan_Rx_Timeout_Len
35
Figure 23 Pciebiserialdb37Lm9 Rx Bytecount Length
36
Lm9_Chan_Rx_Bytecount_Len
36
Loop-Back
37
Pcie Module Front Panel Io Interface Pin Assignment
38
Figure 24 Pciebiserialdb37Lm9 Front Panel Interface
38
Applications Guide
39
Interfacing
39
Construction and Reliability
40
Thermal Considerations
40
Warranty and Repair
41
Service Policy
41
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