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Dynamic Engineering SpaceWire BK Hardware Manual

4 ports, 200 mhz, dma, pcie, pci, pmc, pc104p
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DYNAMIC ENGINEERING
150 DuBois St., Suite B/C Santa Cruz, CA 95060
(831) 457-8891
https://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
SpaceWire "BK" Model
Hardware Manual
Four-Channel SpaceWire Interface
PCIe, PCI, PC104p, PMC Versions
Manual Revision 03p4
PCI-SpaceWire
Corresponding Hardware: 10-2006-01(04)

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  • Page 1 DYNAMIC ENGINEERING 150 DuBois St., Suite B/C Santa Cruz, CA 95060 (831) 457-8891 https://www.dyneng.com sales@dyneng.com Est. 1988 User Manual SpaceWire “BK” Model Hardware Manual Four-Channel SpaceWire Interface PCIe, PCI, PC104p, PMC Versions Manual Revision 03p4 PCI-SpaceWire Corresponding Hardware: 10-2006-01(04)
  • Page 2 PMC-SpaceWire Corresponding Hardware: 10-2004-08(08,09) PCIe-SpaceWire Corresponding Hardware: 10-2018-18(01-03)
  • Page 3 Corresponding Hardware: 10-2008-09(03-04)
  • Page 4 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to...

  • Page 5: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION THEORY OF OPERATION PROGRAMMING Register Definitions SPWR_BASE_CNTL SPWR_USER_SWITCH SPWR_TIME_CNTRL SPWR_TIME_COUNT SPWR_PLL_FIFO SPWR_PLL_STATUS SPWR_CHAN_CNTRL_0-3 SPWR_CHAN_STATUS_0-3 SPWR_CHAN_FIFO_0-3 SPWR_CHAN_WR_DMA_PNTR_0-3 SPWR_CHAN_TX_FIFO_COUNT_0-3 SPWR_CHAN_RD_DMA_PNTR_0-3 SPWR_CHAN_RX_FIFO_COUNT_0-3 SPWR_CHAN_TX_PKT_LEN_0-3 SPWR_CHAN_RX_PKT_LEN_0-3 SPWR_CHAN_TX_AMT_0-3 SPWR_CHAN_RX_AFL_0-3 SPWR_CHAN_CREDIT_AND_TIMECODE_STATUS_0-3 SPWR_CHAN_RX_PKT_FF_FULL_CNTRL_0-3 (CC)PMC (PCI) PN1 INTERFACE PIN ASSIGNMENT (CC)PMC (PCI) PN2 INTERFACE PIN ASSIGNMENT (CC)PMC PN4 USER INTERFACE PIN ASSIGNMENT APPLICATIONS GUIDE Interfacing...
  • Page 6 THERMAL CONSIDERATIONS WARRANTY AND REPAIR Service Policy Out of Warranty Repairs For Service Contact: SPECIFICATIONS ORDER INFORMATION Embedded Solutions Page 6 of 57...
  • Page 7 List of Figures FIGURE 1 SPACEWIRE BLOCK DIAGRAM FIGURE 2 SPACEWIRE DATA STROBE ENCODING FIGURE 3 SPACEWIRE ADDRESS MAP FIGURE 4 SPACEWIRE BASE CONTROL REGISTER FIGURE 5 SPACEWIRE USER SWITCH PORT FIGURE 6 SPACEWIRE TIME CONTROL REGISTER FIGURE 7 SPACEWIRE TIME COUNT REGISTER FIGURE 8 SPACEWIRE PLL DATA FIFO FIGURE 9...

  • Page 8: Product Description

    Product Description SpaceWire is part of the Dynamic Engineering family of modular I/O. This manual describes the “BK” family of SpaceWire. Currently the PCIe, PCI, PC104p, and PMC versions are available. Please refer to the K family manual for information about the original memory map models.

  • Page 9: Figure 1 Spacewire Block Diagram

    The following diagram shows the “BK” SpaceWire configuration: LVDS LVDS LVDS LVDS buffers buffers buffers buffers SpaceWire SpaceWire SpaceWire SpaceWire Optional FIFO 128Kx32 FIFO A FIFO B FIFO C FIFO D 16K x 32 16K x 32 16K x 32 16K x 32 Data Flow Control...
  • Page 10 If you can use the SpaceWire hardware set but need an alternate protocol please contact Dynamic Engineering. We will redesign the state machines and create a custom interface protocol. See our web page for current protocols offered. Please contact Dynamic Engineering with your custom application.
  • Page 11 All formats available and planned will have a common software interface allowing for porting between systems. Dynamic Engineering offers drivers and reference software for Windows®, Linux, and VxWorks. Each SpaceWire channel is supported by two 16K by 32-bit FIFO’s. The TX FIFO’s support long-word writes and the RX FIFO’s support long-word reads.
  • Page 12 word of 4 bytes will be read, then the lower 3 bytes will be read and sent and the 8 byte will be dropped. In the receive direction the action is similar. Bytes are written as long-words to the RX FIFO.

  • Page 13: Theory Of Operation

    Theory of Operation SpaceWire designs are for transferring data from one point to another using the SpaceWire protocol as specified in document ECSS-E-50-12C, published by the European Cooperation for Space Standardization dated 31 July 2008. Continuous development in the SpaceWire community means fairly frequent updates for new features.
  • Page 14 A controller will drop request when it reaches the end of a scatter-gather list entry or the end of a DMA descriptor acquisition. It will also drop request when a transfer from the device to memory is almost out of data, or when a transfer from memory to the device is almost out of room to store the data, or if it has held the PCI bus for 1024 PCI clocks.

  • Page 15: Figure 2 Spacewire Data Strobe Encoding

    The transmitters will multiplex Time-Code characters, FCT characters, N-characters and NULL characters (in that order of priority) onto the data stream to regulate the flow of data in both directions. At the end of a transmitted packet, the transmitter will append an EOP (or possibly an EEP if relaying a packet with an error) character to the message stream to alert the receiver to the completion of the current packet.
  • Page 16 When the transmitter has sent a NULL and the receiver has received a NULL character, the transmitter sends an FCT character and the receiver looks for an FCT in return. If this occurs, it means that the remote node has recognized the NULL and is ready to connect.
  • Page 17 0x000 to operate in legacy mode. A receive FIFO overflow will also cause a receive error to be latched, but will not in itself cause a link disconnect. If a receive data-packet is in progress when an error occurs, the receiver ceases writing data to the receive data FIFO and writes the receive packet-length FIFO with the current byte-count with the packet error bit set.

  • Page 18: Programming

    If DMA is to be used it may be necessary to acquire a block of non-paged memory that is accessible from the PCI bus in which to store chaining descriptor list entries. If the Dynamic Engineering device drivers are used, the I/O channel driver will handle all the DMA internal mechanics automatically.
  • Page 19 PLL is reprogrammed. If you are writing your own driver, contact Dynamic Engineering and we can send you a file with code excerpts from our driver and test software that cover each step of the process from parsing the .jed file to the low- level bit manipulation of the I C bus.
  • Page 20 Firmware Updates Revision A: First release of BK. See feature table for new features. 8/14 Revision B1: Second release of BK. Updated for new FPGA pinout, external clock recovery, PMC rear IO connector redefined to match ccPMC version. Add lane steering for DMA in Big Endian systems.

  • Page 21: Figure 3 Spacewire Address Map

    Address Map Register Name Offset Description SPWR_BASE_CNTRL 0x0000 // 0 Base control register SPWR_USER_SWITCH 0x0004 // 1 User switch & status read port SPWR_TIME_CNTRL 0x0008 // 2 Time control register SPWR_TIME_COUNT 0x000C// 3 Time Code update rate SPWR_PLL_FIFO 0x0010 // 4 Write to PLL programming FIFO, Read PLL read-back FIFO SPWR_PLL_STATUS 0x0014 // 5 Status associated with PLL programming SPWR_CHAN_CNTRL_0...

  • Page 22: Register Definitions Spwr_Base_Cntl

    A value of zero corresponds to a divisor of one. A value of one corresponds to a divisor of two etc. If the Dynamic Engineering device driver is used, these values are written automatically when the PLL is programmed.
  • Page 23 PLL RD: when set selects reading the PLL, when cleared selects writing to the PLL registers. PLL_CHK: Set to check PLL address. PLL USE ALT: When set selects the Alternate PLL address. 0 => x69, 1 => x6A Time-Code Control Flags: These two bits are added to the six-bit time count in bit positions 7 and 6.

  • Page 24: Spwr_User_Switch

    SPWR_USER_SWITCH [0x0004] User Switch Port - read only Dipswitch Port Data Bit Description 31-28 Spare Channel 3 Interrupt Active Channel 2 Interrupt Active Channel 1 Interrupt Active Channel 0 Interrupt Active 23-20 Xilinx Design Revision Minor 19-16 Xilinx Design Configuration Type 15-8 Xilinx Design Revision Number Major Switch Setting...
  • Page 25 4-F => Spare The Major Revision field is the released name for the particular revision – x02 at the moment. The Minor Revision field is for Dynamic Engineering revision tracking during development, and for minor released updates between Major Updates.

  • Page 26: Spwr_Time_Cntrl

    SPWR_TIME_CNTRL [0x0008] Time Control Register (read/write) Time Control Register Data Bit Description 31-15 Spare 14-12 Channel 3 Time-Code Source Control Spare 10-8 Channel 2 Time-Code Source Control Spare Channel 1 Time-Code Source Control Spare Channel 0 Time-Code Source Control FIGURE 6 SPACEWIRE TIME CONTROL REGISTER All bits are active high and are reset to zero on system power-up or reset.

  • Page 27: Spwr_Time_Count

    SPWR_TIME_COUNT [0x000C] Time Count Register (read/write) Time Control Register Data Bit Description 31-0 Master Timer Divider Count FIGURE 7 SPACEWIRE TIME COUNT REGISTER Master Timer Divider Count: This count is used to generate the TICK_IN signal when a channel is used as the source for time-codes. The counter is clocked by the 80 MHz link clock and this count represents the count at which the counter resets to zero, increments the time-code and issues a TICK_IN signal.

  • Page 28: Spwr_Pll_Fifo

    SPWR_PLL_FIFO [0x0010] PLL Data FIFO (read/write) PLL Data FIFO Data Bit Description 31-0 Data to PLL or Data From PLL FIGURE 8 SPACEWIRE PLL DATA FIFO SpaceWire has an improved I2C interface for programming the PLL. Dynamic Engineering driver support packages include utilities to take the .jed file from the Cypress CyberClocks program, parse and load into the FIFO with the proper sequence of controls via Base Control Register.
  • Page 29 The PLL Status bits are used to as feed-back to control the transfer of data to and from the PLL FIFO. TX refers to programming the PLL and RX refers to reading back from the PLL. The Latched Bits {10,9} are held until cleared by writing back with the bit position(s) set. Usually these bits are cleared before starting an operation.

  • Page 30: Spwr_Chan_Cntrl_0-3

    SPWR_CHAN_CNTRL_0-3 [0x0050, 0x00A0, 0x00F0, 0x0140] Channel Control Register (read/write) Channel Control Register Data Bit Description Read DMA Ready (read only) Write DMA Ready (read only) 29-28 Time-Code Flags (read only) 27-26 Spare Return Valid Packet-Lengths Only Enable Transmit Packet-Length Repeat Receive FIFO Programmable Level Load Transmit FIFO Programmable Level Load Read DMA Arbitration Priority Enable...
  • Page 31 Transmit/Receive FIFO Reset: When one or both of these bits are set to a one, the corresponding data FIFO, packet-length FIFO and control and status circuitry will be reset. When these bits are zero, normal FIFO operation is enabled. FIFO resets are referenced to the PCI clock, two periods are required for proper reset.
  • Page 32 RX Almost Full Interrupt Enable: When this bit is set to a one, an interrupt will be generated when the receive FIFO level becomes equal or greater to the value specified in the SPWR_CHAN_RX_AFL register, provided the channel master interrupt enable is asserted.
  • Page 33 Transmit/Receive FIFO Programmable Level Load: These bits are only valid for channels with external data FIFOs. The load bits must be active during FIFO reset to select the programmable level feature. Once selected, these bits must be set to zero for normal FIFO operation.

  • Page 34: Spwr_Chan_Status_0-3

    SPWR_CHAN_STATUS_0-3 [0x0054, 0x00A4, 0x00F4, 0x0144] (Status read/Latch clear write) Channel Status Register Data Bit Description Latched Receive FIFO Almost Full Latched Transmit FIFO Almost Empty 29-24 Time-Code Data Interrupt Active Receive Packet Length Valid Transmit Purge Error SpaceWire Link Established Read DMA Error Write DMA Error Read DMA List Complete...
  • Page 35 Transmit FIFO Almost Empty: When a one is read, the number of data-words in the transmit data FIFO for the corresponding channel is less than or equal to the value written to the SPWR_CHAN_TX_AMT register for that channel; when a zero is read, the level is more than that value.
  • Page 36 Disconnect Error Detected: When a one is read, it indicates that a disconnect error has occurred since the status was last cleared. This bit is latched and must be cleared by writing the same bit back to the channel status port. A zero indicates that no disconnect error has occurred.
  • Page 37 bit back to the channel status port. A zero indicates that the corresponding DMA has not completed. Write/Read DMA Error: When a one is read, it indicates that an error has occurred while the corresponding DMA was in progress. This could be a target or master abort or an incorrect direction bit in one of the DMA descriptors.

  • Page 38: Spwr_Chan_Fifo_0-3

    SPWR_CHAN_RX_AFL register. A zero indicates that the FIFO has not become almost full. This bit is latched and can be cleared by writing back to the Status register with a one in this bit position. Latched Transmit FIFO Almost Empty: When a one is read, it indicates that the transmit FIFO data count has become less than or equal to the value in the SPWR_CHAN_TX_AMT register.
  • Page 39 the address of the next chaining descriptor in the list of buffer memory blocks. This process is continued until the end-of-chain bit in one of the next pointer values read indicates that it is the last chaining descriptor in the list. All three values are on LW boundaries and are LW in size.

  • Page 40: Spwr_Chan_Tx_Fifo_Count_0-3

    SPWR_CHAN_TX_FIFO_COUNT_0-3 [0x005C, 0x00AC, 0x00FC, 0x014C] TX FIFO Data Count (read only) TX FIFO Data Count Channels with External TX Data FIFO’s Data Bit Description 31-20 Number of TX Packet-Length Values Stored 19-0 Number of TX Data-Words Stored Channels with Internal TX Data FIFO’s 31-20 Number of TX Packet-Length Values Stored 19-14...

  • Page 41: Spwr_Chan_Rd_Dma_Pntr_0-3

    SPWR_CHAN_RD_DMA_PNTR_0-3 [0x0060, 0x00B0, 0x0100, 0x0150] Write only Output DMA Pointer Address Port Data Bit Description 31-0 First Chaining Descriptor Physical Address FIGURE 15 SPACEWIRE CHANNEL READ DMA POINTER PORT This write-only port is used to initiate a scatter-gather read [RX] DMA. When the address of the first chaining descriptor is written to this port, the DMA engine reads three successive long words beginning at that address.

  • Page 42: Spwr_Chan_Rx_Fifo_Count_0-3

    SPWR_CHAN_RX_FIFO_COUNT_0-3 [0x0060, 0x00B0, 0x0100, 0x0150] RX FIFO Data Count (read only) RX FIFO Data Count Channels with External RX Data FIFOs Data Bit Description 31-20 Number of RX Packet-Length Values Stored 19-0 Number of RX Data-Words Stored Channels with Internal RX Data FIFO’s 31-20 Number of RX Packet-Length Values Stored 19-15...

  • Page 43: Spwr_Chan_Tx_Pkt_Len_0-3

    SPWR_CHAN_TX_PKT_LEN_0-3 [0x0064, 0x00B4, 0x0104, 0x0154] TX Packet length FIFO Ports (write only) TX Packet Length FIFO Ports Channels with 2 Gbyte Maximum Packet-Lengths Data Bit Description Terminate Packet with an Error-End-of-Packet 30-0 Packet Length (31 bits) FIGURE 17 SPACEWIRE TX PACKET LENGTH FIFO PORTS SPWR_CHAN_RX_PKT_LEN_0-3 [0x0064, 0x00B4, 0x0104, 0x0154] RX Packet length FIFO Ports (read only) RX Packet Length FIFO Ports...

  • Page 44: Spwr_Chan_Tx_Amt_0-3

    SPWR_CHAN_TX_AMT_0-3 [0x0068, 0x00B8, 0x0108, 0x0158] TX Almost-Empty Level (read/write) TX Almost Empty Level Register Data Bit Description 31-0 TX FIFO Almost-Empty Level FIGURE 19 SPACEWIRE CHANNEL TX ALMOST EMPTY LEVEL REGISTER These read/write ports access the transmitter almost-empty level registers for the respective channels.

  • Page 45: Spwr_Chan_Credit_And_Timecode_Status_0-3

    SPWR_CHAN_CREDIT_AND_TIMECODE_STATUS_0-3 [0x0070, 0x00C0, 0x0110, 0x0160] Channel Credit and Time Code Status (read only) Channel Credit and Timecode Status Register Data Bit Description 31-18 Spare 17-12 Channel Time Code 11-10 Spare Transmit Credit Spare Flow Control Token Count FIGURE 21 SPACEWIRE CHANNEL TIMECODE AND CREDIT STATUS REGISTER Important note: This register was implemented for test and debug purposes only.

  • Page 46: Spwr_Chan_Rx_Pkt_Ff_Full_Cntrl_0-3

    SPWR_CHAN_RX_PKT_FF_FULL_CNTRL_0-3 [0x0074, 0x00C4, 0x0114, 0x0164] RX Packet FIFO Full Control Register (read/write) RX Packet FIFO Full Control Register Data Bit Description 31-10 Spare RX Packet FIFO Full Level FIGURE 22 SPACEWIRE CHANNEL RX PACKET FIFO FULL CONTROL REGISTER These bits are set to 0x3DF on system power-up or reset. RX Packet FIFO Full Level: These bits set the RX Packet FIFO Full Threshold level.

  • Page 47: Figure 23 Mdm I/O Connector Pinouts

    SpaceWire I/O Channel Pin Assignment MDM Connectors Channel 0 DIN 0 + DIN 0 - SIN 0 + SIN 0 - SHIELD0 SOUT 0 + SOUT 0 - DOUT 0 + DOUT 0 - Channel 1 DIN 1 + DIN 1 - SIN 1 + SIN 1 - SHIELD1...

  • Page 48: (Cc)Pmc (Pci) Pn1 Interface Pin Assignment

    (cc)PMC (PCI) Pn1 Interface Pin Assignment The figure below gives the pin assignments for the PMC Module PCI Pn1 Interface on the (cc)PMC-SpaceWire. See the User Manual for your carrier board for more information. Unused pins may be assigned by the specification and not needed by this design.

  • Page 49: (Cc)Pmc (Pci) Pn2 Interface Pin Assignment

    (cc)PMC (PCI) Pn2 Interface Pin Assignment The figure below gives the pin assignments for the PMC Module Pn2 Interface on the (cc)PMC-SpaceWire. See the User Manual for your carrier board for more information. Unused pins may be assigned by the specification and not needed by this design. +12V +3.3V RST#...

  • Page 50: (Cc)Pmc Pn4 User Interface Pin Assignment

    (cc)PMC Pn4 User Interface Pin Assignment The figure below provides the pin assignments for the ccPMC and PMC SpaceWire Modules routed to Pn4. Also, see the User Manual for your carrier board for information on interfacing with Pn4. Ports 0-2 are only implemented on PMC Pn4 when the rear IO ordering option is selected.

  • Page 51: Applications Guide

    Applications Guide Interfacing Some general interfacing guidelines are presented below. Do not hesitate to contact the factory if you need more assistance. Proper ESD handling procedures must be followed when handling the PMC-SpaceWire. The card is shipped in an anti-static, shielded bag. The card should remain in the bag until ready for use.

  • Page 52: Construction And Reliability

    Construction and Reliability Dynamic Engineering Modules are conceived and engineered for rugged industrial environments. The SpaceWire family is constructed out of 0.062-inch thick High-Temp ROHS compliant FR4 material. ROHS and standard processing are available options. Through-hole and surface-mount components are used. PMC connectors are rated at 1 Amp per pin, 100 insertion cycles minimum.
  • Page 53 For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty.
  • Page 54 Specifications Formats: ccPMC, PMC, PCI, PCIe, PC104p, PCI-104 Host Interface (PCI): PCI Interface 33 MHz. 32-bit Serial Interfaces: Four SpaceWire channels TX Bit-rates generated: 2 – 200 MHz for each SpaceWire channel Software Interface: Control Registers, FIFO’s, and Status Ports Initialization: Hardware reset forces all registers to 0 except as noted Access Modes:...
  • Page 55 Construction: High Temp ROHS compliant FR4 Multi-Layer Printed Circuit, Through-Hole and Surface-Mount Components Temperature Coefficient: 2.17 W/ o C for uniform heat across PMC [similar for other formats] Components Industrial Temperature components standard Power 3.3V and 5V. Both voltages +/- 5% Embedded Solutions Page 55 of 57...
  • Page 56 Order Information Please refer to our SpaceWire webpage for the most up to date information: https://www.dyneng.com/spacewire.html PCIe-SpaceWire-BK https://www.dyneng.com/PCIe-SpaceWire.html Standard version with two 64KB FIFO’s per channel, standard SpaceWire [ECSS-E-50-12C] timing and protocol. Four channels through the Bezel. Industrial Temperature STD. 200 MHz operation. PCI-SpaceWire-BK https://www.dyneng.com/pci_SpaceWire.html Standard version with two 64KB FIFO’s per channel,...
  • Page 57 DESWCB https://www.dyneng.com/deswcb.html Dynamic Engineering SpaceWire Connector Board – multi- channel cable to single channel cable adapter. Up to 28 MDM connectors can be mounted – specify number when ordering – Plastic housing. Route multi-channel cable to side or rear of housing and break out in the front.

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