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Dynamic Engineering LVDS 8R Manual

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This document contains information of proprietary interest to Dynamic Engineering. It has been supplied in
confidence and the recipient, by accepting this material, agrees that the subject matter will not be copied or
reproduced, in whole or in part, nor its contents revealed in any manner or to any person except to meet the
purpose for which it was delivered.
Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the
company reserves the right to make improvements or changes in the product described in this document at any
time and without notice. Furthermore, Dynamic Engineering assumes no liability arising out of the application or
use of the device described herein.
The electronic equipment described herein generates, uses, and can radiate radio frequency energy. Operation of
this equipment in a residential area is likely to cause radio interference, in which case the user, at his own
expense, will be required to take whatever measures may be required to correct the interference.
Dynamic Engineering's products are not authorized for use as critical components in life support devices or
systems without the express written approval of the president of Dynamic Engineering.
This product has been designed to operate with PCI and compatible user-provided equipment. Connection of
incompatible hardware is likely to cause serious damage.
©2000,2001,2002 by Dynamic Engineering.
Manual Revision E. Revised 4/4/02
PCI LVDS 8R
8 Channel LVDS Serial Interface
Dynamic Engineering
435 Park Drive, Ben Lomond, CA 95005
831-336-8891
www.dyneng.com
10-2001-0202
Hardware and Software Design • Manufacturing Services
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Summary of Contents for Dynamic Engineering LVDS 8R

  • Page 1 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the product described in this document at any time and without notice.

  • Page 2: Table Of Contents

    Table of Contents Introduction Memory Map DMA Definitions DMA Base Control DMA Status DMA FIFO Holding Register Target Read DMA FIFO Holding Register DMA Read DMA Xilinx Status Address Generator Definitions Address Generator SDRAM Start Address Registers Address Generator SDRAM Length Registers Address Generator SDRAM Control Registers Address Generator SDRAM Base Control Registers Address Generator SDRAM Status Registers...
  • Page 3 Operational Brief: LVDS Connector Definition Construction and Reliability Thermal Considerations Warranty and Repair Service Policy Out of Warranty Repairs For Service Contact: Specifications Order Information Hardware and Software Design • Manufacturing Services page 3...

  • Page 4: Introduction

    Introduction The PCI_LVDS_8R features 8 channels of LVDS input. Each input channel is composed of 3 serial data pairs plus a reference clock. The reference clock can operate at speeds up to 175 MHz. The National DS90CR218 [TIA/EIA- 644] or equivalent receiver chip is used. The receiver converts the three parallel streams into 21 bit parallel data.
  • Page 5 The Data in the Output FIFO passes through the DMA Xilinx before the PLX [PCI interface] has access. The data is written into the Output FIFO at 66 MHz and read out at 33 Mhz. The interface supports DMA and target reads. The 2:1 load to read bandwidth insures rapid and efficient data transfer in Retrieve mode.
  • Page 6 FIFO 1K x 32 FE Xilinx LVDS IF LVDS IF FIFO LVDS IF LVDS IF FIFO SDRAM SDRAM 1K x 32 LVDS IF LVDS IF FIFO LVDS IF LVDS IF 256 MB 256 MB FIFO FE Xilinx Add Gen PLX 9054 DMA Xilinx Xilinx Control Bus...

  • Page 7: Memory Map

    Memory Map (Addresses shown as byte) Addresses are offsets from the PCI Base Address defined by the system and the PLX 9054. The PLX 9054 requests several BARs. The BAR associated with Space 0 is the base address for the internal PCI_LVDS_8R hardware.
  • Page 8 Front End Filter Channels 2,3 Decode number Address offse t Chip Definition 0040 FE23 TAG_DEF_2 0044 FE23 X2_STOP 0048 FE23 X3_STOP 004C FE23 Y2_STOP 0050 FE23 Y3_STOP 0054 FE23 Z2_STOP 0058 FE23 Z3_STOP 005C FE23 X_TOTAL_2_RDBK 0060 FE23 X_TOTAL_3_RDBK 0064 FE23 2,3_DTA_PAT 0068...
  • Page 9 Address Generator Channels 0-3 Decode number Address offset Chip Definition 0080 ADD0_3 Start ADD CH 0 0084 ADD0_3 Start ADD CH 1 0088 ADD0_3 Start ADD CH 2 008C ADD0_3 Start ADD CH 3 0090 ADD0_3 Length CH 0 0094 ADD0_3 Length CH 1 0098...
  • Page 10 Front End Filter Channels 4,5 Decode number Address offset Chip Definition 0100 FE45 TAG_DEF_4 0104 FE45 X4_STOP 0108 FE45 X5_STOP 010C FE45 Y4_STOP 0110 FE45 Y5_STOP 0114 FE45 Z4_STOP 0118 FE45 Z5_STOP 011C FE45 X_TOTAL_4_RDBK 0120 FE45 X_TOTAL_5_RDBK 0124 FE45 4,5_DTA_PAT 0128 FE45...
  • Page 11 0164 FE67 6,7_DTA_PAT 0168 FE67 FIFO_6 WRT 016C FE67 FIFO_7 WRT 0170 FE67 TAG_DEF_7 0174 FE67 FE_DONE_6 0178 FE67 FE_DONE_7 017C FE67 Preload data counter 6-7 Address Generator Channels 4-7 Decode number Address offset Chip Definition 0180 ADD4_7 Start ADD CH 4 0184 ADD4_7 Start ADD CH 5...

  • Page 12: Dma Base Control 1

    PLX Interface, Decode and Control Decode number Address offset Chip Definition 0400 DMA Base Control r-w 0404 0408 040C 0410 0414 0418 041C 0420 0424 0428 042C 0430 0434 DMA Xilinx Status Read 0438 DMA FIFO data slave read 043C DMA Status read / DMA Status Clear write 2XXX DMA Data Read...
  • Page 13 DMA Definitions DMA Base Control $0400 Read – Write Bit# Definition Reset_0 Reset_1 Reset_2 Reset_3 Reset_4 spare spare LED Control READ_EN_STD READ_EN_DMA Channel 15-11 spare Int En 0 Int En 1 Int En 2 Int En 3 Int En 4 Int En 5 Int En 6 Int En 7...
  • Page 14 Reset_0 when 0 resets the FE Xilinx devices (4). When ‘1’ enables the FE Xilinx devices. Reset_1 when 0 resets the input FIFOs (16). When ‘1’ enables the Input FIFOs. The FIFOs must be enabled then reset then re-enabled as part of initialization. The clock selection should be to PCI clock for this operation. Please refer to the FE Xilinx description for more details.
  • Page 15 flag; when the output FIFO is not Empty data is moved into the holding register. The Valid bit is set when data is ready to be read and cleared when the data is “stale” or not updated. READ_EN_DMA when ‘1’ enables the read state-machine in the DMA mode. When the PLX device accesses from the DMA read address;...

  • Page 16: Dma Status 1

    DMA Status $043C Bit# Definition Done channel 0 Done channel 1 Done channel 2 Done channel 3 Done channel 4 Done channel 5 Done channel 6 Done channel 7 FIFO_0_Err FIFO_1_Err Interrupt RQST 23-16 SW7-0 undefined valid mt_out0n hf_out0n ff_out0n mt_out1n hf_out1n ff_out1n...

  • Page 17: Dma Fifo Holding Register Target Read 1

    mt_xn is active low. ‘0’ – FIFO is empty hf_xn is active low ‘0’ – FIFO is half full or more ff_xn is active low ‘0’ – FIFO is full. 0 corresponds to channels 0-3, and 1 to channels 4-7. Done channel X when 1 is done meaning that the requested samples have been transferred.

  • Page 18: Dma Fifo Holding Register Dma Read 1

    DMA FIFO Holding Register DMA Read $2XXX Bit# Definiti on 31-0 Output FIFO data Read the data stored within the Output FIFO. Select the Output FIFO to read with the Channel definition. Enable the process with READ_EN_DMA. When enabled and a read to this address occurs the DMA engine within the Xilinx is started.

  • Page 19: Dma Xilinx Status 1

    DMA Xilinx Status $0434 Bit# Definition DN01 DN23 DN45 DN67 DNL0 DNL1 DNA0 DNA1 DNx are the done bits from the Xilinx devices. After initialization the Done signal should be ‘1’ if a proper load has taken place. Hardware and Software Design • Manufacturing Services page 19...

  • Page 20: Address Generator Definitions 2

    Address Generator Definitions Address Generator SDRAM Start Address Registers 0080 ADD0_3 Start ADD CH 0 0084 ADD0_3 Start ADD CH 1 0088 ADD0_3 Start ADD CH 2 008C ADD0_3 Start ADD CH 3 0180 ADD4_7 Start ADD CH 4 0184 ADD4_7 Start ADD CH 5 0188...

  • Page 21: Address Generator Sdram Length Registers 2

    In no case are smaller than 64 bit data words written to or read from the SDRAM. There are no restrictions for page boundaries of the SDRAM. If the initial starting address is placed within x10 before an SDRAM page boundary, then the hardware will process the first part of the transfer as a sequence of individual transfers then go to burst mode at the page boundary.

  • Page 22: Address Generator Sdram Control Registers 2

    The Length register is the number of 64 bit words to transfer into or out of SDRAM. The number of words transferred is N. The count operates from 1<->N providing the transfer length. Because we do not use “0” as a length the address generator can reach 64M-1 [all but 1 64 bit word] words from any one channel in one transfer.
  • Page 23 or 5,6,7 will result in an error. The hardware will terminate the operation without doing any transfers and set the done bits for channels 1,2,3 [5,6,7]. Normally only channel 0 or 4 will have the done bit set. The start bit is read/writeable and resettable. The start bit will, once the SDRAM is initialized and the FIFO is ready, start a transfer or keep one going.
  • Page 24 access and to pre-load channel 0 after initialization. In Retrieve and Direct mode the pre-load control has no affect. Hardware and Software Design • Manufacturing Services page 24...

  • Page 25: Address Generator Sdram Base Control Registers 2

    Address Generator SDRAM Base Control Registers 0x00B0 ADD0_3 SDRAM Base 0-3 0x01B0 ADD4_7 SDRAM Base 4-7 Bit# Definition Initialize SDRAM 0 = hold inactive, 1 = initialize undefined – mask off for read-back swp EEPROM write protect [Memory on SDRAM DIMM] SDA direction 1 = write, 0 = read SDA data The Control register is used to access the EEPROM supplied on the DIMM if desired and to control initialization.
  • Page 26 After initialization the hardware enters a series of states called init_refresh where the SDRAM is ready to use but a command has not been detected. A counter delays for 256 clocks then a refresh cycle [4] occurs in an endless loop.

  • Page 27: Address Generator Sdram Status Registers 2

    Address Generator SDRAM Status Registers 0x00BC ADD0_3 Status 0-3 Bit# Definition Done channel 0 mt_0n hf_0n ff_0n Done channel 1 mt_1n hf_1n ff_1n Done channel 2 mt_2n hf_2n ff_2n Done channel 3 mt_3n hf_3n ff_3n mt_out0n hf_out0n ff_out0n Hardware and Software Design • Manufacturing Services page 27...
  • Page 28 0x01BC ADD4_7 Status 4-7 Bit# Definition Done channel 4 mt_4n hf_4n ff_4n Done channel 5 mt_5n hf_5n ff_5n Done channel 6 mt_6n hf_6n ff_6n Done channel 7 mt_7n hf_7n ff_7n mt_out1n hf_out1n ff_out1n The status register reports the Input FIFO status, Done bits from the FE Xilinx, and the Output FIFO status. mt_xn is active low.

  • Page 29: Fe Tag Bit Definition Registers 2

    FE Definitions FE Tag Bit Definition Registers 0000 FE01 TAG_DEF_0 0030 FE01 TAG_DEF_1 0040 FE23 TAG_DEF_2 0070 FE23 TAG_DEF_3 0100 FE45 TAG_DEF_4 0130 FE45 TAG_DEF_5 0140 FE67 TAG_DEF_6 0170 FE67 TAG_DEF_7 Read – Write Bit# Definition Tag 0 channel Start Save Tag1 channel Start Save Tag 2 channel Start Save Tag 3 channel Start Save...
  • Page 30 Two registers at different offsets with the same bit definitions provided for the A and B channels. Tag Bit definitions : The tag bits are received from the de-serializer as part of the data stream. The received tag bits are decoded using the definitions in the base register. For example if a tag pattern of ‘00’ is received then bits 1,0 are used to determine if the data should be saved or not and if the pattern is a start pattern or not.
  • Page 31 Clock Select : When 0 the PCI clock is used instead of the de-serializer clock. When 1 the de-serializer clock is used. Select the PCI clock to use the load FIFO mode. To fill a specific value into all of SDRAM, write the value to the holding register, select the PCI clock, and start a capture with X set to max size and the memory controller set to have the channel selected start at 0 and occupy the entire space.

  • Page 32: Fe X Stop Registers 3

    FE X Stop Registers 0004 FE01 X0_STOP 0008 FE01 X1_STOP 0044 FE23 X2_STOP 0048 FE23 X3_STOP 0104 FE45 X4_STOP 0108 FE45 X5_STOP 0144 FE67 X6_STOP 0148 FE67 X7_STOP Xx Stop : Read – write 26 – 0 set the number of samples to capture per X loop. FE Y Stop Registers 000C FE01...

  • Page 33: Fe Z Stop Registers 3

    FE Z Stop Registers 0014 FE01 Z0_STOP 0018 FE01 Z1_STOP 0054 FE23 Z2_STOP 0058 FE23 Z3_STOP 0114 FE45 Z4_STOP 0118 FE45 Z5_STOP 0154 FE67 Z6_STOP 0158 FE67 Z7_STOP Zx Stop : Read – Write 20 – 0 set the number of loops of X and Y to implement. If Y is not set then use a larger X value and program to Please note that all three stop values count from 0 to the value programmed –...

  • Page 34: Fe Data Holding Register 3

    of a new acquisition and keeps a cumulative count of the number of samples written to the input FIFO. When running in direct mode with a continuous stream of input data the counter will roll over after 0x7ffffff samples have been written to the input FIFO. In capture mode this is the size of one SDRAM bank, so it is the maximum amount that can be written to any one channel.

  • Page 35: Fe Channel Done 3

    FE Channel Done 0034 FE01 FE_DONE_0 0038 FE01 FE_DONE_1 0074 FE23 FE_DONE_2 0078 FE23 FE_DONE_3 0134 FE45 FE_DONE_4 0138 FE45 FE_DONE_5 0174 FE67 FE_DONE_6 0178 FE67 FE_DONE_7 Writing to the “Done” register for a channel will force a Done signal to be sent to the Address generator for that channel.

  • Page 36: Fe Pre-Load Counter 3

    FE Pre-load Counter 003C FE01 Preload data counter 0-1 007C FE23 Preload data counter 2-3 013C FE45 Preload data counter 4-5 017C FE67 Preload data counter 6-7 27-16 load 1,3,5,7 11-0 load 0,2,4,6 A write to the Pre-Load Counter address will load the counters with the start pattern. The lower [Channel A] counter will be loaded with the 11-0 data bits and the upper [channel B] will be loaded from 27-16.
  • Page 37 Operational Brief: Xilinx Xilinx REn,OEn input lvds_lat SDRAM lvds_fe FIFO Capture Retrieve Direct Control Address & Control lvds_add Status Xilinx output FIFO Hardware and Software Design • Manufacturing Services page 37...
  • Page 38 In Capture mode the Address Generator hardware waits for the combination of an active channel request [start] and the half full status true condition from the corresponding input channel. When data is present the state machine will begin to transfer the data from the input FIFO to the SDRAM. The transfers occur with burst accesses as much as possible.
  • Page 39 In Direct mode data is moved from the Input FIFO to the Output FIFO bypassing the SDRAM. The half-full flag is used to determine when there is data in the Input FIFO. The clock rate and number of accepted samples will determine the captured data rate.
  • Page 40 LVDS Connector Definition [3M N102A0-52E2VC] Signal Name Alternate Name GND* 2 – 9 SPARE CH6RXCLKP 06_CLK_T CH6RXCLKM 06_CLK_C CH6RX2P CH6RX2M CH6RX1P 06_UDATA_T CH6RX1M 06_UDATA_C CH6RX0P 06_LDATA_T CH6RX0M 06_LDATA_C GND* GND* CH4RXCLKP 04_CLK_T CH4RXCLKM 04_CLK_C CH4RX2P CH4RX2M CH4RX1P 04_UDATA_T CH4RX1M 04_UDATA_C CH4RX0P 04_LDATA_T CH4RX0M...
  • Page 41 CH1RX2P CH1RX2M CH1RX1P 01_UDATA_T CH1RX1M 01_UDATA_C CH1RX0P 01_LDATA_T CH1RX0M 01_LDATA_C GND* GND* CH0RXCLKP 00_CLK_T CH0RXCLKM 00_CLK_C CH0RX2P CH0RX2M CH0RX1P 00_UDATA_T CH0RX1M 00_UDATA_C CH0RX0P 00_LDATA_T CH0RX0M 00_LDATA_C GND* GND* 51-60 SPARE CH7RX0M 07_LDATA_C CH7RX0P 07_LDATA_T CH7RX1M 07_UDATA_C CH7RX1P 07_UDATA_T GND* CH7RX2M CH7RX2P CH7RXCLKM 07_CLK_C...
  • Page 42 CH5RX0P 05_LDATA_T CH5RX1M 05_UDATA_C CH5RX1P 05_UDATA_T CH5RX2M CH5RX2P CH5RXCLKM 05_CLK_C CH5RXCLKP 05_CLK_T GND* GND* CH3RX0M 03_LDATA_C CH3RX0P 03_LDATA_T CH3RX1M 03_UDATA_C CH3RX1P 03_UDATA_T CH3RX2M CH3RX2P CH3RXCLKM 03_CLK_C CH3RXCLKP 03_CLK_T GND* GND* CH2RX0M 02_LDATA_C CH2RX0P 02_LDATA_T CH2RX1M 02_UDATA_C CH2RX1P 02_UDATA_T CH2RX2M CH2RX2P CH2RXCLKM 02_CLK_C CH2RXCLKP...
  • Page 43 If the product is found to be defective within the terms of this warranty, Dynamic Engineering’s sole responsibility shall be to repair, or at Dynamic Engineering’s sole option to replace, the defective product.
  • Page 44 Dynamic Engineering’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Dynamic Engineering.
  • Page 45 Specifications Logic Interface: PCI 2.1, 32 bit 33 MHz. PLX 9054 LVDS Interface: 8 Channels of receive: Clock, Serial 0, Serial 1 implemented based on National DS90CR218. TIA/EIA-644 compliant. 175 MHz. Serial data rate per serial channel – 14 bits at 25 MHz. Internal. Options for 21 bit interface.
  • Page 46 Engineering Kit - PDF of schematic, Reference Software including “C” source that we use for testing the design [NT, WinRT environment], LVDS Cable, MDRterm100 [LVDS breakout connector with testpoints] Driver – Windows NT compatible driver for PCI_LVDS_8T All information provided is Copyright Dynamic Engineering Hardware and Software Design • Manufacturing Services page 46...

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