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DYNAMIC ENGINEERING
150 DuBois St. Suite B/C Santa Cruz CA 95060
831-457-8891
https://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
cPCIBPMC6U
cPCI 6U 4HP 2 Position PMC Compatible Carrier
Previous model with shown
Manual Revision 10p1 6/9/22
Corresponding Hardware: Revision 10
Fab number: 10-2006-0710
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Summary of Contents for Dynamic Engineering cPCIBPMC6U
- Page 1 DYNAMIC ENGINEERING 150 DuBois St. Suite B/C Santa Cruz CA 95060 831-457-8891 https://www.dyneng.com sales@dyneng.com Est. 1988 User Manual cPCIBPMC6U cPCI 6U 4HP 2 Position PMC Compatible Carrier Previous model with shown Manual Revision 10p1 6/9/22 Corresponding Hardware: Revision 10 Fab number: 10-2006-0710...
- Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to...
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Page 3: Table Of Contents
PRODUCT DESCRIPTION DIP SWITCH Settings SW1 DIP SWITCH Settings Interrupts Options Other Signals Other Options PMC Position 0 Rear Panel IO Interface Pin Assignment PMC Position 1 Rear Panel IO Interface Pin Assignment APPLICATIONS GUIDE Interfacing Construction and Reliability Thermal Considerations WARRANTY AND REPAIR Service Policy Out of Warranty Repairs... - Page 4 FIGURE 1 CPCIBPMC6U POSITION O PN4 INTERFACE STANDARD FIGURE 2 CPCIBPMC6U POSITION 1 PN4 INTERFACE STANDARD Embedded Solutions Page 4...
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Page 5: Product Description
• GPIO header option • Rear Panel IO option cPCIBPMC6U is ready to use with the default settings. Just install the PMC(s) onto cPCIBPMC6U and into the system. There are a few settings to optimize performance. Embedded Solutions Page 5... -
Page 6: Dip Switch Settings
3.3V is selected for the secondary side. When ‘closed’ is selected 5V is the VIO definition. The VIO plane is a reference for the IO level. The specification does not prohibit larger current consumption from these pins. The cPCIBPMC6U design utilizes a MOSFET to control the 5V or 3.3V rails onto the VIO plane. -
Page 7: Interrupts
The Bridge supports a GPIO function. A header position is available with the positions clearly marked in the silk-screen. The header is installed by request. Please contact Dynamic Engineering for this option. The 4 bits are terminated with 4.7KΩ to 3.3V. -
Page 8: Other Options
PMC buses. The bridged design has independent VIO definitions between the PMC and the primary bus. This design (cPCIBPMC6U) is the 6U 2 PMC position variant. All optional signals can be isolated or added with resistors located to create short stubs when the signals are not in use. -
Page 9: Pmc Position 0 Rear Panel Io Interface Pin Assignment
J 3 . C 1 J 1 4 . 6 3 P M C _ 0 _ I O 6 4 J 3 . B 1 J 1 4 . 6 4 FIGURE 1 CPCIBPMC6U POSITION O PN4 INTERFACE STANDARD Embedded Solutions Page 9... -
Page 10: Pmc Position 1 Rear Panel Io Interface Pin Assignment
J 5 . B 1 J 2 4 . 6 4 FIGURE 2 CPCIBPMC6U POSITION 1 PN4 INTERFACE STANDARD In the tables above Slot 0 PMC / J3 & Slot 1 PMC / J5 are part of the cPCIBPMC6U design. -
Page 11: Applications Guide
Power all system power supplies from one switch. Connecting external voltage to the cPCIBPMC6U when it is not powered can damage it, as well as the rest of the host system. This problem may be avoided by turning all power supplies on and off at the same time. -
Page 12: Construction And Reliability
Construction and Reliability cPCIBPMC6U is constructed out of 0.062 high temp ROHS compliant material. Gold has been used for plating rather than Tin for improved performance over time. Surface mounted components are used. The connectors are SMT for the PMC bus and through hole [compression fit] for the cPCI. -
Page 13: Warranty And Repair
For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty. Out of Warranty Repairs Out of warranty repairs will be billed on a material and labor basis. -
Page 14: Specifications
Specifications Logic Interfaces: PCI 32 Interface 33/66 Access types: PCI bus accesses CLK rates supported: 33 or 66 MHz PCI clock rates Software Interface: transparent Bridge. Initialization: Selections for VIO, primary and secondary clock rates Interface: PMC front bezel via cPCI bracket. Rear IO option. Dimensions: 6U 4HP Construction:... -
Page 15: Order Information
Add J3, J5 and Jn4 connectors to provide rear -ROHS Add for ROHS processing. Conformal Coating is available as an option. -JTAG Add JTAG header to assembly -GPIO Add GPIO header to assembly All information provided is Copyright Dynamic Engineering Embedded Solutions Page 15...
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